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12.4 Software Standby Mode
In the software standby mode, the system clock stops and chip functions halt, including both CPU
functions and the functions of the on-chip supporting modules. Power consumption is reduced to
an extremely low level. The on-chip supporting modules and their registers are reset to their initial
states, but as long as a minimum necessary voltage supply is maintained (at least 2V), the contents
of the CPU registers and on-chip RAM remain unchanged.
12.4.1 Transition to Software Standby Mode
To enter the software standby mode, set the standby bit (SSBY) in the system control register
(SYSCR) to "1," then execute the SLEEP instruction.
12.4.2 Exit from Software Standby Mode
The chip can be brought out of the software standby mode by an input at one of six pins: NMI,
IRQ
, IRQ
, IRQ
, RES, or STBY.
0
1
2
(1) Recovery by External Interrupt: When an NMI, IRQ
, IRQ
, or IRQ
request signal is
0
1
2
received, the clock oscillator begins operating. After the waiting time set in the system control
register (bits STS2 to STS0), clock pulses are supplied to the CPU and on-chip supporting modules.
The CPU executes the interrupt-handling sequence for the requested interrupt, then returns to the
instruction after the SLEEP instruction. The SSBY bit is not cleared.
See section 12.2, "System Control Register: Power-Down Control Bits," for information about the
STS bits.
(2) Recovery by RES Pin: When the RES pin goes Low, the clock oscillator starts and clock
pulses are supplied to the entire chip. Next, when the RES pin goes High, the CPU begins
executing the reset sequence. The SSBY bit is cleared to "0."
The RES pin must be held Low long enough for the clock to stabilize.
(3) Recovery by STBY Pin: When the STBY pin goes Low, the chip exits from the software
standby mode to the hardware standby mode.
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