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16.1.2 Register Configuration
The on-chip RAM is controlled by the register described in table 16-1.
Table 16-1 RAM Control Register
Name
RAM control register
16.2 RAM Control Register (RAMCR)
Bit
RAME
Initial value
Read/Write
The RAM control register (RAMCR) is an 8-bit register that enables or disable the on-chip RAM.
Bit 7—RAM Enable (RAME): This bit enables or disables the on-chip RAM.
The RAME bit is initialized on the rising edge of the signal. It is not initialized in the software
standby mode.
Bit 7
RAME
Description
0
On-chip RAM is disabled.
1
On-chip RAM is enabled.
Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 1.
16.3 Operation
16.3.1 Expanded Modes (Modes 1, 2, 3, and 4)
If the RAME bit is set to 1, accesses to addresses H'FB80 to H'FF7F are directed to the on-chip
RAM. If the RAME bit is cleared to 0, accesses to addresses H'FB80 to H'FF7F are directed to
the external data bus.
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Abbreviation
RAMCR
7
6
5
—
—
1
1
1
R/W
—
—
R/W
Initial Value
R/W
H'FF
4
3
—
—
1
1
—
—
(Initial value)
292
Address
H'FFF9
2
1
0
—
—
—
1
1
1
—
—
—
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