Interrupt Response Time - Hitachi H8/3672 Series Hardware Manual

SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
Prior to start of interrupt
Legend:
PC H : Upper 8 bits of program counter (PC)
PC L : Lower 8 bits of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
2. Register contents must always be saved and restored by word length, starting from
an even-numbered address.
3. Ignored when returning from the interrupt handling routine.
3.4.4

Interrupt Response Time

Table 3-2 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3-2 Interrupt Wait States
Item
Waiting time for completion of executing instruction*
Saving of PC and CCR to stack
Vector fetch
Instruction fetch
Internal processing
Note: * Not including EEPMOV instruction.
Stack area
PC and CCR
exception handling
saved to stack
Figure 3-2 Stack Status after Exception Handling
SP (R7)
CCR
SP + 1
CCR
SP + 2
PCH
SP + 3
PCL
SP + 4
After completion of interrupt
exception handling
States
1 to 13
4
2
4
4
Rev. 1.0, 03/01, page 51 of 280
*3
Even address
Total
15 to 27