Mark Detection Setting Parameters - Mitsubishi Electric QD77MS User Manual

Setting item
Mark detection
[Pr.800]
signal setting
Mark detection
signal
[Pr.801]
compensation
time
Mark detection
[Pr.802]
data type
Mark detection
[Pr.803]
data axis No.
Mark detection
[Pr.804] data buffer
memory No.
Latch data range
[Pr.805]
upper limit value
Latch data range
[Pr.806]
lower limit value
Mark detection
[Pr.807]
mode setting
The following shows the buffer memory used in the mark detection function.

(1) Mark detection setting parameters

Setting details/setting value
Set the external input signal (high speed input request) for
mark detection.
0 : Invalid
1 to 2 : External command signal of axis 1 to axis 2
(QD77MS2)
1 to 4 : External command signal of axis 1 to axis 4
(QD77MS4)
1 to 16 : External command signal of axis 1 to axis 16
(QD77MS16)
Fetch cycle: Power supply ON
Set the compensation time such as delay of sensor.
Set a positive value to compensate for a delay.
-32768 to 32767[µs]
Fetch cycle: Power supply ON or PLC READY signal [Y0]
OFF to ON
Set the target data for mark detection.
0 to 12 : Data type
-1 : Optional 2 word buffer memory
Fetch cycle: Power supply ON
Set the axis No. of target data for mark detection.
1 to 2 : Axis 1 to axis 2 (QD77MS2)
1 to 4 : Axis 1 to axis 4 (QD77MS4)
1 to 16 : Axis 1 to axis 16 (QD77MS16)
801 to 804 : Synchronous encoder axis 1 to axis 4
Fetch cycle: Power supply ON
Set the optional buffer memory No.
Set this parameter as an even number.
0 to 65534: Optional buffer memory
Fetch cycle: Power supply ON
Set the valid upper limit value for latch data at mark
detection.
-2147483648 to 2147483647
Fetch cycle: Power supply ON, PLC READY signal [Y0]
OFF to ON, or latch data range change request
Set the valid lower limit value for latch data at mark
detection
-2147483648 to 2147483647
Fetch cycle: Power supply ON, PLC READY signal [Y0]
OFF to ON, or latch data range change request
Set the continuous detection mode or specified number of
detection mode.
0 : Continuous detection mode
1 to 32 : Specified number of detection mode
(Set the number of detections.)
-1 to -32 : Ring buffer mode (Set the value that made the
number of buffers into negative value.)
Fetch cycle: Power supply ON or PLC READY signal [Y0]
OFF to ON
14 - 46
Chapter 14 Common Functions
Buffer memory address
Default
QD77MS2
value
QD77MS4
0 54000+20k
0 54001+20k
0 54002+20k
0 54003+20k
54004+20k
0
54005+20k
54006+20k
0
54007+20k
54008+20k
0
54009+20k
0 54010+20k
k: Mark detection setting No.-1
QD77MS16