Mitsubishi Electric QD77MS User Manual page 973

Buffer memory address
QD77MS2
QD77MS16
QD77MS4
54000+20k
54001+20k
54002+20k
54003+20k
54004+20k
54005+20k
54006+20k
54007+20k
54008+20k
54009+20k
54010+20k
54640+10k
54641+10k
54642+10k
54960+80k
54962+80k
54963+80k
54964+80k
54965+80k
54966+80k
54967+80k
to
55024+80k
55025+80k
The following shows the relation between the buffer memory addresses for mark
detection function and the various items.
(Note): Do not use the buffer memory address that not been described here for a
"Maker setting".
Compatibility
of setting value
of QD77MS2/
QD77MS4 and
QD77MS16
[Pr.800] Mark detection signal setting
[Pr.801] Mark detection signal compensation time
[Pr.802] Mark detection data type
[Pr.803] Mark detection data axis No.
[Pr.804] Mark detection data buffer memory No.
[Pr.805] Latch data range upper limit value
[Pr.806] Latch data range lower limit value
[Pr.807] Mark detection mode setting
[Cd.800] Number of mark detection clear request
[Cd.801] Mark detection invalid flag
[Cd.802] Latch data range change request
[Md.800] Number of mark detection
[Md.801] Mark detection data storage area
Item
: Compatible
Appendix - 27
1
2
(1 to 32) 3
to
32
k: Mark detection setting No.-1
: Partly compatible : Not compatible
Appendices
Memory
area
Mark
detection
control data