NXP Semiconductors MPC5644A Reference Manual page 503

Signal Name
Primary WKPCFG
ALT1 NMI
ALT2 DSPI_B_SOUT
GPIO GPIO[213]
1
In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE
bits. Set IBE = 1 for input or OBE = 1 for output.
2
For I/O functions that change direction dynamically, such as the external data bus, switching between input and
output is handled internally and the IBE and OBE bits are ignored.
16.6.15.133Pad Configuration Register 214 (SIU_PCR214)
The SIU_PCR214 register controls the enabling/disabling and drive strength of the ENGCLK pin. The
ENGCLK pin is enabled and disabled by setting and clearing the OBE bit. The ENGCLK pin is enabled
during reset.
SIU_BASE+0x1EC
0 1
R
0 0
W
Reset
0 0
= Unimplemented or Reserved
1
ENGCLK is enabled/disabled by setting/clearing this bit.
Signal Name
Primary ENGCLK
1
In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE
bits. Set IBE = 1 for input or OBE = 1 for output.
2
For I/O functions that change direction dynamically, such as the external data bus, switching between input and
output is handled internally and the IBE and OBE bits are ignored.
Freescale Semiconductor
Table 16-168. SIU_PCR213 PA values
Module
Reset/Config
Reset/Config
DSPI
SIU
2 3 4 5 6
0 0 0 PA OBE
0 0 0 1 1
Figure 16-166. Pad Configuration Register (SIU_PCR214)
Table 16-169. SIU_PCR214 PA values
Module
Clock Generation Engineering clock output O
MPC5644A Microcontroller Reference Manual, Rev. 6
Description
Connects eTPU and eMIOS
pins to internal weak pull-up
or weak pull-down devices
after reset
Non-Maskable interrupt
Output
GPIO
7 8 9 10
1
0 DSC ODE
0 1 1 0
Description
System Integration Unit (SIU)
1,2
I/O PA value
I 0b001
I 0b010
O 0b100
I/O 0b000
11 12 13 14 15
HYS 0 0 WPE WPS
0 0 0 0 0
1,2
I/O PA value
0b001
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