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NXP Semiconductors LPC1768 User Manual

NXP Semiconductors LPC1768 User Manual

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UM10360

LPC17xx User manual

Rev. 00.06 — 5 June 2009

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LPC1768, LPC1766, LPC1765, LPC1764, LPC1758, LPC1756, LPC1754,

LPC1752, LPC1751, ARM, ARM Cortex-M3, 32-bit, USB, Ethernet, CAN,

I2S, Microcontroller

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LPC17xx user manual

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Page 1 UM10360 LPC17xx User manual Rev. 00.06 — 5 June 2009 User manual Document information Info Content Keywords LPC1768, LPC1766, LPC1765, LPC1764, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller Abstract LPC17xx user manual...
Page 2 UM10360 NXP Semiconductors LPC17xx user manual Revision history Date Description <20090212> Preliminary LPC17xx user manual revision, internal. <20090310> Preliminary LPC17xx user manual revision, internal update. <20090430> Preliminary LPC17xx user manual revision, internal update. <20090605> Preliminary LPC17xx user manual revision, first posted version.
Page 3: Chapter 1: Lpc17Xx Introductory Information
UM10360 Chapter 1: LPC17xx Introductory information Rev. 00.06 — 5 June 2009 User manual 1. Introduction The LPC17xx is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation. The ARM Cortex-M3 is a next generation core that offers system enhancements such as modernized debug features and a higher level of support block integration.
Page 4 UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information • Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy.
Page 5: Applications
UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information powered off. Battery power can be supplied from a standard 3 V Lithium button cell. The RTC will continue working when the battery voltage drops to as low as 2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.
Page 6: Ordering Information
UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information • Lighting • Industrial networking • Alarm systems • White goods • Motor control 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC1768FBD100 LPC1766FBD100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm...
Page 7: Simplified Block Diagram
Note: shaded peripheral blocks support General Purpose DMA 20 bytes of backup registers RTC Power Domain Fig 1. LPC1768 simplified block diagram UM10360_0 © NXP B.V. 2009. All rights reserved. User manual Rev. 00.06 — 5 June 2009 7 of 808...
Page 8: Architectural Overview
UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information 6. Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and D-code buses which are faster and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices.
Page 9: On-Chip Flash Memory System
UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information • A JTAG debug interface is included. • Serial Wire Debug is included. Serial Wire Debug allows debug operations using only 2 wires, simple trace functions can be added with a third wire.
Page 10: Block Diagram
General Purpose DMA Vbat ultra-low power Backup registers regulator (20 bytes) RTC Power Domain Fig 2. LPC1768 block diagram, CPU and buses UM10360_0 © NXP B.V. 2009. All rights reserved. User manual Rev. 00.06 — 5 June 2009 10 of 808...
Page 11: Memory Map And Peripheral Addressing
UM10360 Chapter 2: LPC17xx Memory map Rev. 00.06 — 5 June 2009 User manual 1. Memory map and peripheral addressing The ARM Cortex-M3 processor has a single 4 GB address space. The following table shows how this space is used on the LPC17xx. Table 3.
Page 12 APB1 peripherals LPC1768 memory space 0x4010 0000 4 GB 0xFFFF FFFF system control 0x400F C000...
Page 13: Chapter 2: Lpc17Xx Memory Map
UM10360 NXP Semiconductors Chapter 2: LPC17xx Memory map Figure 2–3 Table 2–4 show different views of the peripheral address space. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64 peripherals.
Page 14: Memory Re-Mapping
UM10360 NXP Semiconductors Chapter 2: LPC17xx Memory map Table 5. APB1 peripherals and base addresses APB1 peripheral Base address Peripheral name 0x4008 0000 reserved 0x4008 4000 reserved 0x4008 8000 SSP0 0x4008 C000 0x4009 0000 Timer 2 0x4009 4000 Timer 3...
Page 15 UM10360 NXP Semiconductors Chapter 2: LPC17xx Memory map space) may result in an access to the register defined at address 0x4000 C000. Details of such address aliasing within a peripheral space are not defined in the LPC17xx documentation and are not a supported feature.
Page 16: Chapter 3: Lpc17Xx System Control
UM10360 Chapter 3: LPC17xx System control Rev. 00.06 — 5 June 2009 User manual 1. Introduction The system control block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include: •...
Page 17: Reset
UM10360 NXP Semiconductors Chapter 3: LPC17xx System control Table 7. Summary of system control registers Name Description Access Reset value Address Reset RSID Reset Source Identification Register Table 3–8 0x400F C180 Syscon Miscellaneous Registers System Control and Status 0x00 0x400F C1A0 4.
Page 18 UM10360 NXP Semiconductors Chapter 3: LPC17xx System control On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset, External reset, and Watchdog reset), the IRC starts up. After the IRC-start-up time (maximum of 60 μs on power-up) and after the IRC provides a stable clock output, the reset signal is latched and synchronized on the IRC clock.
Page 19: Reset Source Identification Register (Rsid - 0X400F C180)
UM10360 NXP Semiconductors Chapter 3: LPC17xx System control 4.1 Reset Source Identification Register (RSID - 0x400F C180) This register contains one bit for each source of Reset. Writing a 1 to any of these bits clears the corresponding read-side bit to 0. The interactions among the four sources are described below.
Page 20: External Interrupt Inputs
UM10360 NXP Semiconductors Chapter 3: LPC17xx System control But when Brown-Out Detection is enabled to bring the LPC17xx out of Power-down mode (which is itself not a guaranteed operation -- see Section 4–8.7 “Power Mode Control register (PCON - 0x400F C0C0)”), the supply voltage may recover from a transient before...
Page 21: 0X400F C148)
UM10360 NXP Semiconductors Chapter 3: LPC17xx System control Important: whenever a change of external interrupt operating mode (i.e. active level/edge) is performed (including the initialization of an external interrupt), the corresponding bit in the EXTINT register must be cleared! For details see Section 3–6.3 “External Interrupt Mode register (EXTMODE - 0x400F C148)”...
Page 22: 0X400F C14C)
UM10360 NXP Semiconductors Chapter 3: LPC17xx System control Note: Software should only change a bit in this register when its interrupt is disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the interrupt.
Page 23: Other System Controls And Status Flags
UM10360 NXP Semiconductors Chapter 3: LPC17xx System control Table 12. External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit description Bit Symbol Value Description Reset value EXTPOLAR2 0 EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2). EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2).
Page 24 UM10360 NXP Semiconductors Chapter 3: LPC17xx System control Table 13. System Controls and Status register (SCS - address 0x400F C1A0) bit description Symbol Value Description Access Reset value OSCSTAT Main oscillator status. The main oscillator is not ready to be used as a clock source.
Page 25: Chapter 4: Lpc17Xx Clocking And Power Control
UM10360 Chapter 4: LPC17xx Clocking and power control Rev. 00.06 — 5 June 2009 User manual 1. Summary of clocking and power control functions This section describes the generation of the various clocks needed by the LPC17xx and options of clock source selection, as well as power control and wake-up from reduced power modes.
Page 26: Oscillators
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 14. Summary of system control registers Name Description Access Reset value Address Clock source selection CLKSRCSEL Clock Source Select Register 0x400F C10C Phase Locked Loop (PLL0, Main PLL) PLL0CON...
Page 27: Main Oscillator
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 3.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using PLL0. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL (PLL0).
Page 28: Rtc Oscillator
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 15. Recommended values for C in oscillation mode (crystal and external X1/X2 components parameters) low frequency mode (OSCRANGE = 0, see Table 3–13) Fundamental Crystal load Maximum crystal External load...
Page 29: Clock Source Select Register
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control • The IRC oscillator should not be used (via PLL0) as the clock source for the USB subsystem. • The IRC oscillator should not be used (via PLL0) as the clock source for the CAN controllers if the CAN baud rate is higher than 100 kbit/s.
Page 30: Pll0 And Startup/Boot Code Interaction
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control There are additional dividers at the output of PLL0 to bring the frequency down to what is needed for the CPU, peripherals, and potentially the USB subsystem. PLL0 output dividers are described in the Clock Dividers section following the PLL0 description. A block diagram of PLL0 is shown in Figure 4–8...
Page 31: Pll0 Control Register (Pll0Con - 0X400F C080)
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 18. PLL0 registers Name Description Access Reset Address value PLL0CFG PLL0 Configuration Register. Holding register for 0x400F C084 updating PLL0 configuration values. Values written to this register do not take effect until a valid PLL0 feed sequence has taken place.
Page 32: Pll0 Configuration Register
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 19. PLL Control register (PLL0CON - address 0x400F C080) bit description Symbol Description Reset value PLLE0 PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency.
Page 33 UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 21. Multiplier values for PLL0 with a 32 kHz input Multiplier (M) Pre-divide (N) 4272 279.9698 4395 288.0307 4578 300.0238 4725 309.6576 4807 315.0316 5127 336.0031 5188 340.0008 5400 353.8944...
Page 34: Pll0 Status Register (Pll0Stat - 0X400F C088)
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 21. Multiplier values for PLL0 with a 32 kHz input Multiplier (M) Pre-divide (N) 13672 448.0041 13733 450.0029 13733 300.0020 13916 455.9995 14099 461.9960 14420 315.0097 14648 479.9857 15381 504.0046...
Page 35: Pll0 Interrupt: Plock0
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 22. PLL Status register (PLL0STAT - address 0x400F C088) bit description Symbol Description Reset value 14:0 MSEL0 Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier.
Page 36: Pll0 Feed Register (Pll0Feed - 0X400F C08C)
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 23. PLL control bit combinations PLLC0 PLLE0 PLL Function PLL0 is turned off and disconnected. PLL0 outputs the unmodified clock input. PLL0 is active, but not yet connected. PLL0 can be connected after PLOCK0 is asserted.
Page 37 UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 25. PLL frequency parameter Parameter Description PLL0 Pre-divider value from the NSEL0 bits in the PLL0CFG register (PLL0CFG NSEL0 field + 1). N is an integer from 1 through 32.
Page 38: Procedure For Determining Pll0 Settings
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 5.11 Procedure for determining PLL0 settings PLL0 parameter determination can be simplified by using a spreadsheet available from NXP. To determine PLL0 parameters by hand, the following general procedure may be used: 1.
Page 39 UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Start by assuming N = 1, since this produces the smallest multiplier needed for PLL0. So, M = 288 × 10 / (2 × 4 × 10 ) = 36. Since the result is an integer, there is no need to look further for a good set of PLL0 configuration values.
Page 40: Pll0 Setup Sequence
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Remember that when a frequency below about 1 MHz is used as the PLL0 clock source, not all multiplier values are available. As it turns out, all of the rounded M values found in Table 4–27...
Page 41: Pll1 Register Description
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control PLL1 activation is controlled via the PLL1CON register. PLL1 multiplier and divider values are controlled by the PLL1CFG register. These two registers are protected in order to prevent accidental alteration of PLL1 parameters or deactivation of PLL1. The protection is accomplished by a feed sequence similar to that of the Watchdog Timer.
Page 42: Pll1 Control Register (Pll1Con - 0X400F C0A0)
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control PLLC CLOCK SYNCHRONIZATION direct PSEL[1:0] PLLE bypass PHASE- FREQUENCY PLOCK DETECTOR CCLK DIV-BY-M MSEL<4:0> MSEL[4:0] Fig 9. PLL1 block diagram 6.2 PLL1 Control register (PLL1CON - 0x400F C0A0) The PLL1CON register contains the bits that enable and connect PLL1. Enabling PLL1 allows it to attempt to lock to the current settings of the multiplier and divider values.
Page 43: Pll1 Configuration Register (Pll1Cfg - 0X400F C0A4)
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 29. PLL1 Control register (PLL1CON - address 0x400F C0A0) bit description Symbol Description Reset value PLLE1 PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency.
Page 44: Pll1 Modes
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 31. PLL1 Status register (PLL1STAT - address 0x400F C0A8) bit description Symbol Description Reset value MSEL1 Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1.
Page 45: Pll1 Feed Register (Pll1Feed - 0X400F C0Ac)
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 6.6 PLL1 Feed register (PLL1FEED - 0x400F C0AC) A correct feed sequence must be written to the PLL1FEED register in order for changes to the PLL1CON and PLL1CFG registers to take effect. The feed sequence is: 1.
Page 46: Procedure For Determining Pll1 Settings
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control USBCLK = M × F / (2 × P) or USBCLK = F The CCO frequency can be computed as: = USBCLK × 2 × P or F × M × 2 × P The PLL1 inputs and settings must meet the following criteria: •...
Page 47: Clock Dividers
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 7. Clock dividers The output of the PLL0 must be divided down for use by the CPU and the USB subsystem (if used with PLL0, see Section 4–6). Separate dividers are provided such that the CPU frequency can be determined independently from the USB subsystem, which always requires 48 MHz with a 50% duty cycle for proper operation.
Page 48: Usb Clock Configuration Register (Usbclkcfg - 0X400F C108)
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 7.2 USB Clock Configuration register (USBCLKCFG - 0x400F C108) This register is used only if the USB PLL (PLL1) is not connected (via the PLLC1 bit in PLL1CON). If PLL1 is connected, its output is automatically used as the USB clock source, and PLL1 must be configured to supply the correct 48 MHz clock to the USB subsystem.
Page 49 UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 40. Peripheral Clock Selection register 0 (PCLKSEL0 - address 0x400F C1A8) bit description Symbol Description Reset value PCLK_WDT Peripheral clock selection for WDT. PCLK_TIMER0 Peripheral clock selection for TIMER0.
Page 50: Power Control
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 42. Peripheral Clock Selection register bit values PCLKSEL0 and PCLKSEL1 Function Reset individual peripheral’s clock value select options PCLK_peripheral = CCLK/4 PCLK_peripheral = CCLK PCLK_peripheral = CCLK/2 PCLK_peripheral = CCLK/8 except for CAN1, CAN2, and CAN filtering when “11”...
Page 51: Deep Sleep Mode
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control mode, but may not access the flash memory, which is disabled in order to save power. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.
Page 52: Deep Power-Down Mode
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Upon wake-up from Power-down mode, if the IRC was used before entering Power-down mode, after IRC-start-up time (about 60 μs), the 2-bit IRC timer starts counting and expiring in 4 cycles. Code execution can then be resumed immediately following the expiration of the IRC timer if the code was running from SRAM.
Page 53: Power Mode Control Register (Pcon - 0X400F C0C0)
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 8.7 Power Mode Control register (PCON - 0x400F C0C0) Controls for some reduced power modes and other power related controls are contained in the PCON register, as described in Table 4–44.
Page 54: Encoding Of Reduced Power Modes
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 8.7.1 Encoding of Reduced Power Modes The PM1and PM0 bits in PCON allow entering reduced power modes as needed. The encoding of these bits allows backward compatibility with devices that previously only supported Sleep and Power-down modes.
Page 55 UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Important: valid read from a peripheral register and valid write to a peripheral register is possible only if that peripheral is enabled in the PCONP register! Table 46. Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit...
Page 56: Power Control Usage Notes
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 8.10 Power control usage notes After every reset, the PCONP register contains the value that enables selected interfaces and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper configuring via peripheral dedicated registers, the user’s application might have to access...
Page 57: External Clock Output Pin
UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control External clock output pin For system test and development purposes, any one of several internal clocks may be brought out on the CLKOUT function available on the P1.27 pin, as shown in Figure 4–11.
Page 58 UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 47. Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description Symbol Value Description Reset value CLKOUTDIV Integer value to divide the output clock by, minus one. 0000 Clock is divided by 1.
Page 59: Chapter 5: Lpc17Xx Flash Accelerator
UM10360 Chapter 5: LPC17xx Flash accelerator Rev. 00.06 — 5 June 2009 User manual 1. Introduction The flash accelerator block in the LPC17xx allows maximization of the performance of the Cortex-M3 processor when it is running code from flash memory, while also saving power. The flash accelerator also provides speed and power improvements for data accesses to the flash memory.
Page 60: Flash Programming Issues
UM10360 NXP Semiconductors Chapter 5: LPC17xx Flash accelerator 2.2 Flash programming Issues Since the flash memory does not allow accesses during programming and erase operations, it is necessary for the flash accelerator to force the CPU to wait if a memory access to a flash address is requested while the flash memory is busy with a programming operation.
Page 61: Operation
UM10360 NXP Semiconductors Chapter 5: LPC17xx Flash accelerator Table 49. Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) bit description Symbol Value Description Reset value 15:12 FLASHTIM Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access.
Page 62 UM10360 NXP Semiconductors Chapter 5: LPC17xx Flash accelerator When an Instruction Fetch is not satisfied by existing contents of the buffer array, nor has a prefetch been initiated for that flash line, the CPU will be stalled while a fetch is initiated for the related 128-bit flash line.
Page 63: Chapter 6: Lpc17Xx Nested Vectored Interrupt Controller (Nvic)
UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) Rev. 00.06 — 5 June 2009 User manual 1. Features • Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3 • Tightly coupled interrupt controller provides low interrupt latency •...
Page 64 UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) Table 50. Connection of interrupt sources to the Vectored Interrupt Controller Exception Vector Function Flag(s) Number Offset 0x50 Timer 3 Match 0-3 Capture 0-1 0x54 UART0 Rx Line Status (RLS)
Page 65 UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) Table 50. Connection of interrupt sources to the Vectored Interrupt Controller Exception Vector Function Flag(s) Number Offset 0x80 PLL0 (Main PLL) PLL0 Lock (PLOCK0) 0x84 Counter Increment (RTCCIF) Alarm (RTCALF)
Page 66: Chapter 7: Lpc17Xx Pin Configuration
UM10360 Chapter 7: LPC17xx Pin configuration Rev. 00.06 — 5 June 2009 User manual 1. LPC17xx pin configuration 002aad945_1 Fig 13. LPC176x LQFP100 pin configuration 002aae158 Fig 14. LPC175x LQFP80 pin configuration 1.1 LPC17xx pin description I/O pins on the LPC17xx are 5V tolerant and have input hysteresis unless indicated in the table below.
Page 67 UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 51. Pin description …continued Symbol LQFP LQFP Type Description P0[0] / RD1 / P0[0] — General purpose digital input/output pin. TXD3 / SDA1 RD1 — CAN1 receiver input. TXD3 — Transmitter output for UART3.
Page 68 UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 51. Pin description …continued Symbol LQFP LQFP Type Description P0[8] / I2STX_WS / P0[8] — General purpose digital input/output pin. MISO1 / MAT2[2] I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave.
Page 69 UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 51. Pin description …continued Symbol LQFP LQFP Type Description P0[20] / DTR1 / P0[20] — General purpose digital input/output pin. SCL1 DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal.
Page 70 UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 51. Pin description …continued Symbol LQFP LQFP Type Description P0[28] / SCL0 / P0[28] — General purpose digital input/output pin. Open-drain 5 V tolerant USB_SCL digital I/O pad, compatible with I C-bus specifications for 100 kHz standard mode, 400 kHz Fast Mode, and 1 MHz Fast Mode Plus.
Page 71 UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 51. Pin description …continued Symbol LQFP LQFP Type Description P1[18] / P1[18] — General purpose digital input/output pin. USB_UP_LED / USB_UP_LED — USB GoodLink LED indicator. It is LOW when device is PWM1[1] / CAP1[0] configured (non-control endpoints enabled).
Page 72 UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 51. Pin description …continued Symbol LQFP LQFP Type Description P1[27] / CLKOUT / P1[27] — General purpose digital input/output pin. USB_OVRCR / CLKOUT — Clock output pin. CAP0[1] USB_OVRCR — USB port Over-Current status.
Page 73 UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 51. Pin description …continued Symbol LQFP LQFP Type Description P2[4] / PWM1[5] / P2[4] — General purpose digital input/output pin. DSR1 / PWM1[5] — Pulse Width Modulator 1, channel 5 output.
Page 74 UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 51. Pin description …continued Symbol LQFP LQFP Type Description P2[12] / EINT2 / P2[12] — General purpose digital input/output pin. 5 V tolerant pad with 5 I2STX_WS ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
Page 75 UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 51. Pin description …continued Symbol LQFP LQFP Type Description RSTOUT RSTOUT — This is a 3.3 V pin. A LOW on this pin indicates that the LPC17xx is in a Reset state.
Page 76: Chapter 8: Lpc17Xx Pin Connect Block
UM10360 Chapter 8: LPC17xx Pin connect block Rev. 00.06 — 5 June 2009 User manual 1. How to read this chapter Table 8–52 shows the functions of the PINSEL registers in the LPC17xx. Table 52. Summary of PINSEL registers Register Controls Table PINSEL0...
Page 77: Pin Mode Select Register Values
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block The direction control bit in the GPIO registers is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Each derivative typically has a different pinout and therefore a different set of functions possible for each pin.
Page 78: Register Description
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 55. Open Drain Pin Mode Select register Bits PINMODE_OD0 to Function Value after PINMODE_OD4 Reset Values Pin is in the normal (not open drain) mode. Pin is in the open drain mode.
Page 79: Pin Function Select Register 0 (Pinsel0 - 0X4002 C000)
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 56. Pin Connect Block Register Map Name Description Access Reset Address Value PINMODE_OD3 Open drain mode control register 3 0x4002 C074 PINMODE_OD4 Open drain mode control register 4 0x4002 C078...
Page 80: Pin Function Select Register 2 (Pinsel2 - 0X4002 C008)
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 58. Pin function select register 1 (PINSEL1 - address 0x4002 C004) bit description PINSEL1 Pin name Function when Function Function Function Reset when 01 when 10 when 11 value P0.16 GPIO Port 0.16 RXD1...
Page 81: Pin Function Select Register 3 (Pinsel3 - 0X4002 C00C)
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block 5.4 Pin Function Select Register 3 (PINSEL3 - 0x4002 C00C) The PINSEL3 register controls the functions of the upper half of Port 1. The direction control bit in the FIO1DIR register is effective only when the GPIO function is selected for a pin.
Page 82: Pin Function Select Register 7 (Pinsel7 - 0X4002 C01C)
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 61. Pin function select register 4 (PINSEL4 - address 0x4002 C010) bit description PINSEL4 Pin Function when Function when 01 Function Function when Reset name when 10 value 23:22 P2.11 GPIO Port 2.11...
Page 83: Pin Mode Select Register 0 (Pinmode0 - 0X4002 C040)
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 64. Pin function select register 10 (PINSEL10 - address 0x4002 C028) bit description Symbol Value Description Reset value Reserved. Software should not write 1 to these bits. NA GPIO/TRACE TPIU interface pins control.
Page 84: Pin Mode Select Register 2 (Pinmode2 - 0X4002 C048)
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 66. Pin Mode select register 1 (PINMODE1 - address 0x4002 C044) bit description PINMODE1 Symbol Description Reset value P0.16MODE Port 1 pin 16 control, see P0.00MODE. P0.17MODE Port 1 pin 17 control, see P0.00MODE.
Page 85: Pin Mode Select Register 4 (Pinmode4 - 0X4002 C050)
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 68. Pin Mode select register 3 (PINMODE3 - address 0x4002 C04C) bit description PINMODE3 Symbol Description Reset value P1.16MODE Port 1 pin 16 control, see P0.00MODE. P1.17MODE Port 1 pin 17 control, see P0.00MODE.
Page 86: Pin Mode Select Register 7 (Pinmode7 - 0X4002 C05C)
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block 5.14 Pin Mode select register 7 (PINMODE7 - 0x4002 C05C) This register controls pull-up/pull-down resistor configuration for Port 3 pins 16 to 31. For details see Section 8–4 “Pin mode select register values”.
Page 87: Open Drain Pin Mode Select Register 1
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 72. Open Drain Pin Mode select register 0 (PINMODE_OD0 - address 0x4002 C068) bit description PINMODE Symbol Value Description Reset _OD0 value P0.10OD Port 0 pin 10 open drain mode control, see P0.00OD P0.11OD...
Page 88: Open Drain Pin Mode Select Register 2
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 73. Open Drain Pin Mode select register 1 (PINMODE_OD1 - address 0x4002 C06C) bit description PINMODE Symbol Value Description Reset _OD1 value Reserved. P1.08OD Port 1 pin 8 open drain mode control, see P1.00OD P1.09OD...
Page 89: Open Drain Pin Mode Select Register 3
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 74. Open Drain Pin Mode select register 2 (PINMODE_OD2 - address 0x4002 C070) bit description PINMODE Symbol Value Description Reset _OD2 value P2.05OD Port 2 pin 5 open drain mode control, see P2.00OD P2.06OD...
Page 90: I 2 C Pin Configuration Register (I2Cpadcfg - 0X4002 C07C)
UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 76. Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit description PINMODE Symbol Value Description Reset _OD4 value P4.28OD Port 4 pin 28 open drain mode control.
Page 91: Chapter 9: Lpc17Xx General Purpose Input/Output (Gpio)
UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration GPIOs are configured using the following registers: 1. Power: always enabled. 2. Pins: See Section 8–3 for GPIO pins and their modes. 3.
Page 92: Applications
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) • Registers provide a software view of pending rising edge interrupts, pending falling edge interrupts, and overall pending GPIO interrupts. • GPIO0 and GPIO2 interrupts share the same position in the NVIC with External Interrupt 3.
Page 93 UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 79. GPIO register map (local bus accessible registers - enhanced GPIO features) Generic Description Access Reset PORTn Register Name value Address & Name FIODIR Fast GPIO Port Direction control register. This register FIO0DIR - 0x2009 C000 individually controls the direction of each port pin.
Page 94: Gpio Port Direction Register Fioxdir (Fio0Dir To Fio4Dir- 0X2009 C000 To 0X2009 C080)
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 80. GPIO interrupt register map Generic Access Reset PORTn Register Name value Address & Name IntEnR GPIO Interrupt Enable for Rising edge. IO0IntEnR - 0x4002 8090 IO2IntEnR - 0x4002 80B0 IntEnF GPIO Interrupt Enable for Falling edge.
Page 95: Gpio Port Output Set Register Fioxset
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 82. Fast GPIO port Direction control byte and half-word accessible register description Generic Description Register Reset PORTn Register Register length (bits) value Address & Name name & access FIOxDIR0...
Page 96 UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 83. Fast GPIO port output Set register (FIO0SET to FIO7SET - addresses 0x2009 C018 to 0x2009 C098) bit description Symbol Value Description Reset value 31:0 FP0SET Fast GPIO output value Set bits. Bit 0 in FIOxSET controls pin FP1SET Px.0, bit 31 in FIOxSET controls pin Px.31.
Page 97: Gpio Port Output Clear Register Fioxclr (Fio0Clr To Fio7Clr- 0X2009 C01C To 0X2009 C09C)
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 5.3 GPIO port output Clear register FIOxCLR (FIO0CLR to FIO7CLR- 0x2009 C01C to 0x2009 C09C) This register is used to produce a LOW level output at port pins configured as GPIO in an OUTPUT mode.
Page 98: Gpio Port Pin Value Register Fioxpin (Fio0Pin To Fio7Pin- 0X2009 C014 To 0X2009 C094)
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 86. Fast GPIO port output Clear byte and half-word accessible register description Generic Description Register Reset PORTn Register Register length (bits) value Address & Name name & access FIOxCLR3 Fast GPIO Port x output...
Page 99: Fast Gpio Port Mask Register Fioxmask (Fio0Mask To Fio7Mask - 0X2009 C010 To 0X2009 C090)
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Aside from the 32-bit long and word only accessible FIOxPIN register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 9–88, too. Next to providing the same functions as the FIOxPIN register, these additional registers allow easier and faster access to the physical port pins.
Page 100 UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 89. Fast GPIO port Mask register (FIO0MASK to FIO7MASK - addresses 0x2009 C010 to 0x2009 C090) bit description Symbol Value Description Reset value 31:0 FP0MASK Fast GPIO physical pin access control.
Page 101: Gpio Interrupt Registers
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 5.6 GPIO interrupt registers The following registers configure the pins of Port 0 and Port 2 to generate interrupts. 5.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0x4002 8080) This read-only register indicates the presence of interrupt pending on all of the GPIO ports that support GPIO interrupts.
Page 102: Gpio Interrupt Enable For Port 2 Rising Edge (Io2Intenr - 0X4002 80B0)
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 92. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit description Symbol Value Description Reset value P0.17ER Enable rising edge interrupt for P0.17. P0.18ER Enable rising edge interrupt for P0.18.
Page 103: Gpio Interrupt Enable For Port 0 Falling Edge (Io0Intenf - 0X4002 8094)
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 93. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit description Symbol Value Description Reset value P2.12ER Enable rising edge interrupt for P2.12. P2.13ER Enable rising edge interrupt for P2.13.
Page 104: Gpio Interrupt Enable For Port 2 Falling Edge (Io2Intenf - 0X4002 80B4)
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 94. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094) bit description Symbol Value Description Reset value P0.28EF Enable falling edge interrupt for P0.28. P0.29EF Enable falling edge interrupt for P0.29.
Page 105: Gpio Interrupt Status For Port 2 Rising Edge Interrupt (Io2Intstatr - 0X4002 80A4)
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 96. GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084) bit description Symbol Value Description Reset value P0.0REI Status of Rising Edge Interrupt for P0.0 A rising edge has not been detected on P0.0.
Page 106: Gpio Interrupt Status For Port 0 Falling Edge Interrupt (Io0Intstatf - 0X4002 8088)
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 97. GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4) bit description Symbol Value Description Reset value P2.0REI Status of Rising Edge Interrupt for P2.0 A rising edge has not been detected on P2.0.
Page 107: Gpio Interrupt Status For Port 2 Falling Edge Interrupt (Io2Intstatf - 0X4002 80A8)
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 98. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088) bit description Symbol Value Description Reset value 14:12 - Reserved. P0.15FEI Status of Falling Edge Interrupt for P0.15.
Page 108: Gpio Interrupt Clear Register For Port 0 (Io0Intclr - 0X4002 808C)
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 99. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8) bit description Symbol Value Description Reset value P2.11FEI Status of Falling Edge Interrupt for P2.11.
Page 109: Gpio Interrupt Clear Register For Port 0 (Io2Intclr - 0X4002 80Ac)
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 100. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description Symbol Value Description Reset value P0.27CI Clear GPIO port Interrupts for P0.27. P0.28CI Clear GPIO port Interrupts for P0.28.
Page 110: Writing To Fioset/Fioclr Vs. Fiopin
UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Solution 2: using 16-bit (half-word) accessible fast GPIO registers FIO0MASKL = 0x00FF; FIO0PINL = 0xA500; Solution 3: using 8-bit (byte) accessible fast GPIO registers FIO0PIN1 = 0xA5; 6.2 Writing to FIOSET/FIOCLR vs. FIOPIN Writing to the FIOSET/FIOCLR registers allow a program to easily change a port’s output...
Page 111: Chapter 10: Lpc17Xx Ethernet
UM10360 Chapter 10: LPC17xx Ethernet Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The Ethernet controller is configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bit PCENET. Remark: On reset, the Ethernet block is disabled (PCENET = 0). 2.
Page 112: Features
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 102. Ethernet acronyms, abbreviations, and definitions Acronym or Definition Abbreviation Frame An Ethernet frame consists of destination address, source address, length type field, payload and frame check sequence. Half-word 16-bit entity Local Area Network...
Page 113: Architecture And Operation
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision backoff and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter.
Page 114: Dma Engine Functions
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet – The transmit DMA manager which reads descriptors and data from memory and writes status to memory. – The transmit retry module handling Ethernet retry and abort situations. – The transmit flow control module which can insert Ethernet pause frames.
Page 115: Ethernet Packet
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Hardware in the DMA engine controls how data incoming from the Ethernet MAC is saved to memory, causes fragment related status to be saved, and advances the hardware receive pointer for incoming data. Driver software must handle the disposition of received data, changing of descriptor data addresses (to avoid unnecessary data movement), and advancing the software receive pointer.
Page 116: Overview
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The Ethernet frame consists of the destination address, the source address, an optional VLAN field, the length/type field, the payload and the frame check sequence. Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferred starting with the least significant bit.
Page 117: Example Phy Devices
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block. Receive flow control frames are automatically handled by the MAC. Transmit flow control frames can be initiated by software. In half duplex mode, the flow control module will generate back pressure by sending out continuous preamble only, interrupted by pauses to prevent the jabber limit from being exceeded.
Page 118: Registers And Software Interface
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10. Registers and software interface The software interface of the Ethernet block consists of a register view and the format definitions for the transmit and receive descriptors. These two aspects are addressed in the next two subsections.
Page 119 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 106. Register definitions Symbol Address R/W Description 0x5000 004C to Reserved, user software should not write ones to 0x5000 00FC reserved bits. The value read from a reserved bit is not defined.
Page 120: Ethernet Mac Register Definitions
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 106. Register definitions Symbol Address R/W Description IntEnable 0x5000 0FE4 R/W Interrupt enable register. IntClear 0x5000 0FE8 WO Interrupt clear register. IntSet 0x5000 0FEC WO Interrupt set register. 0x5000 0FF0 Reserved, user software should not write ones to reserved bits.
Page 121: Mac Configuration Register 2 (Mac2 - 0X5000 0004)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 107. MAC Configuration register 1 (MAC1 - address 0x5000 0000) bit description Symbol Function Reset value 13:12 - Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 122: Back-To-Back Inter-Packet-Gap Register (Ipgt - 0X5000 0008)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 108. MAC Configuration register 2 (MAC2 - address 0x5000 0004) bit description Symbol Function Reset value 11:10 Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 123: Collision Window / Retry Register (Clrt - 0X5000 0010)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 111. Non Back-to-back Inter-packet-gap register (IPGR - address 0x5000 000C) bit description Symbol Function Reset value NON-BACK-TO-BACK This is a programmable field representing the Non-Back-to-Back INTER-PACKET-GAP PART2 Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in...
Page 124: Phy Support Register (Supp - 0X5000 0018)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 11.7 PHY Support Register (SUPP - 0x5000 0018) The PHY Support register (SUPP) has an address of 0x5000 0018. The SUPP register provides additional control over the RMII interface. The bit definition of this register is...
Page 125: Mii Mgmt Command Register (Mcmd - 0X5000 0024)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 116. MII Mgmt Configuration register (MCFG - address 0x5000 0020) bit description Symbol Function Reset value 14:6 Unused RESET MII MGMT This bit resets the MII Management hardware. 31:16 Unused Table 117. Clock select encoding...
Page 126: Mii Mgmt Write Data Register (Mwtd - 0X5000 002C)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 119. MII Mgmt Address register (MADR - address 0x5000 0028) bit description Symbol Function Reset value REGISTER This field represents the 5-bit Register Address field of Mgmt ADDRESS cycles. Up to 32 registers can be accessed.
Page 127: Station Address 0 Register (Sa0 - 0X5000 0040)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 122. MII Mgmt Indicators register (MIND - address 0x5000 0034) bit description Symbol Function Reset value NOT VALID When ’1’ is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid.
Page 128: Station Address 2 Register (Sa2 - 0X5000 0048)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 124. Station Address register (SA1 - address 0x5000 0044) bit description Symbol Function Reset value STATION ADDRESS, This field holds the fourth octet of the station address. 4th octet 15:8 STATION ADDRESS, This field holds the third octet of the station address.
Page 129: Status Register (Status - 0X5000 0104)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 126. Command register (Command - address 0x5000 0100) bit description Symbol Function Reset value PassRxFilter When set to ’1’, disables receive filtering i.e. all frames received are written to memory. TxFlowControl Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex.
Page 130: Receive Status Base Address Register (Rxstatus - 0X5000 010C)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 128. Receive Descriptor Base Address register (RxDescriptor - address 0x5000 0108) bit description Symbol Function Reset value Fixed to ’00’ 31:2 RxDescriptor MSBs of receive descriptor base address. The receive descriptor base address is a byte address aligned to a word boundary i.e.
Page 131: Receive Consume Index Register (Rxconsumeindex - 0X5000 0118)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 131. Receive Produce Index register (RxProduceIndex - address 0x5000 0114) bit description Symbol Function Reset value 15:0 RxProduceIndex Index of the descriptor that is going to be filled next by the receive datapath.
Page 132: Transmit Status Base Address Register (Txstatus - 0X5000 0120)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 12.9 Transmit Status Base Address Register (TxStatus - 0x5000 0120) The Transmit Status base address register (TxStatus) has an address of 0x5000 0120. Its bit definition is shown in Table 10–134. Table 134. Transmit Status Base Address register (TxStatus - address 0x5000 0120) bit...
Page 133: Transmit Consume Index Register (Txconsumeindex - 0X5000 012C)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet TxProduceIndex equals TxConsumeIndex - 1 the descriptor array is full and software should stop producing new descriptors until hardware has transmitted some frames and updated the TxConsumeIndex. 12.12 Transmit Consume Index Register (TxConsumeIndex - 0x5000 012C) The Transmit Consume Index register (TxConsumeIndex) is a Read Only register with an address of 0x5000 012C.
Page 134: Transmit Status Vector 1 Register (Tsv1 - 0X5000 015C)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 138. Transmit Status Vector 0 register (TSV0 - address 0x5000 0158) bit description Symbol Function Reset value Excessive Defer Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode.
Page 135: Receive Status Vector Register (Rsv - 0X5000 0160)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 12.15 Receive Status Vector Register (RSV - 0x5000 0160) The Receive status vector register (RSV) is a Read Only register with an address of 0x5000 0160. The receive status vector register stores the most recent receive status returned by the MAC.
Page 136: Flow Control Counter Register (Flowcontrolcounter - 0X5000 0170)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 12.16 Flow Control Counter Register (FlowControlCounter - 0x5000 0170) The Flow Control Counter register (FlowControlCounter) has an address of 0x5000 0170. Table 10–141 lists the bit definitions of the register. Table 141. Flow Control Counter register (FlowControlCounter - address 0x5000 0170) bit...
Page 137: Receive Filter Wol Status Register (Rxfilterwolstatus - 0X5000 0204)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 143. Receive Filter Control register (RxFilterCtrl - address 0x5000 0200) bit description Symbol Function Reset value AcceptPerfectEn When set to ’1’, the frames with a destination address identical to the station address are accepted.
Page 138: Hash Filter Table Lsbs Register (Hashfilterl - 0X5000 0210)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 145. Receive Filter WoL Clear register (RxFilterWoLClear - address 0x5000 0208) bit description Symbol Function Reset value AcceptUnicastWoLClr When a ’1’ is written to one of these bits (0 to 5), the...
Page 139: Module Control Register Definitions
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 14. Module control register definitions 14.1 Interrupt Status Register (IntStatus - 0x5000 0FE0) The Interrupt Status register (IntStatus) is a Read Only register with an address of 0x5000 0FE0. The interrupt status register bit definition is shown in Table 10–148.
Page 140: Interrupt Clear Register (Intclear - 0X5000 0Fe8)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 149. Interrupt Enable register (intEnable - address 0x5000 0FE4) bit description Symbol Function Reset value RxOverrunIntEn Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations. RxErrorIntEn Enable for interrupt trigger on receive errors.
Page 141: Interrupt Set Register (Intset - 0X5000 0Fec)
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 150. Interrupt Clear register (IntClear - address 0x5000 0FE8) bit description Symbol Function Reset value SoftIntClr Writing a ’1’ to one of these bits (12 and/or 13) clears the corresponding status bit in interrupt status register WakeupIntClr IntStatus.
Page 142: Descriptor And Status Formats
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 15. Descriptor and status formats This section defines the descriptor format for the transmit and receive scatter/gather DMA engines. Each Ethernet frame can consist of one or more fragments. Each fragment corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (for receive) and gather (for transmit) multiple fragments for a single Ethernet frame.
Page 143 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet received. The RxConsumeIndex is programmed by software and is the index of the next descriptor that the software receive driver is going to process. When RxProduceIndex == RxConsumeIndex, the receive buffer is empty. When RxProduceIndex ==...
Page 144 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 156. Receive Status HashCRC Word Symbol Description SAHashCRC Hash CRC calculated from the source address. 15:9 Unused 24:16 DAHashCRC Hash CRC calculated from the destination address. 31:25 - Unused The StatusInfo word contains flags returned by the MAC and flags generated by the receive data path reflecting the status of the reception.
Page 145: Transmit Descriptors And Statuses
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Range"...
Page 146 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Two registers, TxConsumeIndex and TxProduceIndex, define the descriptor locations that will be used next by hardware and software. Both register act as counters starting at 0 and wrapping when they reach the value of TxDescriptorNumber. The TxProduceIndex contains the index of the next descriptor that is going to be filled by the software driver.
Page 147: Ethernet Block Functional Description
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The transmit status consists of one word which is the StatusInfo word. It contains flags returned by the MAC and flags generated by the transmit data path reflecting the status of the transmission.
Page 148: Ahb Interface
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet data buffer and receive status is returned in the receive descriptor status word. Optionally an interrupt can be generated to notify software that a packet has been received. Note that the DMA manager will prefetch and buffer up to three descriptors.
Page 149 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The DMA managers work with arrays of frame descriptors and statuses that are stored in memory. The descriptors and statuses act as an interface between the Ethernet hardware and the device driver software. There is one descriptor array for receive frames and one descriptor array for transmit frames.
Page 150 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Ethernet block has finished reading/writing the last descriptor/status of the array (with the highest memory address), the next descriptor/status it reads/writes is the first descriptor/status of the array at the base address of the array.
Page 151: Initialization
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit frames are gathered from multiple fragments in memory and receive frames can be scattered to multiple fragments in memory.
Page 152: Transmit Process
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet After setting up the descriptor arrays, frame buffers need to be allocated for the receive descriptors before enabling the receive data path. The Packet field of the receive descriptors needs to be filled with the base address of the frame buffer of that descriptor.
Page 153 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet been committed to memory, set the Interrupt bit in the descriptor Control field to 1. To have the hardware add a CRC in the frame sequence control field of this Ethernet frame, set the CRC bit in the descriptor.
Page 154 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Update ConsumeIndex Each time the Tx DMA manager commits a status word to memory it completes the transmission of a descriptor and it increments the TxConsumeIndex (taking wrap around into account) to hand the descriptor back to the device driver software. Software can re-use the descriptor for new transmissions after hardware has handed it back.
Page 155 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet LateCollision, ExcessiveCollision, and ExcessiveDefer are ORed together into the Error bit of the Status. Errors are also propagated to the IntStatus register; the TxError bit in the IntStatus register is set in the case of a LateCollision, ExcessiveCollision, ExcessiveDefer, or NoDescriptor error;...
Page 156 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet All of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the IntEnable register. Enabling or disabling does not affect the IntStatus register contents, only the propagation of the interrupt status to the CPU (via the NVIC).
Page 157 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet (0x2008 11F8) to the TxStatus register. The device driver writes the number of descriptors and statuses minus 1(3) to the TxDescriptorNumber register. The descriptors and statuses in the arrays need not be initialized, yet.
Page 158: Receive Process
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Since the Interrupt bit in the descriptor of the last fragment is set, after committing the status of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt, which triggers the device driver to inspect the status information.
Page 159 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet descriptors to be read is determined by the total number of descriptors owned by the hardware: RxConsumeIndex - RxProduceIndex - 1. Block transferring of descriptors minimizes memory load. Read data returned from memory is buffered and consumed as needed.
Page 160 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet packet and then stored in every StatusHashCRC word of the statuses associated with the corresponding fragments. If the reception reports an error, any remaining data in the receive frame is discarded and the LastFrag bit will be set in the receive status field, so the error flags in all but the last fragment of a frame will always be 0.
Page 161 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The receive data path can generate four different interrupt types: • If the Interrupt bit in the descriptor Control field is set, the Rx DMA will set the RxDoneInt bit in the IntStatus register after receiving a fragment and committing the associated data and status to memory.
Page 162 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet RxDescriptor RxStatus 0x200810EC 0x200811F8 FRAGMENT 0 BUFFER (8 bytes) 0x 2008 11F8 StatusInfo 0x200810EC PACKET 0x20081409 StatusHashCRC StatusInfo 0x 2008 1200 0x200810F0 CONTROL StatusHashCRC FRAGMENT 1 BUFFER (8 bytes) 0x200810F4 StatusInfo PACKET 0x 2008 1208...
Page 163 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet continuous memory space; even when a frame is distributed over multiple fragments it will typically be in a linear, continuous memory space; when the descriptors wrap at the end of the descriptor array the frame will not be in a continuous memory space.
Page 164: Transmission Retry
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Each four pairs of bits transferred on the RMII interface are transferred as a byte on the data write interface after being delayed by 128 or 136 cycles for filtering by the receive filter and buffer modules.
Page 165: Duplex Modes
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 17.7 Duplex modes The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex mode needs to be configured by the device driver software during initialization. For a full duplex connection the FullDuplex bit of the Command register needs to be set to 1 and the FULL-DUPLEX bit of the MAC2 configuration register needs to be set to 1;...
Page 166 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the Command register will start a pause frame transmission. The value inserted into the pause-timer value field of transmitted pause frames is programmed via the PauseTimer[15:0] bits in the FlowControlCounter register.
Page 167: Half-Duplex Mode Backpressure
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet device driver PauseTimer clear register MirrorCounter TxFlowCtl TxFlowCtl writes pause control pause control pause control RMII normal frame normal transimisson frame frame transmit transmission transmission transmission transmission MirrorCounter (1/515 bit slots) RMII pause in effect...
Page 168: Receive Filtering
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 17.10 Receive filtering Features of receive filtering The Ethernet MAC has several receive packet filtering functions that can be configured from the software driver: • Perfect address filter: allows packets with a perfectly matching station address to be identified and passed to the software driver.
Page 169 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet packet AcceptUnicastEn AcceptMulticastEn StationAddress IMPERFECT PERFECT AcceptMulticastHashEn HASH ADDRESS AcceptPerfectEn FILTER FILTER AcceptUnicastHashEn HashFilter FMatch RxFilterWoL RxFilterEnWoL RxAbort FReady Fig 22. Receive filter block diagram Unicast, broadcast and multicast Generic filtering based on the type of frame (unicast, multicast or broadcast) can be programmed using the AcceptUnicastEn, AcceptMulticastEn, or AcceptBroadcastEn bits of the RxFilterCtrl register.
Page 170: Power Management
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet • Hash function: – The standard Ethernet cyclic redundancy check (CRC) function is calculated from the 6 byte destination address in the Ethernet frame (this CRC is calculated anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of the 32-bit CRC result are taken to form the hash.
Page 171 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The Ethernet block supports power management with remote wake-up over LAN. The host system can be powered down, even including part of the Ethernet block itself, while the Ethernet block continues to listen to packets on the LAN. Appropriately formed packets can be received and recognized by the Ethernet block and used to trigger the host system to wake up from its power-down state.
Page 172: Enabling And Disabling Receive And Transmit
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet packet only sets the wake-up interrupt status bit if the packet passes the receive filter as illustrated in Figure 10–22: the result of the receive filter is ANDed with the magic packet filter result to produce the result.
Page 173 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet ACTIVE RxStatus = 1 xxxxxxxxxxxxxxxxxx RxEnable = 0 and not busy receiving RxEnable = 1 RxProduceIndex = RxConsumeIndex - 1 INACTIVE RxStatus = 0 reset Fig 23. Receive Active/Inactive state machine After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit is set in the Command register, the state machine transitions to the ACTIVE state.
Page 174: Transmission Padding And Crc
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet ACTIVE TxStatus = 1 xxxxxxxxxxxxxxxxxxxxxx TxEnable = 1 TxEnable = 0 and not busy transmitting TxProduceIndex <> TxConsumeIndex TxProduceIndex = TxConsumeIndex INACTIVE TxStatus = 0 reset Fig 24. Transmit Active/Inactive state machine After reset, the state machine is in the INACTIVE state. As soon as the TxEnable bit is set in the Command register and the Produce and Consume indices are not equal, the state machine transitions to the ACTIVE state.
Page 175: Huge Frames And Frame Length Checking
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet If EPADEN is 1, then small frames will be padded and a CRC will always be added to the padded frames. In this case if ADPEN and VLPEN are both 0, then the frames will be padded to 60 bytes and a CRC will be added creating 64 bytes frames;...
Page 176: Reset
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 17.18 Reset The Ethernet block has a hard reset input which is connected to the chip reset, as well as several soft resets which can be activated by setting the appropriate bit(s) in registers. All registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise specified.
Page 177: Ethernet Errors
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet • RegReset: Resets all of the data paths and registers in the host registers module, excluding the registers in the MAC. A soft reset of the registers will also abort all AHB transactions of the transmit and receive data path. The reset bit will be cleared autonomously by the Ethernet block.
Page 178 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet By making some assumptions, the bandwidth needed for each type of AHB transfer can be calculated and added in order to find the overall bandwidth requirement. The flexibility of the descriptors used in the Ethernet block allows the possibility of defining memory buffers in a range of sizes.
Page 179: Types Of Cpu Access
UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet • Rx data write: – Data to be received in an Ethernet frame, the size is variable. – Basic Ethernet rate = 12.5 Mbps. This gives a total rate of 30.5 Mbps for the traffic generated by the Ethernet DMA function.
Page 180 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet • Generation of the destination and source address hash CRCs. The C pseudocode function below calculates the CRC on a frame taking the frame (without FCS) and the number of bytes in the frame as arguments. The function returns the CRC as a 32-bit integer.
Page 181 UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet For obtaining the destination and source address hash CRCs, this function calculates first both the 32-bit CRCs, then the nine most significant bits from each 32-bit CRC are extracted, concatenated, and written in every StatusHashCRC word of every fragment status.
Page 182: Chapter 11: Lpc17Xx Usb Device Controller
UM10360 Chapter 11: LPC17xx USB device controller Rev. 00.06 — 5 June 2009 User manual 1. How to read this chapter This chapter describes the USB controller which is present on all LPC17xx devices. On some LPC17xx family devices, the USB controller can also be configured for Host or OTG operation instead of device.
Page 183: Features
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 162. USB related acronyms, abbreviations, and definitions used in this chapter Acronym/abbreviation Description Advanced High-performance bus ATLE Auto Transfer Length Extraction Analog Transceiver DMA Descriptor DMA Description Pointer Direct Memory Access...
Page 184: Functional Description
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 163. Fixed endpoint configuration Logical Physical Endpoint type Direction Packet size (bytes) Double buffer endpoint endpoint Control 8, 16, 32, 64 Control 8, 16, 32, 64 Interrupt 1 to 64...
Page 185: Analog Transceiver
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller MASTER USB_CONNECT INTERFACE ENGINE DMA interface (AHB master) USB_D+ EP_RAM SERIAL REGISTER ACCESS INTERFACE INTERFACE CONTROL ENGINE USB_D- USB_UP_LED register EP_RAM interface (4K) (AHB slave) USB DEVICE BLOCK Fig 25. USB device controller block diagram 6.1 Analog transceiver...
Page 186: Dma Engine And Bus Master Interface
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 6.5 DMA engine and bus master interface When enabled for an endpoint, the DMA Engine transfers data between RAM on the AHB bus and the endpoint’s buffer in EP_RAM. A single DMA channel is shared between all endpoints.
Page 187: Pin Description
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Once data has been received or sent, the endpoint buffer can be read or written. How this is accomplished depends on the endpoint’s type and operating mode. The two operating modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode.
Page 188: Power Management Support
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 165. USB device controller clock sources Clock source Description AHB master clock Clock for the AHB master bus interface and DMA AHB slave clock Clock for the AHB slave interface...
Page 189: Remote Wake-Up
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 9.4 Remote wake-up The USB device controller supports software initiated remote wake-up. Remote wake-up involves resume signaling on the USB bus initiated from the device. This is done by clearing the SUS bit in the SIE Set Device Status register. Before writing into the register, all the clocks to the device controller have to be enabled using the USBClkCtrl register.
Page 190: Clock Control Registers
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 166. USB device register map Name Description Access Reset value Address DMA registers USBDMARSt USB DMA Request Status 0x0000 0000 0x5000 C250 USBDMARClr USB DMA Request Clear 0x0000 0000 0x5000 C254...
Page 191: Usb Clock Status Register (Usbclkst - 0X5000 Cff8)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 167. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 192: Usb Device Interrupt Status Register (Usbdevintst - 0X5000 C200)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 169. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description Symbol Description Reset value USB_INT_REQ_LP Low priority interrupt line status. This bit is read only. USB_INT_REQ_HP High priority interrupt line status. This bit is read only.
Page 193: Usb Device Interrupt Enable Register (Usbdevinten - 0X5000 C204)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 171. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description Symbol Description Reset value DEV_STAT Set when USB Bus reset, USB suspend change or Connect change event occurs.
Page 194: Usb Device Interrupt Set Register (Usbdevintset - 0X5000 C20C)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Remark: Before clearing the EP_SLOW or EP_FAST interrupt bits, the corresponding endpoint interrupts in USBEpIntSt should be cleared. USBDevIntClr is a write only register. Table 174. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit allocation...
Page 195: Usb Device Interrupt Priority Register (Usbdevintpri - 0X5000 C22C)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 10.2.6 USB Device Interrupt Priority register (USBDevIntPri - 0x5000 C22C) Writing one to a bit in this register causes the corresponding interrupt to be routed to the USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the USB_INT_REQ_LP interrupt line.
Page 196: Usb Endpoint Interrupt Enable Register (Usbepinten - 0X5000 C234)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 180. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description Symbol Description Reset value EP0RX Endpoint 0, Data Received Interrupt bit. EP0TX Endpoint 0, Data Transmitted Interrupt bit or sent a NAK.
Page 197: Usb Endpoint Interrupt Clear Register (Usbepintclr - 0X5000 C238)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 181. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit allocation Reset value: 0x0000 0000 Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX Symbol EP11TX EP11RX EP10TX...
Page 198: Usb Endpoint Interrupt Set Register (Usbepintset - 0X5000 C23C)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX Table 184. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit description...
Page 199: Endpoint Realization Registers
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 187. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit allocation Reset value: 0x0000 0000 Symbol EP15TX EP15RX EP14TX E14RX EP13TX EP13RX EP12TX EP12RX Symbol EP11TX EP11RX EP10TX...
Page 200: Usb Realize Endpoint Register (Usbreep - 0X5000 C244)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Since all the realized endpoints occupy EP_RAM space, the total EP_RAM requirement is ∑ EPRAMspace n ( ) TotalEPRAMspace where N is the number of realized endpoints. Total EP_RAM space should not exceed 4096 bytes (4 kB, 1 kwords).
Page 201: Usb Endpoint Index Register (Usbepin - 0X5000 C248)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller USBReEp |= (UInt32) ((0x1 << endpt)); /* Load Endpoint index Reg with physical endpoint no.*/ USBEpIn = (UInt32) endpointnumber; /* load the max packet size Register */ USBEpMaxPSize = MPS; /* check whether the EP_RLZED bit in the Device Interrupt Status register is set while (!(USBDevIntSt &...
Page 202: Usb Transfer Registers
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller MPS_EP0 ENDPOINT INDEX MPS_EP31 The Endpoint Index is set via the USBEpIn register. MPS_EP0 to MPS_EP31 are accessed via the USBMaxPSize register. Fig 26. USB MaxPacketSize register array indexing 10.5 USB transfer registers The registers in this group are used for transferring data between endpoint buffers and RAM in Slave mode operation.
Page 203: Usb Transmit Data Register
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 194. USB Receive Packet Length register (USBRxPlen - address 0x5000 C220) bit description Symbol Value Description Reset value PKT_LNGTH - The remaining number of bytes to be read from the currently selected endpoint’s buffer.
Page 204: Sie Command Code Registers
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 196. USB Transmit Packet Length register (USBTxPLen - address 0x5000 C224) bit description Symbol Value Description Reset value PKT_LNGTH - The remaining number of bytes to be written to the 0x000 selected endpoint buffer.
Page 205: Usb Command Data Register (Usbcmddata - 0X5000 C214)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 198. USB Command Code register (USBCmdCode - address 0x5000 C210) bit description Symbol Value Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 206: Usb Dma Request Clear Register (Usbdmarclr - 0X5000 C254)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Symbol EP15 EP14 EP13 EP12 EP11 EP10 Symbol Table 201. USB DMA Request Status register (USBDMARSt - address 0x5000 C250) bit description Symbol Value Description Reset value Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0).
Page 207: Usb Udca Head Register (Usbudcah - 0X5000 C280)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Software can also use this register to initiate a DMA transfer to proactively fill an IN endpoint buffer before an IN token packet is received from the host. USBDMARSet is a write only register.
Page 208: Usb Ep Dma Enable Register (Usbepdmaen - 0X5000 C288)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 10.7.6 USB EP DMA Enable register (USBEpDMAEn - 0x5000 C288) Writing one to a bit to this register will enable the DMA operation for the corresponding endpoint. Writing zero has no effect.The DMA cannot be enabled for control endpoints EP0 and EP1.
Page 209: Usb Dma Interrupt Enable Register (Usbdmainten - 0X5000 C294)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 208. USB DMA Interrupt Status register (USBDMAIntSt - address 0x5000 C290) bit description Symbol Value Description Reset value End of Transfer Interrupt bit. All bits in the USBEoTIntSt register are 0.
Page 210: Usb End Of Transfer Interrupt Clear Register (Usbeotintclr - 0X5000 C2A4)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 210. USB End of Transfer Interrupt Status register (USBEoTIntSt - address 0x5000 C2A0s) bit description Symbol Value Description Reset value Endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request.
Page 211: Usb New Dd Request Interrupt Clear Register (Usbnddrintclr - 0X5000 C2B0)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 10.7.14 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0x5000 C2B0) Writing one to a bit in this register clears the corresponding bit in the USBNDDRIntSt register. Writing zero has no effect. USBNDDRIntClr is a write only register.
Page 212: Usb System Error Interrupt Set Register (Usbsyserrintset - 0X5000 C2C0)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 217. USB System Error Interrupt Clear register (USBSysErrIntClr - address 0x5000 C2BC) bit description Symbol Value Description Reset value Clear endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request. 0...
Page 213 UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller register to request low priority interrupt handling. However, the USBDevIntPri register can route either the FRAME or the EP_FAST bit to the USB_INT_REQ_HP bit in the USBIntSt register. Only one of the EP_FAST and FRAME interrupt events can be routed to the USB_INT_REQ_HP bit.
Page 214 UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller interrupt event on Slave mode from other Endpoints USBEpIntSt USBDevIntSt FRAME EP_FAST EP_SLOW USBDevIntPri[0] USBEpIntEn[n] USBEpIntPri[n] USBDevIntPri[1] ERR_INT USBDMARSt USBIntSt USB_INT_REQ_HP to NVIC USB_INT_REQ_LP USB_INT_REQ_DMA to DMA engine EN_USB_INTS USBEoTIntST DMA Mode...
Page 215: Serial Interface Engine Command Description
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 12. Serial interface engine command description The functions and registers of the Serial Interface Engine (SIE) are accessed using commands, which consist of a command code followed by optional data bytes (read or write action).
Page 216: Set Address (Command: 0Xd0, Data: Write 1 Byte)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 219. SIE command code table Command name Recipient Code (Hex) Data phase Device commands Set Address Device Write 1 byte Configure Device Device Write 1 byte Set Mode Device Write 1 byte...
Page 217: Set Mode (Command: 0Xf3, Data: Write 1 Byte)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 221. Configure Device Register bit description Symbol Description Reset value CONF_DEVICE Device is configured. All enabled non-control endpoints will respond. This bit is cleared by hardware when a bus reset occurs. When set, the UP_LED signal is driven LOW if the device is not in the suspended state (SUS=0).
Page 218: Read Current Frame Number (Command: 0Xf5, Data: Read 1 Or 2 Bytes)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 12.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes) Returns the frame number of the last successfully received SOF. The frame number is eleven bits wide. The frame number returns least significant byte first. In case the user is only interested in the lower 8 bits of the frame number, only the first byte needs to be read.
Page 219: Get Device Status (Command: 0Xfe, Data: Read 1 Byte)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 223. Set Device Status Register bit description Bit Symbol Value Description Reset value SUS_CH Suspend (SUS) bit change indicator. The SUS bit can toggle because: • The device goes into the suspended state.
Page 220: Read Error Status (Command: 0Xfb, Data: Read 1 Byte)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 224. Get Error Code Register bit description Symbol Value Description Reset value Error Code. 0000 No Error. 0001 PID Encoding Error. 0010 Unknown PID. 0011 Unexpected Packet - any packet sequence violation from the specification.
Page 221: Select Endpoint (Command: 0X00 - 0X1F, Data: Read 1 Byte (Optional))
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 12.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional)) The Select Endpoint command initializes an internal pointer to the start of the selected buffer in EP_RAM. Optionally, this command can be followed by a data read, which returns some additional information on the packet(s) in the endpoint buffer(s).
Page 222: Select Endpoint/Clear Interrupt (Command: 0X40 - 0X5F, Data: Read 1 Byte)
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 226. Select Endpoint Register bit description Bit Symbol Value Description Reset value B_2_FULL The buffer 2 status. Buffer 2 is empty. Buffer 2 is full. Reserved, user software should not write ones to reserved bits.
Page 223: Clear Buffer (Command: 0Xf2, Data: Read 1 Byte (Optional))
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 227. Set Endpoint Status Register bit description Bit Symbol Value Description Reset value Disabled endpoint bit. The endpoint is enabled. The endpoint is disabled. RF_MO Rate Feedback Mode. Interrupt endpoint is in the Toggle mode.
Page 224: Usb Device Controller Initialization
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the Validate Buffer command and cleared when the data has been sent on the USB bus and the buffer is empty.
Page 225: Slave Mode Operation
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller – Write the desired address for the UDCA to USBUDCAH (for example 0x7FD0 0000). – Enable the desired endpoints for DMA operation using USBEpDMAEn. – Set EOT, DDR, and ERR bits in USBDMAIntEn.
Page 226: Data Transfer For In Endpoints
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller If the software clears RD_EN before the entire packet is read, reading is terminated, and the data remains in the endpoint’s buffer. When RD_EN is set again for this endpoint, the data will be read from the beginning.
Page 227: Usb Device Communication Area
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 15.2 USB device communication area The CPU and DMA controller communicate through a common area of memory, called the USB Device Communication Area, or UDCA. The UDCA is a 32-word array of DMA Descriptor Pointers (DDPs), each of which corresponds to a physical endpoint.
Page 228: The Dma Descriptor
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command (Section 11–12.3).
Page 229: Next_Dd_Pointer
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 229. DMA descriptor Word Access Access Description position (H/W) (S/W) position DD_retired (To be initialized to 0) DD_status (To be initialized to 0000): 0000 - NotServiced 0001 - BeingServiced 0010 - NormalCompletion...
Page 230: Dma_Buffer_Length
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 15.4.6 DMA_buffer_length This indicates the depth of the DMA buffer allocated for transferring the data. The DMA engine will stop using this descriptor when this limit is reached and will look for the next descriptor.
Page 231: Ls_Byte_Extracted
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 15.4.11 LS_byte_extracted Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of the transfer length has been extracted. The extracted size is reflected in the DMA_buffer_length field, bits 23:16.
Page 232: Transferring The Data
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller If a new descriptor has to be read, the DMA engine will calculate the location of the DDP for this endpoint and will fetch the start address of the DD from this location. A DD start address at location zero is considered invalid.
Page 233: No_Packet Dd
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller USB transfer end completion - If the current packet is fully transferred and its size is less than the Max_packet_size field, and the end of the DMA buffer is still not reached, the USB transfer end completion occurs.
Page 234: Dma Descriptor Completion
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller The isochronous packet size is stored in memory as shown in Figure 11–29. Each word in the packet size memory shown is divided into fields: Frame_number (bits 31 to 17), Packet_valid (bit 16), and Packet_length (bits 15 to 0). The space allocated for the packet size memory for a given DD should be DMA_buffer_length words in size –...
Page 235: Auto Length Transfer Extraction (Atle) Mode Operation
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Next_DD_Pointer NULL DMA_buffer_length Max_packet_size Isochronous_endpoint Next_DD_Valid DMA_mode 0x000A DMA_buffer_start_addr 0x80000000 Present_DMA_Count ATLE settings Packet_Valid DD_Status DD_Retired Isocronous_packetsize_memory_address 0x60000000 after 4 packets 0x000A0010 FULL 0x80000035 frame_ number Packet_Valid Packet_Length EMPTY 0x60000010 data memory packet size memory Fig 29.
Page 236 UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller data to be sent data in packets data to be stored in by host driver as seen on USB RAM by DMA engine DMA_buffer_start_addr 160 bytes 64 bytes of DD1 160 bytes...
Page 237: Setting Up The Dma Transfer
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller In ATLE mode, the last buffer length to be transferred always ends with a short or empty packet indicating the end of the USB transfer. If the concatenated transfer lengths are such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host will send an empty packet to mark the end of the USB transfer.
Page 238: Ending The Packet Transfer
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 15.7.4 Ending the packet transfer The DMA engine proceeds with the transfer until the number of bytes specified in the field DMA_buffer_length is transferred to or from on-chip RAM. Then the EOT interrupt will be generated.
Page 239 UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 5. Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit. Software finds that the active buffer (B_2) has data (FE=1). Software clears the endpoint interrupt and begins reading the contents of B_2.
Page 240: Isochronous Endpoints
UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by software will go into B_2. In DMA mode, switching of the active buffer is handled automatically in hardware. For...
Page 241: Chapter 12: Lpc17Xx Usb Host Controller
Rev. 00.06 — 5 June 2009 User manual 1. How to read this chapter The USB host controller is available on the LPC1768, LPC1766, LPC1765, LPC1758, LPC1756, and LPC1754. On these devices, the USB controller can be configured for device, Host, or OTG operation.
Page 242: Features
UM10360 NXP Semiconductors Chapter 12: LPC17xx USB Host controller Table 230. USB (OHCI) related acronyms and abbreviations used in this chapter Acronym/abbreviation Description Low Speed OHCI Open Host Controller Interface Universal Serial Bus 3.1 Features • OHCI compliant. • OpenHCI specifies the operation and interface of the USB Host Controller and SW Driver –...
Page 243: Pin Description
UM10360 NXP Semiconductors Chapter 12: LPC17xx USB Host controller 4.1 Pin description Table 231. USB Host port pins Pin name Direction Description Type USB_D+ Positive differential data USB Connector USB_D − Negative differential data USB Connector USB_UP_LED GoodLink LED control signal...
Page 244: Usb Host Register Definitions
UM10360 NXP Semiconductors Chapter 12: LPC17xx USB Host controller Table 232. USB Host register address definitions …continued Name Address Function Reset value HcControlHeadED 0x5000 C020 Contains the physical address of the first endpoint descriptor of the control list. HcControlCurrentED 0x5000 C024...
Page 245: Chapter 13: Lpc17Xx Usb Otg Controller
Rev. 00.06 — 5 June 2009 User manual 1. How to read this chapter The USB OTG controller is available in the LPC1768, LPC1766, LPC1765, LPC1758, LPC1756, and LPC1754. On these devices, the USB controller can be configured for device, Host, or OTG operation.
Page 246: Architecture
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller 5. Architecture The architecture of the USB OTG controller is shown below in the block diagram. The host, device, OTG, and I C controllers can be programmed through the register interface. The OTG controller enables dynamic switching between host and device roles through the HNP protocol.
Page 247: Connecting The Usb Port To An External Otg Transceiver
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller Table 233. USB OTG port pins Pin name Direction Description Pin category USB_D+ Positive differential data USB Connector USB_D − Negative differential data USB Connector USB_UP_LED GoodLink LED control signal Control...
Page 248: Connecting Usb As A Host
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller 7.2 Connecting USB as a host The USB port is connected as host using an embedded USB transceiver. There is no OTG functionality on the port. USB_UP_LED 33 Ω USB_D+ 33 Ω...
Page 249: Usb Interrupt Status Register (Usbintst - 0X5000 C1C0)
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller Table 234. USB OTG and I C register address definitions Name Address Access Function Interrupt register USBIntSt 0x400F C1C0 R/W USB Interrupt Status OTG registers OTGIntSt 0x5000 C100 OTG Interrupt Status...
Page 250: Otg Interrupt Status Register (Otgintst - 0X5000 C100)
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller Table 235. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit description Symbol Description Reset Value USB_NEED_CLK USB need clock indicator. This bit is read only. 30:9 Reserved, user software should not write ones to reserved bits.
Page 251: Otg Status And Control Register (Otgstctrl - 0X5000 C110)
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller 8.6 OTG Status and Control Register (OTGStCtrl - 0x5000 C110) The OTGStCtrl register allows enabling hardware tracking during the HNP hand over sequence, controlling the OTG timer, monitoring the timer count, and controlling the functions mapped to port U1 and U2.
Page 252: Otg Clock Control Register
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller Table 237. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description Symbol Description Reset Value PU_REMOVED When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+...
Page 253: Otg Clock Status Register
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller Table 239. OTG clock control register (OTG_clock_control - address 0x5000 CFF4) bit description Symbol Value Description Reset Value AHB_CLK_EN AHB master clock enable Disable the AHB clock. Enable the AHB clock.
Page 254: I2C Transmit Register (I2C_Tx - 0X5000 C300)
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller Table 241. I C Receive register (I2C_RX - address 0x5000 C300) bit description Symbol Description Reset Value RX Data Receive data. 8.11 I C Transmit Register (I2C_TX - 0x5000 C300) This register is the top byte of the transmit FIFO. The transmit FIFO is 4 bytes deep.
Page 255 UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller Table 243. I C status register (I2C_STS - address 0x5000 C304) bit description Symbol Value Description Reset Value No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received.
Page 256: I2C Control Register (I2C_Ctl - 0X5000 C308)
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller Table 243. I C status register (I2C_STS - address 0x5000 C304) bit description Symbol Value Description Reset Value Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.
Page 257: I2C Clock High Register (I2C_Clkhi - 0X5000 C30C)
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller Table 244. I C Control register (I2C_CTL - address 0x5000 C308) bit description Symbol Value Description Reset Value RFDAIE Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e.
Page 258: Hnp Support
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller C related interrupts are set in the I2C_STS register and routed, if enabled by I2C_CTL, to the USB_I2C_INT bit. For more details on the interrupts created by device controller, see the USB device chapter.
Page 259: B-Device: Peripheral To Host Switching
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller The OTG software stack is responsible for implementing the HNP state machines as described in the On-The-Go Supplement to the USB 2.0 Specification. The OTG controller hardware provides support for some of the state transitions in the HNP state machines as described in the following subsections.
Page 260 UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller idle B_HNP_TRACK = 0 B_HNP_TRACK = 1 ? set HNP_FAILURE, clear B_HNP_TRACK, clear PU_REMOVED bus suspended ? disconnect device controller from U1 PU_REMOVED set? set REMOVE_PU PU_REMOVED set? reconnect port U1 to the...
Page 261 UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller b_peripheral when host sends SET_FEATURE with b_hnp_enable, set B_HNP_TRACK REMOVE_PU set? remove D+ pull-up, set PU_REMOVED go to go to b_wait_acon b_peripheral HNP_FAILURE set? add D+ pull-up HNP_SUCCESS set? go to b_host Fig 39.
Page 262: A-Device: Host To Peripheral Hnp Switching
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Add D+ pull-up /* Add D+ pull-up through ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x006;...
Page 263 UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller idle A_HNP_TRACK = 0 A_HNP_TRACK = 1 ? set HNP_FAILURE, clear A_HNP_TRACK disconnect host controller from U1 bus suspended ? resume detected ? connnect host controller back to U1 bus reset detected?
Page 264 UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller a_host when host sends SET_FEATURE with a_hnp_enable, set A_HNP_TRACK set BDIS_ACON_EN in external OTG transceiver load and enable OTG timer suspend host on port 1 go to a_suspend TMR set? HNP_SUCCESS set?
Page 265 UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller Set BDIS_ACON_EN in external OTG transceiver /* Set BDIS_ACON_EN in ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x004; // Send Mode Control 1 (Set) register address OTG_I2C_TX = 0x210;...
Page 266: Clocking And Power Management
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller Load and enable OTG timer /* The following assumes that the OTG timer has previously been */ /* configured for a time scale of 1 ms (TMR_SCALE = “10”) /* and monoshot mode (TMR_MODE = 0)
Page 267: Device Clock Request Signals
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller ahb_slave_clk cclk REGISTER PCUSB INTERFACE ahb_master_clk CLOCK SWITCH AHB_CLK_ON ahb_need_clk AHB_CLK_EN CLOCK dev_dma_need_clk DEVICE USB CLOCK SWITCH CONTROLLER DIVIDER usbclk dev_need_clk DEV_CLK_ON (48 MHz) DEV_CLK_EN CLOCK host_dma_need_clk HOST SWITCH CONTROLLER host_need_clk...
Page 268: Host Clock Request Signals
UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller The dev_dma_need_clk signal is asserted on any Device controller DMA access to memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA throughput is not affected by any latency associated with re-enabling ahb_master_clk.
Page 269 UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG controller 4. Enable the desired USB pin functions by writing to the corresponding PINSEL registers. 5. Follow the appropriate steps in Section 11–13 “USB device controller initialization” initialize the device controller. 6. Follow the guidelines given in the OpenHCI specification for initializing the host controller.
Page 270: Chapter 14: Lpc17Xx Uart0/2/3
UM10360 Chapter 14: LPC17xx UART0/2/3 Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The UART0/2/3 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bits PCUART0/2/3. Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled (PCUART2/3 = 0).
Page 271: Register Description
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 4. Register description Each UART contains registers as shown in Table 14–248. The Divisor Latch Access Bit (DLAB) is contained in UnLCR7 and enables access to the Divisor Latches. UM10360_0 © NXP B.V. 2009. All rights reserved.
Page 272 UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 248. UART Register Map Generic Description Access Reset UARTn Register Name value Name & Address Receiver Buffer Register. Contains the next received U0RBR - 0x4000 C000 (DLAB =0) character to be read.
Page 273: Uartn Receiver Buffer Register (U0Rbr - 0X4000 C000, U2Rbr - 0X4009 8000, U3Rbr - 0X4009 C000 When Dlab = 0, Read Only)
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 14.4.1 UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR - 0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0, Read Only) The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface.
Page 274: Uartn Interrupt Enable Register (U0Ier - 0X4000 C004, U2Ier - 0X4009 8004, U3Ier - 0X4009 C004 When Dlab = 0)
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 UnLCR must be one in order to access the UARTn Divisor Latches. Details on how to select the right value for U1DLL and U1DLM can be found later in this chapter, see Section 14–4.12.
Page 275: Uartn Interrupt Identification Register (U0Iir - 0X4000 C008, U2Iir - 0X4009 8008, U3Iir - 0X4009 C008, Read Only)
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 4.5 UARTn Interrupt Identification Register (U0IIR - 0x4000 C008, U2IIR - 0x4009 8008, U3IIR - 0x4009 C008, Read Only) The UnIIR provides a status code that denotes the priority and source of a pending interrupt.
Page 276 UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls below the trigger level.
Page 277: Uartn Fifo Control Register (U0Fcr - 0X4000 C008, U2Fcr - 0X4009 8008, U3Fcr - 0X4009 C008, Write Only)
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 THRE = 1 and there have not been at least two characters in the UnTHR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to UnTHR without a THRE interrupt to decode and service.
Page 278: Uartn Line Control Register (U0Lcr - 0X4000 C00C, U2Lcr - 0X4009 800C, U3Lcr - 0X4009 C00C)
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 UART receiver DMA In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO level becoming equal to or greater than trigger level, or if a character timeout occurs. See the description of the RX Trigger Level above.
Page 279 UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 258: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014, Read Only) bit description Bit Symbol Value Description Reset Value Receiver UnLSR0 is set when the UnRBR holds an unread character Data Ready and is cleared when the UARTn RBR FIFO is empty.
Page 280: Uartn Scratch Pad Register (U0Scr - 0X4000 C01C, U2Scr - 0X4009 801C U3Scr - 0X4009 C01C)
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 258: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014, Read Only) bit description Bit Symbol Value Description Reset Value Transmitter TEMT is set when both UnTHR and UnTSR are empty; TEMT...
Page 281: Auto-Baud
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 260: UARTn Auto-baud Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR - 0x4009 C020) bit description Symbol Value Description Reset value AutoRestart 0 No restart. Restart in case of time-out (counter restarts at next...
Page 282: Auto-Baud Modes
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 any write to UnDLM and UnDLL registers should be done before UnACR register write. The minimum and the maximum baud rates supported by UARTn are function of pclk, number of data bits, stop bits and parity bits.
Page 283: Uartn Irda Control Register (U0Icr - 0X4000 C024, U2Icr - 0X4009 8024, U3Icr - 0X4009 C024)
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' U0ACR start rate counter 16xbaud_rate 16 cycles 16 cycles a.
Page 284: Uartn Fractional Divider Register (U0Fdr - 0X4000 C028, U2Fdr - 0X4009 8028, U3Fdr - 0X4009 C028)
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 261: UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit description Symbol Value Description Reset value IrDAEn IrDA mode on UARTn is disabled, UARTn acts as a standard UART.
Page 285: Baud Rate Calculation
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 263: UARTn Fractional Divider Register (U0FDR - address 0x4000 C028, U2FDR - 0x4009 8028, U3FDR - 0x4009 C028) bit description Function Value Description Reset value DIVADDVAL Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate.
Page 286 UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an True integer? DIVADDVAL = 0 False MULVAL = 1 = 1.5 Pick another FR from = Int(PCLK/(16 x BR x FR the range [1.1, 1.9]...
Page 287: Uartn Transmit Enable Register (U0Ter - 0X4000 C030, U2Ter - 0X4009 8030, U3Ter - 0X4009 C030)
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 264. Fractional Divider setting look-up table DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.000 1.250 1.500 1.750 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778...
Page 288: Uartn Fifo Level Register (U0Fifolvl - 0X4000 C058, U2Fifolvl - 0X4009 8058, U3Fifolvl - 0X4009 C058, Read Only)
UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 14–265 describes how to use TXEn bit in order to achieve software flow control. Table 265: UARTn Transmit Enable Register (U0TER - address 0x4000 C030, U2TER - 0x4009 8030, U3TER - 0x4009 C030) bit description...
Page 289 UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 The UARTn Baud Rate Generator block, UnBRG, generates the timing enables used by the UARTn TX block. The UnBRG clock input source is the APB clock (PCLK). The main clock is divided down per the divisor specified in the UnDLL and UnDLM registers. This divided down clock is a 16x oversample clock, NBAUDOUT.
Page 290 UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 TX DMA CLR UnTX TX DMA REQ TXDn UnTHR UnTSR NTXRDY UnBRG UnDLL NBAUDOUT UnDLM RCLK RX DMA CLR UnRX RX DMA REQ INTERRUPT RXDn UnRBR UnRSR NRXRDY UnIER UnINTR UnIIR UnFCR UnLSR...
Page 291: Chapter 15: Lpc17Xx Uart1
UM10360 Chapter 15: LPC17xx UART1 Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The UART1 peripheral is configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bits PCUART1. Remark: On reset, UART1 is enabled (PCUART1 = 1). 2.
Page 292: Pin Description
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 3. Pin description Table 267: UART1 Pin Description Type Description RXD1 Input Serial Input. Serial receive data. TXD1 Output Serial Output. Serial transmit data. CTS1 Input Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via TXD1 from the UART1.
Page 293: Register Description
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 4. Register description UART1 contains registers organized as shown in Table 15–268. The Divisor Latch Access Bit (DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches. Table 268: UART1 register map...
Page 294: Uart1 Receiver Buffer Register (U1Rbr - 0X4001 0000, When Dlab = 0, Read Only)
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 4.1 UART1 Receiver Buffer Register (U1RBR - 0x4001 0000, when DLAB = 0, Read Only) The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface.
Page 295: Uart1 Interrupt Enable Register (U1Ier - 0X4001 0004, When Dlab = 0)
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 271: UART1 Divisor Latch LSB Register (U1DLL - address 0x4001 0000 when DLAB = 1) bit description Symbol Description Reset Value DLLSB The UART1 Divisor Latch LSB Register, along with the U1DLM 0x01 register, determines the baud rate of the UART1.
Page 296: Uart1 Interrupt Identification Register (U1Iir - 0X4001 0008, Read Only)
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 273: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description Symbol Value Description Reset Value If auto-cts mode is enabled this bit enables/disables the Interrupt modem status interrupt generation on a CTS1 signal Enable transition.
Page 297 UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 274: UART1 Interrupt Identification Register (U1IIR - address 0x4001 0008, Read Only) bit description Symbol Value Description Reset Value IntId Interrupt identification. U1IER[3:1] identifies an interrupt corresponding to the UART1 Rx FIFO. All other combinations of U1IER[3:1] not listed below are reserved (100,101,111).
Page 298 UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 wished to send a 105 character message and the trigger level was 10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters.
Page 299: Uart1 Fifo Control Register (U1Fcr - 0X4001 0008, Write Only)
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 It is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem input RI will generate a modem interrupt. The source of the modem interrupt can be determined by examining U1MSR[3:0].
Page 300: Uart1 Line Control Register (U1Lcr - 0X4001 000C)
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 UART transmitter DMA In DMA mode, the transmitter DMA request is asserted on the event of the transmitter FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA controller.
Page 301: Auto-Flow Control
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 278: UART1 Modem Control Register (U1MCR - address 0x4001 0010) bit description Symbol Value Description Reset value Loopback The modem loopback mode provides a mechanism to perform Mode diagnostic loopback testing. Serial data from the transmitter is Select connected internally to serial input of the receiver.
Page 302: Auto-Cts
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Example: Suppose the UART1 operating in ‘550 mode has trigger level in U1FCR set to 0x2 then if Auto-RTS is enabled the UART1 will de-assert the RTS1 output as soon as the receive FIFO contains 8 bytes (Table 15–276 on page...
Page 303: Uart1 Line Status Register (U1Lsr - 0X4001 0014, Read Only)
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 UART1 TX start bits0..7 stop start bits0..7 stop start bits0..7 stop CTS1 pin Fig 47. Auto-CTS Functional Timing While starting transmission of the initial character the CTS1 signal is asserted. Transmission will stall as soon as the pending transmission has completed. The UART will continue transmitting a 1 bit as long as CTS1 is de-asserted (high).
Page 304: Uart1 Modem Status Register (U1Msr - 0X4001 0018, Read Only)
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 280: UART1 Line Status Register (U1LSR - address 0x4001 0014, Read Only) bit description Bit Symbol Value Description Reset Value Framing When the stop bit of a received character is a logic 0, a framing Error error occurs.
Page 305: Uart1 Scratch Pad Register (U1Scr - 0X4001 001C)
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 281: UART1 Modem Status Register (U1MSR - address 0x4001 0018, Read Only) bit description Bit Symbol Value Description Reset Value Delta Set upon state change of input CTS. Cleared on an U1MSR read.
Page 306: Auto-Baud
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 283: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description Symbol Value Description Reset value Start This bit is automatically cleared after auto-baud completion. Auto-baud stop (auto-baud is not running). Auto-baud start (auto-baud is running). Auto-baud run bit.
Page 307: Auto-Baud Modes
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 The U1ACR AutoRestart bit can be used to automatically restart baud-rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate measurement will restart at the next falling edge of the UART1 Rx pin.
Page 308: Uart1 Fractional Divider Register (U1Fdr - 0X4001 0028)
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 5. If Mode = 0 then the rate counter will stop on next falling edge of the UART1 Rx pin. If Mode = 1 then the rate counter will stop on the next rising edge of the UART1 Rx pin.
Page 309: Baud Rate Calculation
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 284: UART1 Fractional Divider Register (U1FDR - address 0x4001 0028) bit description Function Value Description Reset value DIVADDVAL Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate.
Page 310 UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an True integer? DIVADDVAL = 0 False MULVAL = 1 = 1.5 Pick another FR from = Int(PCLK/(16 x BR x FR the range [1.1, 1.9]...
Page 311: Uart1 Transmit Enable Register (U1Ter - 0X4001 0030)
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 285. Fractional Divider setting look-up table DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.000 1.250 1.500 1.750 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778...
Page 312: Uart1 Rs485 Control Register (U1Rs485Ctrl - 0X4001 004C)
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Although Table 15–286 describes how to use TxEn bit in order to achieve hardware flow control, it is strongly suggested to let UART1 hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control.
Page 313: Uart1 Rs-485 Address Match Register
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 287: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description Symbol Value Description Reset value OINV This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
Page 314 UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 RS-485/EIA-485 Normal Multidrop Mode (NMM) Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt.
Page 315: Uart1 Fifo Level Register (U1Fifolvl - 0X4001 0058, Read Only)
UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time can be programmed in the 8-bit RS485DLY register. The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be programmed.
Page 316 UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 The interrupt interface contains registers U1IER and U1IIR. The interrupt interface receives several one clock wide enables from the U1TX and U1RX blocks. Status information from the U1TX and U1RX is stored in the U1LSR. Control information for the U1TX and U1RX is stored in the U1LCR.
Page 317: Chapter 16: Lpc17Xx Can1/2
UM10360 Chapter 16: LPC17xx CAN1/2 Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The CAN1/2 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bits PCAN1/2. Remark: On reset, the CAN1/2 blocks are disabled (PCAN1/2 = 0). 2.
Page 318: Can Controller Features
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 • Guaranteed latency time for high priority messages. • Programmable transfer rate (up to 1 Mbit/s). • Multicast and broadcast message facility. • Data length from 0 up to 8 bytes. • Powerful error handling capability.
Page 319: Apb Interface Block (Aib)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 • Nested Vectored Interrupt Controller (NVIC) • CAN Transceiver • Common Status Registers INTERFACE CAN CORE APB BUS MANAGEMENT BLOCK LOGIC ERROR MANAGEMENT TRANSCEIVER NVIC LOGIC TRANSMIT BUFFERS 1,2 AND 3 COMMON TIMING...
Page 320: Receive Buffer (Rxb)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 24 23 16 15 Frame info unused TX DLC unused TX Priority Descriptor Field 0 . . . 0 ID.28 ... ID.18 TX Data 4 TX Data 3 TX Data 2 TX Data 1...
Page 321: Error Management Logic (Eml)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 24 23 16 15 10 9 8 7 Frame info unused RX DLC unused ID Index Descriptor Field unused ID.28 ... ID.18 RX Data 4 RX Data 3 RX Data 2 RX Data 1...
Page 322 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Both self-tests are using the ‘Self Reception’ feature of the CAN Controller. With the Self Reception Request, the transmitted message is also received and stored in the receive buffer. Therefore the acceptance filter has to be configured accordingly. As soon as the CAN message is transmitted, a transmit and a receive interrupt are generated, if enabled.
Page 323: Memory Map Of The Can Block
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 6. Memory map of the CAN block The CAN Controllers and Acceptance Filter occupy a number of APB slots, as follows: Table 292. Memory map of the CAN block Address Range Used for 0x4003 8000 - 0x4003 87FF Acceptance Filter RAM.
Page 324 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 294. CAN1 and CAN2 controller register map Generic Description Access CAN1 Register CAN2 Register Name Address & Name Address & Name Receive frame status CAN1RFS - 0x4004 4020 CAN2RFS - 0x4004 8020...
Page 325: Can Mode Register (Can1Mod - 0X4004 4000, Can2Mod - 0X4004 8000)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 295. CAN1 and CAN2 controller register summary Generic Operating Mode Reset Mode Name Read Write Read Write TFI1 Tx Info1 Tx Info Tx Info Tx Info TID1 Tx Identifier Tx Identifier Tx Identifier...
Page 326: Can Command Register (Can1Cmr - 0X4004 X004, Can2Cmr - 0X4004 8004)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 297. CAN Mode register (CAN1MOD - address 0x4004 4000, CAN2MOD - address 0x4004 8000) bit description Bit Symbol Value Function Reset Value Transmit Priority Mode. 0(CAN ID) The transmit priority for 3 Transmit Buffers depends on the CAN Identifier.
Page 327 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 298. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit description Symbol Value Function Reset Value [1][2] Transmission Request. 0 (absent) No transmission request. 1 (present) The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer.
Page 328: Can Global Status Register (Can1Gsr - 0X4004 X008, Can2Gsr - 0X4004 8008)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 - Setting the command bits TR and AT simultaneously results in transmitting a message once. No re-transmission will be performed in case of an error or arbitration lost (single shot transmission). - Setting the command bits SRR and TR simultaneously results in sending the transmit message once using the self-reception feature.
Page 329 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 299. CAN Global Status Register (CAN1GSR - address 0x4004 4008, CAN2GSR - address 0x4004 8008) bit description Symbol Value Function Reset Value Transmit Complete Status. 0 (incomplete) At least one requested transmission has not been successfully completed yet.
Page 330: Can Interrupt And Capture Register (Can1Icr - 0X4004 400C, Can2Icr - 0X4004 800C)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 RX error counter The RX Error Counter Register, which is part of the Status Register, reflects the current value of the Receive Error Counter. After hardware reset this register is initialized to 0. In Operating Mode this register appears to the CPU as a read only memory.
Page 331 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Bits 1 through 10 clear when they are read. Bits 16-23 are captured when a bus error occurs. At the same time, if the BEIE bit in CANIER is 1, the BEI bit in this register is set, and a CAN interrupt can occur.
Page 332 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 300. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description Symbol Value Function Reset Value 0 (reset) Bus Error Interrupt -- this bit is set if the BEIE bit in...
Page 333 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 300. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description Symbol Value Function Reset Value 20:16 ERRBIT Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field.
Page 334: Can Interrupt Enable Register (Can1Ier - 0X4004 4010, Can2Ier - 0X4004 8010)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 300. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description Symbol Value Function Reset Value 31:24 ALCBIT Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field.
Page 335: Can Bus Timing Register
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 301. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit description Symbol Function Reset Value Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt.
Page 336 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 302. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit description Symbol Value Function Reset Value Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock.
Page 337: Can Error Warning Limit Register (Can1Ewl - 0X4004 4018, Can2Ewl - 0X4004 8018)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 × TSEG1 TSEG1 × TSEG2 TSEG2 7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018) This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read at any time but can only be written if the RM bit in CANmod is 1.
Page 338 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 304. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description Symbol Value Function Reset Value Transmit Status 1. 0(idle) There is no transmission from Tx Buffer 1.
Page 339: Can Receive Frame Status Register
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 304. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description Symbol Value Function Reset Value Error Status. This bit is identical to the ES bit in the CANxGSR.
Page 340: Id Index Field
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 7.9.1 ID index field The ID Index is a 10-bit field in the Info Register that contains the table position of the ID Look-up Table if the currently received message was accepted. The software can use this index to simplify message transfers from the Receive Buffer into the Shared Message Memory.
Page 341: Can Receive Data Register B (Can1Rdb - 0X4004 402C, Can2Rdb - 0X4004 802C)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 308. CAN Receive Data register A (CAN1RDA - address 0x4004 4028, CAN2RDA - address 0x4004 8028) bit description Symbol Function Reset Value ≥ 15:8 Data 2 If the DLC field in CANRFS 0010, this contains the first Data byte of the current received message.
Page 342 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 310. CAN Transmit Frame Information register (CAN1TFI[1/2/3] - address 0x4004 40[30/40/50], CAN2TFI[1/2/3] - 0x4004 80[30/40/50]) bit description Symbol Function Reset Value PRIO If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field.
Page 343: Can Transmit Identifier Register (Can1Tid[1/2/3] - 0X4004 40[34/44/54], Can2Tid[1/2/3] - 0X4004 80[34/44/54])
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 7.14 CAN Transmit Identifier register (CAN1TID[1/2/3] - 0x4004 40[34/44/54], CAN2TID[1/2/3] - 0x4004 80[34/44/54]) When the corresponding TBS bit in CANxSR is 1, software can write to one of these registers to define the Identifier field of the next transmit message. Bits not listed read as 0 and should be written as 0.
Page 344: Can Transmit Data Register B (Can1Tdb[1/2/3] - 0X4004 40[3C/4C/5C], Can2Tdb[1/2/3] - 0X4004 80[3C/4C/5C])
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 7.16 CAN Transmit Data register B (CAN1TDB[1/2/3] - 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] - 0x4004 80[3C/4C/5C]) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the 5th through 8th data bytes of the next transmit message. The Data Length Code defines the number of transferred data bytes.
Page 345: Can Controller Operation
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 316. CAN Wake-up Flags register (CANWAKEFLAGS - address 0x400F C114) bit description Symbol Function Reset Value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 346: Interrupts
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 in response to bus activity is not able to receive an initial message until after it detects Bus_Free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus is active when software sets SM, the wake-up is immediate.
Page 347: Central Transmit Status Register (Cantxsr - 0X4004 0000)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 9.1 Central Transmit Status Register (CANTxSR - 0x4004 0000) Table 317. Central Transit Status Register (CANTxSR - address 0x4004 0000) bit description Symbol Description Reset Value When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR).
Page 348: Central Miscellaneous Status Register (Canmsr - 0X4004 0008)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 9.3 Central Miscellaneous Status Register (CANMSR - 0x4004 0008) Table 319. Central Miscellaneous Status Register (CANMSR - address 0x4004 0008) bit description Symbol Description Reset Value When 1, one or both of the CAN1 Tx and Rx Error Counters has reached...
Page 349: Acceptance Filter Off Mode
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 A write access to all section configuration registers is only possible during the Acceptance Filter Off and Bypass Mode. Read access is allowed in all Acceptance Filter Modes. 11.1 Acceptance filter Off mode The Acceptance Filter Off Mode is typically used during initialization.
Page 350: Id Look-Up Table Ram
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 321. Section configuration register settings ID-Look up Table Section Register Value Section status Explicit Extended Frame Format Identifier Section EFF_GRP_sa = EFF_sa disabled > EFF_sa enabled Group of Extended Frame Format Identifier Section...
Page 351 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 bits to its word in RAM, and turned off by writing 32 one bits (0xFFFF FFFF) to its word in RAM. Only the disable bits are actually changed. Disabled entries must maintain the ascending sequence of Identifiers.
Page 352: Acceptance Filter Registers
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Receive Frame Status register. If the Acceptance Filter does not find a match in either the individual or Range table for the size of Identifier received, it signals the CAN controller to discard/ignore the received message.
Page 353: Standard Frame Individual Start Address Register (Sff_Sa - 0X4003 C004)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 14.3 Standard Frame Individual Start Address register (SFF_sa - 0x4003 C004) Table 323. Standard Frame Individual Start Address register (SFF_sa - address 0x4003 C004) bit description Symbol Description Reset Value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 354: Extended Frame Start Address Register
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 14.5 Extended Frame Start Address register (EFF_sa - 0x4003 C00C) Table 325. Extended Frame Start Address register (EFF_sa - address 0x4003 C00C) bit description Symbol Description Reset Value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 355: End Of Af Tables Register (Endoftable - 0X4003 C014)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 14.7 End of AF Tables register (ENDofTable - 0x4003 C014) Table 327. End of AF Tables register (ENDofTable - address 0x4003 C014) bit description Symbol Description Reset Value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 356: Lut Error Register (Luterr - 0X4003 C01C)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 14.10 LUT Error register (LUTerr - 0x4003 C01C) Table 329. LUT Error register (LUTerr - address 0x4003 C01C) bit description Symbol Description Reset Value LUTerr This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM.
Page 357: Configuration And Search Algorithm
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 15. Configuration and search algorithm The CAN Identifier Look-up Table Memory can contain explicit identifiers and groups of CAN identifiers for Standard and Extended CAN Frame Formats. They are organized as a sorted list or table with an increasing order of the Source CAN Channel (SCC) together with CAN Identifier in each section.
Page 358: Fullcan Mode
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Message Message disable bit disable bit Index 0, 1 SCC = 1 ID = 0x5A SCC = 1 FullCAN Explicit Index 2, 3 SCC = 2 SCC = 3 Standard Frame Index 4, 5...
Page 359 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 receive interrupt whenever a CAN message is accepted and received. Software has to move the received message out of the receive buffer from the according CAN controller into the user RAM. To cover dashboard like applications where the controller typically receives data from several CAN channels for further processing, the CAN Gateway block was extended by a so-called FullCAN receive function.
Page 360: Fullcan Message Layout
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.1 FullCAN message layout Table 333. Format of automatically stored Rx messages Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 361 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 START read 1st word SEM == 01? this message has not been SEM == 11? received since last check clear SEM, write back 1 st word read 2nd and 3rd words read 1st word...
Page 362: Fullcan Interrupts
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.2 FullCAN interrupts The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size a maximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM is used for FullCAN objects only.
Page 363: Message Lost Bit And Can Channel Number
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Message Message disable bit disable bit Index 0, 1 11-bit CAN ID 11-bit CAN ID FullCAN Explicit Index 2, 3 11-bit CAN ID 11-bit CAN ID Standard Frame Index 4, 5 11-bit CAN ID...
Page 364: Setting The Message Lost Bit Of A Fullcan Message Object (Msglost 63 To 0)
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.2.3 Setting the interrupt pending bits (IntPnd 63 to 0) The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN message and if the interrupt of the according FullCAN Object is enabled (enable bit FCANIntxEn) is set).
Page 365: Set And Clear Mechanism Of The Fullcan Interrupt 364 Scenario 1: Normal Case, No Message Lost . 364 Scenario 2: Message Lost
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 semaphore bits IntPndx Write write write write read clear read read read look-up ID, SEM table access MsgLostx message processor handler access access Fig 63. Normal case, no messages lost 16.3.2 Scenario 2: Message lost...
Page 366: Scenario 3: Message Gets Overwritten Indicated By Semaphore Bits
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.3.3 Scenario 3: Message gets overwritten indicated by Semaphore bits This scenario is a special case in which the lost message is indicated by the existing semaphore bits. The scenario is entered, if during a Software read of a message object another new message gets stored by the message handler.
Page 367: Scenario 3.2: Message Gets Overwritten Indicated By Message Lost
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 semaphore bits IntPndx write write clear write write write read clear write write write read read read read read read look-up table access 1st Object 2nd Object write write 2nd Object 1st Object read...
Page 368: Scenario 4: Clearing Message Lost Bit
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 semaphore bits IntPndx look-up write write write write write write read write write write clear read read read write write write table access 1st Object 2nd Object 3rd Object write write write 1st Object...
Page 369: Examples Of Acceptance Filter Tables And Id Index Values
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 semaphore bits IntPndx write write write write write write write write write read clear read read write write write read look-up table access 1st Object 2nd Object 3rd Object write write write 1st Object...
Page 370: Configuration Example 4
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 In cases where explicit identifiers as well as groups of the identifiers are programmed, a CAN identifier search has to start in the explicit identifier section first. If no match is found, it continues the search in the group of identifier section. By this order it can be guaranteed...
Page 371: Configuration Example 6
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 000 d := 000 h := 0 0000 0000 b SFF_sa look-up table RAM ID index # APB base + column_lower column_upper address 00d = 00h 04d = 04h 44d = 2Ch 48d = 30h...
Page 372 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 336. Used ID-Look-up Table sections ID-Look-up Table Section Status FullCAN not activated Explicit Standard Frame Format activated Group of Standard Frame Format activated Explicit Extended Frame Format activated Group of Extended Frame Format...
Page 373: Configuration Example 7
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Message Message disable bit disable bit Index SFF_sa ID28 ID28 ID18 ID18 = 0x00 Explicit Standard ID28 ID18 ID28 ID18 Frame Format ID28 ID18 ID28 ID18 Identifier Section Disabled, 7 ID18 ID18 ID28...
Page 374 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 FullCAN explicit standard frame format identifier section (11-bit CAN ID) The start address of the FullCAN Explicit Standard Frame Format Identifier section is (automatically) set to 0x00. The end of this section is defined in the SFF_sa register. In the FullCAN ID section only identifiers of FullCAN Object are stored for acceptance filtering.
Page 375: Look-Up Table Programming Guidelines
UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 FullCAN FullCAN Message Message Interrupt Interrupt Disable bit Disable bit Enable bit Enable bit Index FullCAN Disabled, 1 ID28 ID18 ID18 ID28 Explicit Standard ID28 ID18 ID18 ID28 Frame Format ID18 ID18 ID28...
Page 376 UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 • Each section has to be organized as a sorted list or table with an increasing order of the Source CAN Channel (SCC) in conjunction with the CAN Identifier (there is no exception for disabled identifiers).
Page 377: Chapter 17: Lpc17Xx Spi
UM10360 Chapter 17: LPC17xx SPI Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The SPI is configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bit PCSPI. Remark: On reset, the SPI is enabled (PCSPI = 1). 2.
Page 378: Pin Description
UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI 4. Pin description Table 338. SPI pin description Type Pin Description Name Input/ Serial Clock. The SPI clock signal (SCK) is used to synchronize the transfer of Output data across the SPI interface. The SPI is always driven by the master and received by the slave.
Page 379 UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI SCK (CPOL = 0) SCK (CPOL = 1) SSEL CPHA = 0 Cycle # CPHA = 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8...
Page 380: Spi Peripheral Details
UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI 6. SPI peripheral details 6.1 General information There are five control and status registers for the SPI port. They are described in detail in Section 17–7 “Register description” on page 382. The SPI Control Register (S0SPCR) contains a number of programmable bits used to control the function of the SPI block.
Page 381: Slave Operation
UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI 3. Wait for the SPIF bit in the SPI Status Register to be set to 1. The SPIF bit will be set after the last cycle of the SPI data transfer. 4. Read the SPI Status Register.
Page 382: Register Description
UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI Register has been read when the SPIF status is active. If the SPI Data Register is written in this time frame, the write data will be lost, and the write collision (WCOL) bit in the SPI Status Register will be activated.
Page 383 UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI Table 341: SPI Control Register (S0SPCR - address 0x4002 0000) bit description Symbol Value Description Reset Value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 384: Spi Data Register (S0Spdr - 0X4002 0008) 384 Spi Clock Counter Register (S0Spccr - 0X4002 000C)
UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI 7.2 SPI Status Register (S0SPSR - 0x4002 0004) The S0SPSR register controls the operation of SPI0 as per the configuration bits setting shown in Table 17–342. Table 342: SPI Status Register (S0SPSR - address 0x4002 0004) bit description...
Page 385: Spi Test Control Register (Sptcr - 0X4002 0010)
UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI In Slave mode, the SPI clock rate provided by the master must not exceed 1/8 of the SPI peripheral clock selected in Section 4–7.4. The content of the S0SPCCR register is not relevant.
Page 386: Architecture
UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI Table 347: SPI Interrupt Register (S0SPINT - address 0x4002 001C) bit description Bit Symbol Description Reset Value SPIF SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit.
Page 387: Chapter 18: Lpc17Xx Ssp0/1 Interface
UM10360 Chapter 18: LPC17xx SSP0/1 interface Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The two SSP interfaces, SSP0 and SSP1 are configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bit PCSSP0 to enable SSP0 and bit PCSSP1 to enable SSP1.
Page 388: Pin Descriptions
UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface The LPC17xx has two Synchronous Serial Port controllers -- SSP0 and SSP1. 4. Pin descriptions Table 348. SSP pin descriptions Interface pin name/function Type Pin Description Name Microwire SCK0/1 Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the transfer of data.
Page 389: Spi Frame Format
UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface DX/DR 4 to 16 bits a. Single frame transfer DX/DR 4 to 16 bits 4 to 16 bits b. Continuous/back-to-back frames transfer Fig 74. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two...
Page 390: Spi Format With Cpol=0,Cpha=0
UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface The CPHA control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge.
Page 391: Spi Format With Cpol=0,Cpha=1
UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface In the case of a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured.
Page 392 UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface SSEL MOSI MISO 4 to 16 bits a. Single transfer with CPOL=1 and CPHA=0 SSEL MOSI MISO 4 to 16 bits 4 to 16 bits b. Continuous transfer with CPOL=1 and CPHA=0 Fig 77.
Page 393: Spi Format With Cpol = 1,Cpha = 1
UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface 5.2.5 SPI format with CPOL = 1,CPHA = 1 The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in Figure 18–78, which covers both single and continuous transfers.
Page 394 UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface 8-bit control 4 to 16 bits output data Fig 79. Microwire frame format (single transfer) Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSP to the off-chip slave device.
Page 395: Setup And Hold Time Requirements On Cs With Respect To Sk In Microwire Mode
UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface 8-bit control 4 to 16 bits 4 to 16 bits output data output data Fig 80. Microwire frame format (continuos transfers) 5.3.1 Setup and hold time requirements on CS with respect to SK in Microwire...
Page 396: Sspn Control Register 0 (Ssp0Cr0 -
UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface Table 349. SSP Register Map Generic Name Description Access Reset SSPn Register Value Name & Address Status Register SSP0SR - 0x4008 800C SSP1SR - 0x4003 000C CPSR Clock Prescale Register SSP0CPSR - 0x4008 8010...
Page 397: Sspn Control Register 1 (Ssp0Cr1 -
UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface Table 350: SSPn Control Register 0 (SSP0CR0 - address 0x4008 8000, SSP1CR0 - 0x4003 0000) bit description Symbol Value Description Reset Value Frame Format. Microwire This combination is not supported and should not be used.
Page 398: Sspn Data Register (Ssp0Dr - 0X4008 8008,
UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface Table 351: SSPn Control Register 1 (SSP0CR1 - address 0x4008 8004, SSP1CR1 - 0x4003 0004) bit description Symbol Value Description Reset Value Master/Slave Mode.This bit can only be written when the SSE bit is 0.
Page 399: 0X4008 8010, Ssp1Cpsr - 0X4003 0010)
UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface Table 353: SSPn Status Register (SSP0SR - address 0x4008 800C, SSP1SR - 0x4003 000C) bit description Symbol Description Reset Value Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
Page 400: Sspn Raw Interrupt Status Register (Ssp0Ris -
UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface Table 355: SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4008 8014, SSP1IMSC - 0x4003 0014) bit description Symbol Description Reset Value RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received.
Page 401: Sspn Interrupt Clear Register (Ssp0Icr -
UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 interface Table 357: SSPn Masked Interrupt Status register (SSPnMIS -address 0x4008 801C, SSP1MIS - 0x4003 001C) bit description Symbol Description Reset Value RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.
Page 402: Chapter 19: Lpc17Xx I2C0/1/2 Interface
UM10360 Chapter 19: LPC17xx I2C0/1/2 interface Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The I C0/1/2 interfaces are configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bit PCI2C0/1/2. Remark: On reset, all I C interfaces are enabled (PCI2C0/1/2 = 1).
Page 403: Applications
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface • C0 is a standard I C compliant bus interface with open-drain pins. This interface supports functions described in the I C specification for speeds up to 1 MHz. This includes multi-master operation and allows powering off this device in a working system while leaving the I C-bus functional.
Page 404: I 2 C Fast Mode Plus
Fast Mode Plus is a 1 Mbit/sec transfer rate to communicate with the I C products which the NXP Semiconductors is now providing. In order to use Fast Mode Plus, the I C0 pins must be configured, then rates above 400...
Page 405: C Operating Modes
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface the same microcontroller. Therefore, I C1 and I C2 are implemented using standard port pins, and do not support the ability to turn power off to the device while leaving the I C-bus functioning between other devices.
Page 406: Master Receiver Mode
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface SLAVE ADDRESS DATA DATA “0” - write “1” - read data transferred (n Bytes + Acknowledge) A = Acknowledge (SDA low) from Master to Slave A = Not acknowledge (SDA high) from Slave to Master...
Page 407: Slave Receiver Mode
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface After a repeated START condition, I C may switch to the master transmitter mode. DATA DATA DATA data transferred (n Bytes + Acknowledge) A = Acknowledge (SDA low) From master to slave...
Page 408: Slave Transmitter Mode
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 6.4 Slave Transmitter mode The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via SDA while the serial clock is input through SCL.
Page 409 UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface ADDRESS REGISTERS I2CnADDR0 to I2CnADDR3 MATCHALL I2CnMMCTRL[3] MASK REGISTERS MASK and COMPARE I2CnMASK0 to I2CnMASK3 INPUT FILTER I2CnDATABUFFER SHIFT REGISTER OUTPUT I2CnDAT STAGE MONITOR MODE REGISTER I2CnMMCTRL BIT COUNTER/ PCLK ARBITRATION and...
Page 410: Address Registers, I2Adr0 To I2Adr3
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 7.2 Address Registers, I2ADR0 to I2ADR3 These registers may be loaded with the 7-bit slave address (7 most significant bits) to which the I C block will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable General Call address (0x00) recognition.
Page 411: Serial Clock Generator
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface SDA line SCL line (1) Another device transmits serial data. (2) Another device overrules a logic (dotted line) transmitted this I C master by pulling the SDA line low. Arbitration is lost, and this I C enters Slave Receiver mode.
Page 412: Timing And Control
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface via the I C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH registers for details. The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above.
Page 413 UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface Table 363. I C register map Name Description Access Reset C0 Address C1 Address C2 Address value and Name and Name and Name I2CONSET I C Control Set Register. When a one is...
Page 414: I C000;2, C000; C000;Ontrol Set Register (Ic000;2,C000;Onset: I C000;2, C000;0, Ic000;2,C000;0C000;Onset - 0X4001 C000;000; I C000;2, C000;1, Ic000;2,C000;1C000;Onset - 0X4005 C000;000; I C000;2, C000;C000;2,, Ic000;2,C000;C000;2,C000;Onset - 0X400A 0000)
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface Table 363. I C register map Name Description Access Reset C0 Address C1 Address C2 Address value and Name and Name and Name I2ADR3 C Slave Address Register 3. Contains 0x00 0x4001 C028...
Page 415 UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface Table 364. I C Control Set register (I2CONSET: I C0, I2C0CONSET - address 0x4001 C000, C1, I2C1CONSET - address 0x4005 C000, I C2, I2C2CONSET - address 0x400A 0000) bit description Bit Symbol...
Page 416: I 2 C Control Clear Register
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface In slave mode, setting this bit can recover from an error condition. In this case, no STOP condition is transmitted to the bus. The hardware behaves as if a STOP condition has been received and it switches to “not addressed”...
Page 417: I C1,2, C1, Status Register (Ic1,2,Stat: I C1,2, C1,0, Ic1,2,C1,0Stat - 0X4001 C1,004; I C1,2, C1,1, Ic1,2,C1,1Stat - 0X4005 C1,004; I C1,2, C1,C1,2,, Ic1,2,C1,C1,2,Stat - 0X400A 0004)
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface Table 365. I C Control Clear register (I2CONCLR: I C0, I2C0CONCLR - 0x4001 C018; I I2C1CONCLR - 0x4005 C018; I C2, I2C2CONCLR - 0x400A 0018) bit description Bit Symbol Description STAC START flag Clear bit.
Page 418: I C0,2, C0, Monitor Mode Control Register (Ic0,2,Mmc0,Trl: I C0,2, C0,0, Ic0,2,C0,Mmc0,Trl0 - 0X4001 C0,01C0,; I C0,2, C0,1, Ic0,2,C0,1Mmc0,Trl- 0X4005 C0,01C0,; I C0,2, C0,C0,2,, Ic0,2,C0,C0,2,Mmc0,Trl- 0X400A 001C0,)
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 8.5 I C Monitor mode control register (I2MMCTRL: I C0, I2CMMCTRL0 - 0x4001 C01C; I C1, I2C1MMCTRL- 0x4005 C01C; I C2, I2C2MMCTRL- 0x400A 001C) This register controls the Monitor mode which allows the I...
Page 419: Interrupt In Monitor Mode
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 8.5.1 Interrupt in Monitor mode All interrupts will occur as normal when the module is in monitor mode. This means that the first interrupt will occur when an address-match is detected (any address received if the MATCH_ALL bit is set, otherwise an address matching one of the four address registers).
Page 420: I 2 C Slave Address Registers
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 8.7 I C Slave Address registers (I2ADR0 to 3: I C0, I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C, 20, 24, 28]; I C1, I2C1ADR[0, 1, 2, 3] - address 0x4005 C0[0C, 20, 24, 28]; I...
Page 421: Selecting The Appropriate I C Data Rate And Duty Cycle
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 8.9 I C SCL HIGH duty cycle register (I2SCLH: I C0, I2C0SCLH - 0x4001 C010; I C1, I2C1SCLH - 0x4005 C010; I C2, I2C2SCLH - 0x400A 0010) Table 372. I C SCL HIGH Duty Cycle register (I2SCLH: I C0, I2C0SCLH - address 0x4001 C010;...
Page 422: Details Of I C Operating Modes
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface I2SCLL and I2SCLH values should not necessarily be the same. Software can set different duty cycles on SCL by setting these two registers. For example, the I C-bus specification defines the SCL low time and high time at different values for a Fast Mode and Fast Mode Plus I 9.
Page 423: Master Receiver Mode
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface Table 376. I2CONSET used to initialize Master Transmitter mode Symbol I2EN Value The I C rate must also be configured in the I2SCLL and I2SCLH registers. I2EN must be set to logic 1 to enable the I C block.
Page 424 UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface The upper 7 bits are the address to which the I C block will respond when addressed by a master. If the LSB (GC) is set, the I C block will respond to the General Call address (0x00);...
Page 425 UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface successful transmission DATA to a Slave Receiver next transfer started with a Repeated Start condition Acknowledge received after the Slave address to Master receive mode, Acknowledge entry received after a = MR...
Page 426 UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface successful transmission to DATA DATA a Slave transmitter next transfer started with a Repeated Start condition Not Acknowledge received after the Slave address to Master transmit mode, entry = MT arbitration lost in...
Page 427 UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface reception of the own Slave address and one DATA DATA P OR S or more Data bytes all are acknowledged last data byte received is Not P OR S acknowledged arbitration lost as...
Page 428: Slave Transmitter Mode
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface reception of the own Slave address and one or more Data DATA DATA P OR S bytes all are acknowledged arbitration lost as Master and addressed as Slave last data byte transmitted. Switched...
Page 429 UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface Table 379. Master Transmitter mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 430 UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface Table 380. Master Receiver mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 431 UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface Table 381. Slave Receiver mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 432 UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface Table 381. Slave Receiver mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 433 UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface Table 382. Slave Transmitter mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 434: Miscellaneous States
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 9.5 Miscellaneous states There are two I2STAT codes that do not correspond to a defined I C hardware state (see Table 19–383). These are discussed below. 9.5.1 I2STAT = 0xF8 This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set.
Page 435: Some Special Cases
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface Table 383. Miscellaneous States Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI 0xF8...
Page 436: I 2 C-Bus Obstructed By A Low Level On Scl Or Sda
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP condition is transmitted. The I C hardware behaves as if a STOP condition was received and is able to transmit a START condition.
Page 437: C State Service Routines
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface time limit STA flag STO flag SDA line SCL line start condition Fig 96. Forced access to a busy I C-bus STA flag SDA line SCL line start condition (1) Unsuccessful attempt to send a START condition.
Page 438: I 2 C Interrupt Service
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface The I C hardware now begins checking the I C-bus for its own slave address and General Call. If the General Call or the own slave address is detected, an interrupt is requested and I2STAT is loaded with the appropriate state information.
Page 439: I 2 C Interrupt Routine
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 2. Set up the Slave Address to which data will be transmitted, and add the Read bit. 3. Write 0x20 to I2CONSET to set the STA bit. 4. Set up the Master Receive buffer.
Page 440: Master Transmitter States
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 4. Set up Master Transmit mode data buffer. 5. Set up Master Receive mode data buffer. 6. Initialize Master data counter. 7. Exit 10.6 Master Transmitter states 10.6.1 State: 0x18 Previous state was State 0x08 or State 0x10, Slave Address + Write has been transmitted, ACK has been received.
Page 441: State: 0X38
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 10.6.5 State: 0x38 Arbitration has been lost during Slave Address + Write or data. The bus has been released and not addressed Slave mode is entered. A new START condition will be transmitted when the bus is free again.
Page 442: Slave Receiver States
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 2. Write 0x14 to I2CONSET to set the STO and AA bits. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Exit 10.8 Slave Receiver states 10.8.1 State: 0x60 Own Slave Address + Write has been received, ACK has been returned. Data will be received and ACK returned.
Page 443: State: 0X80
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 4. Initialize Slave data counter. 5. Exit 10.8.5 State: 0x80 Previously addressed with own Slave Address. Data has been received and ACK has been returned. Additional data will be read. 1. Read data byte from I2DAT into the Slave Receive buffer.
Page 444: Slave Transmitter States
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit 10.9 Slave Transmitter states 10.9.1 State: 0xA8 Own Slave Address + Read has been received, ACK has been returned. Data will be transmitted, ACK bit will be received.
Page 445: State: 0Xc8
UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 interface 10.9.5 State: 0xC8 The last data byte has been transmitted, ACK has been received. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag.
Page 446: Basic Configuration
UM10360 Chapter 20: LPC17xx I2S interface Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The I S interface is configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bit PCI2S. Remark: On reset, the I S interface is disabled (PCI2S = 0).
Page 447: Description
UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface 3. Description The I S performs serial data out via the transmit channel and serial data in via the receive channel. These support the NXP Inter IC Audio format for 8-bit, 16-bit and 32-bit audio data, both for stereo and mono modes.
Page 448: Register Description
UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface Table 384. Pin descriptions Pin Name Type Description I2STX_CLK Input/Output Transmit Clock. A clock signal used to synchronize the transfer of data on the transmit channel. It is driven by the master and received by the slave.
Page 449: Digital Audio Output Register (I2Sdao - 0X400A 8000)
UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface Table 385. I S register map Name Description Access Reset Address Value I2SDAO Digital Audio Output Register. Contains 0x87E1 0x400A 8000 control bits for the I S transmit channel. I2SDAI Digital Audio Input Register. Contains control...
Page 450: Digital Audio Input Register (I2Sdai - 0X400A 8004)
UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface Table 386: Digital Audio Output register (I2SDAO - address 0x400A 8000) bit description Symbol Value Description Reset Value wordwidth Selects the number of bytes in data as follows: 8-bit data 16-bit data...
Page 451: Transmit Fifo Register (I2Stxfifo - 0X400A 8008)
UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface 5.3 Transmit FIFO register (I2STXFIFO - 0x400A 8008) The I2STXFIFO register provides access to the transmit FIFO. The function of bits in I2STXFIFO are shown in Table 20–388. Table 388: Transmit FIFO register (I2STXFIFO - address 0x400A 8008) bit description...
Page 452: Dma Configuration Register 2 (I2Sdma2 - 0X400A 8018)
UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface Table 391: DMA Configuration register 1 (I2SDMA1 - address 0x400A 8014) bit description Symbol Description Reset Value rx_dma1_enable When 1, enables DMA1 for I S receive. tx_dma1_enable When 1, enables DMA1 for I S transmit.
Page 453: Transmit Clock Rate Register (I2Stxrate - 0X400A 8020)
UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface Table 393: Interrupt Request Control register (I2SIRQ - address 0x400A 801C) bit description Symbol Description Reset Value 15:13 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 454: Transmit Clock Rate Register (I2Stxbitrate - 0X400A 8028)
UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface Table 395: Receive Clock Rate register (I2SRXRATE - address 0x400A 8024) bit description Symbol Description Reset Value S receive Y_divider MCLK rate denominator. This value is used to divide receive PCLK to produce the MCLK.
Page 455: Receive Mode Control Register (I2Srxmode - 0X400A 8034)
UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface Table 398: Transmit Mode Control register (I2STXMODE - 0x400A 8030) bit description Symbol Value Description Reset Value TXCLKSEL Clock source selection for the transmit bit clock divider. Select the TX fractional rate divider clock output as the...
Page 456: S Operating Modes
UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface • Data word length is determined by the wordwidth value in the configuration register. There is a separate wordwidth value for the receive channel and the transmit channel. – 0: word is considered to contain four 8-bit data words.
Page 457 UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface Table 400: I S transmit modes I2SDAO I2STXMODE Description [3:0] 0 0 0 0 Typical transmitter master mode. See Figure 20–99. transmit function operates as a master. The transmit clock source is the fractional rate divider.
Page 458 UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface I2STXMODE[3] (Pin OE) I2STX_MCLK I2STX_RATE[15:8] I2STX_CLK I2STX_RATE[7:0] I2STXBITRATE[5:0] I2STX_SDA 8-bit peripheral I2S_PCLK TX_REF TX bit clock ÷N ÷2 Fractional block (1 to 64) I2STX_WS Rate Divider (transmit) TX_WS ref Fig 99. Typical transmitter master mode, with or without MCLK output...
Page 459 UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface I2STX_SDA peripheral RX bit clock block I2STX_WS (transmit) RX_WS ref Fig 104. 4-wire transmitter slave mode sharing the receiver bit clock and WS Table 401: I S receive modes I2SDAI I2SRXMODE Description...
Page 460 UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface I2SRXMODE[3] (Pin OE) I2SRX_MCLK I2SRX_RATE[15:8] I2SRX_CLK I2SRX_RATE[7:0] I2SRXBITRATE[5:0] I2SRX_SDA 8-bit peripheral I2S_PCLK RX_REF RX bit clock ÷N ÷2 Fractional block (1 to 64) I2SRX_WS Rate Divider (receive) RX_WS ref Fig 105. Typical receiver master mode, with or without MCLK output...
Page 461: Fifo Controller
UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface I2SRX_SDA peripheral TX bit clock block I2SRX_WS (receive) TX_WS ref Fig 110. 4-wire receiver slave mode sharing the transmitter bit clock and WS 8. FIFO controller Handling of data for transmission and reception is performed via the FIFO controller which can generate two DMA requests and an interrupt request.
Page 462 UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S interface Mono 8-bit data mode N + 3 N + 2 N + 1 Stereo 8-bit data mode LEFT + 1 RIGHT + 1 LEFT RIGHT Mono 16-bit data mode N + 1...
Page 463: Chapter 21: Lpc17Xx Timer 0/1/2/3
UM10360 Chapter 21: LPC17xx Timer 0/1/2/3 Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The Timer 0, 1, 2, and 3 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bits PCTIM0/1/2/3. Remark: On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled (PCTIM2/3 = 0).
Page 464: Applications
UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 3. Applications • Interval Timer for counting internal events. • Pulse Width Demodulator via Capture inputs. • Free running timer. 4. Description The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally-supplied clock, and can optionally generate interrupts or perform other actions at specified timer values, based on four match registers.
Page 465 UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 Table 406. TIMER/COUNTER0-3 register map Generic Description Access Reset TIMERn Register/ Name Value Name & Address Interrupt Register. The IR can be written to T0IR - 0x4000 4000 clear interrupts. The IR can be read to...
Page 466: Interrupt Register
UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 Table 406. TIMER/COUNTER0-3 register map Generic Description Access Reset TIMERn Register/ Name Value Name & Address Capture Register 0. CR0 is loaded with the T0CR0 - 0x4000 402C value of TC when there is an event on the T1CR0 - 0x4000 802C CAPn.0(CAP0.0 or CAP1.0 respectively)
Page 467: Count Control Register (T[0/1/2/3]Ctcr - 0X4000 4070, 0X4000 8070, 0X4009 0070, 0X4009 4070)
UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 Table 408. Timer Control Register (TCR, TIMERn: TnTCR - addresses 0x4000 4004, 0x4000 8004, 0x4009 0004, 0x4009 4004) bit description Symbol Description Reset Value Counter Enable When one, the Timer Counter and Prescale Counter are enabled for counting.
Page 468: Timer Counter
UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 Table 409. Count Control Register (T[0/1/2/3]CTCR - addresses 0x4000 4070, 0x4000 8070, 0x4009 0070, 0x4009 4070) bit description Symbol Value Description Reset Value Count When bits 1:0 in this register are not 00, these bits select Input which CAP pin is sampled for clocking.
Page 469: Match Control Register (T[0/1/2/3]Mcr - 0X4000 4014, 0X4000 8014, 0X4009 0014, 0X4009 4014)
UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 6.8 Match Control Register (T[0/1/2/3]MCR - 0x4000 4014, 0x4000 8014, 0x4009 0014, 0x4009 4014) The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter. The function of each of the bits is shown Table 21–410.
Page 470: Capture Registers (Cr0 - Cr1)
UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 6.9 Capture Registers (CR0 - CR1) Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin. The settings in the Capture...
Page 471: External Match Register (T[0/1/2/3]Emr - 0X4000 403C, 0X4000 803C, 0X4009 003C, 0X4009 403C)
UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 6.11 External Match Register (T[0/1/2/3]EMR - 0x4000 403C, 0x4000 803C, 0x4009 003C, 0x4009 403C) The External Match Register provides both control and status of the external match pins. In the descriptions below, “n” represents the Timer number, 0 or 1, and “m” represent a Match number, 0 through 3.
Page 472: Dma Operation
UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 6.12 DMA operation DMA requests are generated by 0 to 1 transitions of the External Match 0 and 1 bits of each timer. In order to have an effect, the GPDMA must be configured and the relevant...
Page 473: Architecture
UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 8. Architecture The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in Figure 21–114. MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER...
Page 474: Features
UM10360 Chapter 22: LPC17xx Repetitive Interrupt Timer (RIT) Rev. 00.06 — 5 June 2009 User manual 1. Features • 32-bit counter running from PCLK. Counter can be free-running, or be reset by a generated interrupt. • 32-bit compare value. • 32-bit compare mask.
Page 475: Ri Control Register (Rictrl - 0X400B 0008)
UM10360 NXP Semiconductors Chapter 22: LPC17xx Repetitive Interrupt Timer (RIT) 3.3 RI Control register (RICTRL - 0x400B 0008) Table 417. RI Control register (RICTRL - address 0x400B 0008) bit description Symbol Value Description Reset value RITINT Interrupt flag This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers.
Page 476 UM10360 NXP Semiconductors Chapter 22: LPC17xx Repetitive Interrupt Timer (RIT) Counting can be halted in software by writing a ‘0’ to the Enable_Timer bit - RICTRL(2). Counting will also be halted while a hardware BREAK is in progress provided the Enable_Break bit –...
Page 477: Basic Configuration
UM10360 Chapter 23: LPC17xx System Tick Timer Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The System Tick Timer is configured using the following registers: 1. Pins: Select the STCLK function on pin P3.26 if it is to be used to clock the timer. Select the pin modes for the port pins with timer functions through the PINMODE registers (Section...
Page 478: Register Description
UM10360 NXP Semiconductors Chapter 23: LPC17xx System Tick Timer STCALIB STRELOAD load data STCURR private cclk peripheral 24-bit down counter clock STCLK pin under- count flow enable load ENABLE CLKSOURCE STCTRL COUNTFLAG TICKINT System Tick interrupt Fig 116. System Tick Timer block diagram 5.
Page 479: System Timer Reload Value Register (Streload - 0Xe000 E014)
UM10360 NXP Semiconductors Chapter 23: LPC17xx System Tick Timer Table 420. System Timer Control and status register (STCTRL - 0xE000 E010) bit description Symbol Description Reset value 15:3 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 480 UM10360 NXP Semiconductors Chapter 23: LPC17xx System Tick Timer Table 423. System Timer Calibration value register (STCALIB - 0xE000 E01C) bit description Symbol Description Reset value 23:0 TENMS Reload value to get a 10 millisecond System Tick underflow rate when 0x0F423F running at 100 MHz.
Page 481: Basic Configuration
UM10360 Chapter 24: LPC17xx Pulse Width Modulator (PWM) Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The PWM is configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bit PCPWM1. Remark: On reset, the PWM is enabled (PCPWM1 = 1). 2.
Page 482: Description
UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) 3. Description The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC17xx. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers.
Page 483 UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) SHADOW REGISTER 0 MATCH REGISTER 0 LOAD ENABLE MATCH REGISTER 1 SHADOW REGISTER 1 LOAD ENABLE SHADOW REGISTER 2 MATCH REGISTER 2 LOAD ENABLE SHADOW REGISTER 3 MATCH REGISTER 3...
Page 484: Sample Waveform With Rules For Single And
UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) 4. Sample waveform with rules for single and double edge control A sample of how PWM values relate to waveform outputs is shown in Figure 24–118. PWM output logic is shown in Figure 24–117...
Page 485: Rules For Single Edge Controlled Pwm Outputs
UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) 4.1 Rules for Single Edge Controlled PWM Outputs 1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0.
Page 486: Pwm Base Addresses
UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) 6. PWM base addresses Table 426: Addresses for PWM1 Base Addresses 0x4001 8000 7. Register description The PWM1 function includes registers as shown in Table 24–427 below. Table 427. PWM1 register map...
Page 487 UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) Table 427. PWM1 register map Generic Description Access Reset PWMn Register Name Value Name & Address Capture Control Register. The CCR controls which edges of PWM1CCR - 0x4001 8028 the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
Page 488: Pwm Timer Control Register (Pwm1Tcr 0X4001 8004)
UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) Table 428: PWM Interrupt Register (PWM1IR - address 0x4001 8000) bit description Symbol Description Reset Value PWMCAP0 Interrupt flag for capture input 0 Interrupt PWMCAP1 Interrupt flag for capture input 1.
Page 489: Pwm Match Control Register (Pwm1Mcr - 0X4001 8014)
UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) Table 430: PWM Count control Register (PWM1CTCR - address 0x4001 004) bit description Symbol Value Description Reset Value Counter/ Timer Mode: the TC is incremented when the Prescale Timer Mode Counter matches the Prescale Register.
Page 490 UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) Table 431: Match Control Register (PWM1MCR - address 0x4000 4014) bit description Symbol Value Description Reset Value PWMMR2I Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC.
Page 491: Pwm Capture Control Register (Pwm1Ccr - 0X4001 8028)
UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) Table 431: Match Control Register (PWM1MCR - address 0x4000 4014) bit description Symbol Value Description Reset Value PWMMR6R 1 Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it.
Page 492: Pwm Control Register (Pwm1Pcr - 0X4001 804C)
UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) 7.6 PWM Control Register (PWM1PCR - 0x4001 804C) The PWM Control Register is used to enable and select the type of each PWM channel. The function of each of the bits are shown in Table 24–433.
Page 493 UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) values has taken place, all bits of the LER are automatically cleared. Until the corresponding bit in the PWMLER is set and a PWM Match 0 event occurs, any value written to the PWM Match registers has no effect on PWM operation.
Page 494: Introduction
UM10360 Chapter 25: LPC17xx Motor Control PWM Rev. 00.06 — 5 June 2009 User manual 1. Introduction The Motor Control PWM (MCPWM) is optimized for three-phase AC and DC motor control applications, but can be used in many other applications that need timing, counting, capture, and comparison.
Page 495: Block Diagram
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM 4. Block Diagram PCLK MCI0-2 Clock Event Clock Event Clock Event selection selection selection selection selection selection MCCNTCON MCCAPCON cntl cntl cntl MAT0 MAT1 MAT2 ACMODE ACMODE (write) (write) (write) MAT0...
Page 496: Configuring Other Modules For Mcpwm Use
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM 5. Configuring other modules for MCPWM use Configure the following registers in other modules before using the Motor Control PWM: 1. Power: in the PCONP register (Table 4–46), set bit PCMCPWM.
Page 497: Register Description
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM 7. Register description “Control” registers and “interrupt” registers have separate read, set, and clear addresses. Reading such a register’s read address(e.g. MCCON) yields the state of the register bits. Writing ones to the set address (e.g. MCCON_SET) sets register bit(s), and writing ones to the clear address (e.g.
Page 498: Mcpwm Control Register
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM 7.1 MCPWM Control register 7.1.1 MCPWM Control read address (MCCON - 0x400B 8000) The MCCON register controls the operation of all channels of the PWM. This address is read-only, but the underlying register can be modified by writing to addresses MCCON_SET and MCCON_CLR.
Page 499 UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM Table 437. MCPWM Control read address (MCCON - 0x400B 8000) bit description Symbol Value Description Reset value DISUP1 Enable/disable updates of functional registers for channel 1 (see Section 25–8.2). Functional registers are updated from the write registers at the end of each PWM cycle.
Page 500: Mcpwm Control Set Address
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM 7.1.2 MCPWM Control set address (MCCON_SET - 0x400B 8004) Writing ones to this write-only address sets the corresponding bits in MCCON. Table 438. MCPWM Control set address (MCCON_SET - 0x400B 8004) bit description...
Page 501: Mcpwm Capture Control Set Address (Mccapcon_Set - 0X400B 8010)
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM Table 440. MCPWM Capture Control read address (MCCAPCON - 0x400B 800C) bit description Symbol Description Reset Value CAP1MCI2_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.
Page 502: Mcpwm Interrupt Registers
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM 7.3 MCPWM Interrupt registers The Motor Control PWM module includes the following interrupt sources: Table 443. Motor Control PWM interrupts Symbol Description ILIM0-2 Limit interrupts for channels 0-2. IMAT0-2 Match interrupts for channels 0-2.
Page 503: Mcpwm Interrupt Flags Read Address (Mcintf - 0X400B 8068)
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM Table 447. PWM interrupt enable clear register (MCINTEN_CLR - address 0x400B 8058) bit description Description 31:0 Writing ones to this address sets the corresponding bits in MCINTEN, thus disabling interrupts. See Table 25–444...
Page 504: Mcpwm Count Control Register
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM 7.4 MCPWM Count Control register 7.4.1 MCPWM Count Control read address (MCCNTCON - 0x400B 805C) The MCCNTCON register controls whether the MCPWM channels are in timer or counter mode, and in counter mode whether the counter advances on rising and/or falling edges on any or all of the three MCI inputs.
Page 505: Mcpwm Count Control Set Address (Mccntcon_Set - 0X400B 8060)
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM Table 451. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description Symbol Value Description Reset Value TC1MCI2_FE If MODE1 is 1, counter 1 advances on a falling edge on MCI2.
Page 506: Mcpwm Timer/Counter 0-2 Registers (Mctc0-2 - 0X400B 8018, 0X400B 801C, 0X400B 8020)
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM Table 453. MCPWM Count Control clear address (MCCAPCON_CLR - 0x400B 8064) bit description Description 31:0 Writing one(s) to this write-only address clears the corresponding bit(s) in the MCCNTCON register. See Table 25–451 for the bit allocation.
Page 507: 0X400B 8030, 0X400B 8034, 0X400B 8038)
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM Table 455. MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028, 0x400B 802C) bit description Symbol Description Reset value 31:0 MCLIM0-2 Limit values for TC0-2 0xFFFF FFFF Note: In timer mode, the period of a channel’s modulated MCO outputs is determined by its Limit register, and the pulse width at the start of the period is determined by its Match register.
Page 508: And 100% Duty Cycle
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM 7.7.3 0 and 100% duty cycle To lock a channel’s MCO outputs at the state “B active, A passive”, simply write its Match register with a higher value than you write to its Limit register. The match never occurs.
Page 509: Mcpwm Capture Registers
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM Table 458. MCPWM Communication Pattern register (MCCP - address 0x400B 8040) bit description Symbol Description Reset value CCPA2 0 = MCOA2 passive, 1 = MCOA2 tracks internal MCOA0. CCPB2 0 = MCOB2 passive, 1 = MCOB2 tracks internal MCOA0.
Page 510 UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM Note: In timer mode, the period of a channel’s modulated MCO outputs is determined by its Limit register, and the pulse width at the start of the period is determined by its Match register.
Page 511 UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM Dead-time counter When the a channel’s DTE bit is set in MCCON, the dead-time counter delays the passive-to-active transitions of both MCO outputs. The dead-time counter starts counting down, from the channel’s DT value (in the MCDT register) to 0, whenever the channel’s A or B output changes from active to passive.
Page 512: Shadow Registers And Simultaneous Updates 512 Fast Abort (Abort)
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM 8.2 Shadow registers and simultaneous updates The Limit, Match, and Communication Pattern registers (MCLIM, MCMAT, and MCCP) are implemented as register pairs, each consisting of a write register and an operational register.
Page 513: Three-Phase Dc Mode
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM 8.6 Three-phase DC mode The three-phase DC mode is selected by setting the DCMODE bit in the MCCON register. In this mode, the internal MCOA0 signal can be routed to any or all of the MCO outputs.
Page 514: Three Phase Ac Mode
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM MCOB2 CCPB2 = 1, on-state CCPA2 = 1, on-state MCOA2 MCOB1 CCPB1 = 0, off-state MCOA1 CCPA1 = 1, on-state MCOB0 CCPB0 = 0, off-state CCPA0 = 1, on-state MCOA0 POLA0 = 0, INVBDC = 0 Fig 124.
Page 515: Interrupts
UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor Control PWM MCOB2 POLA2 = 0 MCOA2 MAT2 MAT2 MCOB1 POLA1 = 0 MCOA1 MAT1 MAT1 MCOB0 POLA0 = 0 MCOA0 MAT0 LIM0 LIM0 timer reset timer reset Fig 125. Three-phase AC mode sample waveforms, edge aligned PWM mode 8.8 Interrupts...
Page 516: Basic Configuration
UM10360 Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The QEI is configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bit PCQEI. Remark: On reset, the QEI is disabled (PCQEI = 0). 2.
Page 517 UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) VELOCITY velocity interrupt TIMER (TIM_Int) VELOCITY RELOAD low velocity interrupt VELOCITY (LVEL_Int) COMPARE VELOCITY CAPTURE index Ph A VELOCITY DIGITAL QUAD COUNTER FILTER Ph B DECODER PCLK encoder clock interrupt...
Page 518: Functional Description
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 4. Functional description The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture the velocity of the encoder wheel.
Page 519: Digital Input Filtering
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Table 463. Encoder direction DIR bit DIRINV bit direction forward reverse reverse forward Figure 26–127 shows how quadrature encoder signals equate to direction and count. direction position -1 -1 -1 -1...
Page 520: Velocity Compare
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) number of edges counted in a given time period is directly proportional to the velocity of the encoder. Setting the reset velocity bit (RESV) has the same effect as an overflow of the velocity timer, except that the setting the RESV bit will not generate a velocity interrupt.
Page 521: Register Description
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 6. Register description 6.1 Register summary Table 465. Register summary Symbol Address Description Control registers QEICON 0x400B C000 Control register QEICONF 0x400B C008 Configuration register QEISTAT 0x400B C004 Encoder status register...
Page 522: Qei Configuration Register (Qeiconf - 0X400B C008)
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Table 466: QEI Control register (QEICON - address 0x400B C000) bit description Symbol Description Reset value RESP Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared.
Page 523: Qei Maximum Position Register
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Table 469: QEI Position register (QEIPOS - address 0x400B C00C) bit description Symbol Description Reset value 0:31 Current position value. 6.3.2 QEI Maximum Position register (QEIMAXPOS - 0x400B C010) This register contains the maximum value of the encoder position. In forward rotation the position register resets to zero when the position register exceeds this value.
Page 524: C020)
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 6.3.6 QEI Index Count register (INXCNT - 0x400B C020) This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation.
Page 525: C034)
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 6.3.11 QEI Velocity Capture register (QEICAP - 0x400B C034) This register contains the most recently measured velocity of the encoder. This corresponds to the number of velocity pulses counted in the previous velocity timer period.The current velocity count is latched into this register when the velocity timer...
Page 526: Qei Interrupt Set Register (Qeiset - 0X400B Cfec)
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Table 482: QEI Interrupt Status register (QEIINTSTAT - address 0x400B CFE0) bit description Symbol Description Reset value INX_Int Indicates that an index pulse was detected. TIM_Int Indicates that a velocity timer overflow occurred VELC_Int Indicates that captured velocity is less than compare velocity.
Page 527: Qei Interrupt Clear Register (Qeiclr - 0X400B Cfe8)
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Table 483: QEI Interrupt Set register (QEISET - address 0x400B CFEC) bit description Symbol Description Reset value INX_Int Indicates that an index pulse was detected. TIM_Int Indicates that a velocity timer overflow occurred VELC_Int Indicates that captured velocity is less than compare velocity.
Page 528: Qei Interrupt Enable Register (Qeiie - 0X400B Cfe4)
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Table 484: QEI Interrupt Clear register (QEICLR - 0x400B CFE8) bit description Symbol Description Reset value INX_Int Indicates that an index pulse was detected. TIM_Int Indicates that a velocity timer overflow occurred VELC_Int Indicates that captured velocity is less than compare velocity.
Page 529: Qei Interrupt Enable Set Register (Qeiies - 0X400B Cfdc)
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Table 485: QEI Interrupt Enable register (QEIIE - address 0x400B CFE4) bit description Symbol Description Reset value INX_Int Indicates that an index pulse was detected. TIM_Int Indicates that a velocity timer overflow occurred VELC_Int Indicates that captured velocity is less than compare velocity.
Page 530: Qei Interrupt Enable Clear Register (Qeiiec - 0X400B Cfd8)
UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Table 486: QEI Interrupt Enable Set register (QEIIES - address 0x400B CFDC) bit description Symbol Description Reset value INX_EN Indicates that an index pulse was detected. TIM_EN Indicates that a velocity timer overflow occurred VELC_EN Indicates that captured velocity is less than compare velocity.
Page 531 UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Table 487: QEI Interrupt Enable Clear register (QEIIEC - address 0x400B CFD8) bit description Symbol Description Reset value INX_EN Indicates that an index pulse was detected. TIM_EN Indicates that a velocity timer overflow occurred VELC_EN Indicates that captured velocity is less than compare velocity.
Page 532: Basic Configuration
UM10360 Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The RTC is configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bits PCRTC. Remark: On reset, the RTC is enabled.
Page 533: Architecture
UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers 4. Architecture to main regulator DD(REG)(3v3) RTC power domain Ultra-low Power Backup power selector Registers regulator RTC power RTCX1 Ultra-low 1 Hz clock Real Time Clock RTC Alarm...
Page 534: Pin Description
UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers 5. Pin description Table 488. RTC pin description Name Type Description RTCX1 Input to the RTC oscillator circuit. RTCX2 Output from the RTC oscillator circuit. Remark: If the RTC is not used, the RTCX1/2 pins can be left floating.
Page 535: Rtc Interrupts
UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Table 489. Real-Time Clock register map Name Size Description Access Reset Address Value MONTH Months Register 0x4002 4038 YEAR Years Register 0x4002 403C CALIBRATION 18 Calibration Value Register...
Page 536: Miscellaneous Register Group
UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers 6.2 Miscellaneous register group 6.2.1 Interrupt Location Register (ILR - 0x4002 4000) The Interrupt Location Register is a 2-bit register that specifies which blocks are generating an interrupt (see Table 27–490).
Page 537: Counter Increment Interrupt Register (Ciir - 0X4002 400C)
UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers 6.2.3 Counter Increment Interrupt Register (CIIR - 0x4002 400C) The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt every time a counter is incremented. This interrupt remains valid until cleared by writing a 1 to bit 0 of the Interrupt Location Register (ILR[0]).
Page 538: Rtc Auxiliary Enable Register
UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Table 494. RTC Auxiliary control register (RTC_AUX - address 0x4002 405C) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 539: Consolidated Time Register 1 (Ctime1 - 0X4002 4018)
UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Table 496. Consolidated Time register 0 (CTIME0 - address 0x4002 4014) bit description Symbol Description Reset value Seconds Seconds value in the range of 0 to 59 Reserved, user software should not write ones to reserved bits.
Page 540: Leap Year Calculation
UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Table 499. Time Counter relationships and values Counter Size Enabled by Minimum value Maximum value Second Clk1 (see Figure 27–129) Minute Second Hour Minute Day of Month Hour...
Page 541: Calibration Procedure
UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Table 501. Calibration register (CALIBRATION - address 0x4002 4040) bit description Symbol Value Description Reset value 16:0 CALVAL If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours.
Page 542: General Purpose Registers
UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers • When the calibration counter reaches CALVAL, a calibration match occurs and the RTC timers are incremented by 2. • When the calibration event occurs, the LSB of the ALSEC register is forced to be one so that the alarm interrupt will not be missed when skipping a second.
Page 543: Chapter 28: Lpc17Xx Watchdog Timer (Wdt)
UM10360 Chapter 28: LPC17xx Watchdog Timer (WDT) Rev. 00.06 — 5 June 2009 User manual 1. Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be disabled.
Page 544: Register Description
UM10360 NXP Semiconductors Chapter 28: LPC17xx Watchdog Timer (WDT) • The Watchdog should be fed again before the Watchdog counter underflows to prevent reset/interrupt. When the Watchdog is in the reset mode and the counter underflows, the CPU will be reset, loading the stack pointer and program counter from the vector table as in the case of external reset.
Page 545: Watchdog Timer Constant Register (Wdtc - 0X4000 0004)
UM10360 NXP Semiconductors Chapter 28: LPC17xx Watchdog Timer (WDT) Table 505: Watchdog Mode register (WDMOD - address 0x4000 0000) bit description Symbol Description Reset Value WDEN WDEN Watchdog enable bit (Set Only). When 1, the watchdog timer is running. WDRESET WDRESET Watchdog reset enable bit (Set Only). When 1, a watchdog timeout will cause a chip reset.
Page 546: Watchdog Feed Register (Wdfeed - 0X4000 0008)
UM10360 NXP Semiconductors Chapter 28: LPC17xx Watchdog Timer (WDT) Table 507: Watchdog Constant register (WDTC - address 0x4000 0004) bit description Symbol Description Reset Value 31:0 Count Watchdog time-out interval. 0x0000 00FF 4.3 Watchdog Feed register (WDFEED - 0x4000 0008) Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the WDTC value.
Page 547: Block Diagram
UM10360 NXP Semiconductors Chapter 28: LPC17xx Watchdog Timer (WDT) Table 510: Watchdog Timer Clock Source Selection register (WDCLKSEL - address 0x4000 0010) bit description Symbol Value Description Reset Value WDSEL These bits select the clock source for the Watchdog timer as described below.
Page 548 UM10360 NXP Semiconductors Chapter 28: LPC17xx Watchdog Timer (WDT) feed sequence WDTC feed ok WDFEED feed error RTC oscillator wdclk ÷ 4 32-BIT DOWN COUNTER pclk internal RC oscillator underflow enable count WDCLKSEL WDTV SHADOW BIT WMOD register WDINT WDTOF WDRESET...
Page 549: Basic Configuration
UM10360 Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The ADC is configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set the PCADC bit. Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit, and then enable the ADC in the AD0CR register (bit PDN Table 29–513).
Page 550: Register Description
UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) Table 511. ADC pin description Type Description AD0.7 to AD0.0 Input Analog Inputs. The ADC cell can measure the voltage on any of these input signals. Note that these analog inputs are always connected to their pins, even if the Pin function Select register assigns them to port pins.
Page 551 UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) Table 512. ADC registers Generic Description Access Reset value Name Address & Name ADDR7 A/D Channel 7 Data Register. This register contains the result of 0x4003 402C the most recent conversion completed on channel 7.
Page 552: A/D Global Data Register (Ad0Gdr - 0X4003 4004)
UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) Table 513: A/D Control Register (AD0CR - address 0x4003 4000) bit description Symbol Value Description Reset value 26:24 START When the BURST bit is 0, these bits control whether and when an A/D conversion is started: No start (this value should be used when clearing PDN to 0).
Page 553: A/D Interrupt Enable Register (Ad0Inten - 0X4003 400C)
UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) Table 514: A/D Global Data Register (AD0GDR - address 0x4003 4004) bit description Symbol Description Reset value 29:27 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 554: A/D Data Registers (Ad0Dr0 To Ad0Dr7 - 0X4003 4010 To 0X4003 402C)
UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) 5.4 A/D Data Registers (AD0DR0 to AD0DR7 - 0x4003 4010 to 0x4003 402C) The A/D Data Registers hold the result of the last conversion for each A/D channel, when an A/D conversion is complete. They also include the flags that indicate when a conversion has been completed and when a conversion overrun has occurred.
Page 555: A/D Trim Register (Adtrim - 0X4003 4034)
UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) Table 517: A/D Status register (AD0STAT - address 0x4003 4030) bit description Symbol Description Reset value OVERRUN3 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3.
Page 556: Accuracy Vs. Digital Receiver
UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) 6.3 Accuracy vs. digital receiver The ADC function must be selected via the PINSEL registers in order to get accurate voltage readings on the monitored pin. The PINMODE should also be set to the mode for which neither pull-up nor pull-down resistor is enabled.
Page 557: Basic Configuration
UM10360 Chapter 30: LPC17xx Digital-to-Analog Converter (DAC) Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The DAC is configured using the following registers: 1. Power: The DAC is always connected to V . Register access is determined by PINSEL and PINMODE settings (see below).
Page 558: Register Description
UM10360 NXP Semiconductors Chapter 30: LPC17xx Digital-to-Analog Converter (DAC) 4. Register description The DAC registers are shown in Table 30–520. Note that the DAC does not have a control bit in the PCONP register. To enable the DAC, its output must be selected to appear on the related pin, P0.26, by configuring the PINSEL1 register.
Page 559: D/A Converter Counter Value Register
UM10360 NXP Semiconductors Chapter 30: LPC17xx Digital-to-Analog Converter (DAC) Table 522. D/A Control register (DACCTRL - address 0x4008 C004) bit description Symbol Value Description Reset Value INT_DMA_REQ 0 This bit is cleared on any write to the DACR register. This bit is set by hardware when the timer times out.
Page 560: Double Buffering
UM10360 NXP Semiconductors Chapter 30: LPC17xx Digital-to-Analog Converter (DAC) 5.2 Double buffering Double-buffering is enabled only if both, the CNT_ENA and the DBLBUF_ENA bits are set in DACCTRL. In this case, any write to the DACR register will only load the pre-buffer, which shares its register address with the DACR register.
Page 561: Basic Configuration
UM10360 Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Rev. 00.06 — 5 June 2009 User manual 1. Basic configuration The GPDMA is configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bit PCGPDMA. Remark: On reset, the GPDMA is disabled (PCGPDMA = 0). 2.
Page 562: Functional Description
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. • Supports 8-bit, 16-bit, and 32-bit wide transactions.
Page 563: Ahb Slave Interface
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller 4.1.1 AHB slave interface All transactions to DMA Controller registers on the AHB slave interface are 32 bits wide. 8-bit and 16-bit accesses are not supported and will result in an exception.
Page 564 UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Table 524. Endian behavior Source Destination Source Destination Source Source data Destination Destination data endian endian width width transfer transfer no/byte lane no/byte lane Little Little 1/[7:0] 1/[7:0] 21212121...
Page 565 UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Table 524. Endian behavior …continued Source Destination Source Destination Source Source data Destination Destination data endian endian width width transfer transfer no/byte lane no/byte lane 1/[31:24] 1/[15:0] 12341234 2/[23:16]...
Page 566: Channel Hardware
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller 4.1.7 Channel hardware Each stream is supported by a dedicated hardware channel, including source and destination controllers, as well as a FIFO. This enables better latency than a DMA controller with only a single hardware channel shared between several DMA streams and simplifies the control logic.
Page 567: Dma Request Connections
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller 4.2.3 DMA request connections The connection of the GPDMA to the supported peripheral devices depends on the DMA functions implemented in those peripherals. Table 31–525 shows the DMA Request numbers used by the supported peripherals.
Page 568 UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Table 526. GPDMA register map …continued Name Description Reset state Access Address DMACRawIntErrStat DMA Raw Error Interrupt Status Register 0x5000 4018 DMACEnbldChns DMA Enabled Channel Register 0x5000 401C DMACSoftBReq...
Page 569: 0X5000 4000)
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Table 526. GPDMA register map …continued Name Description Reset state Access Address DMACC5SrcAddr DMA Channel 5 Source Address Register 0x5000 41A0 DMACC5DestAddr DMA Channel 5 Destination Address Register 0x5000 41A4...
Page 570: Register (Dmacinttcclear - 0X5000 4008)
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Table 528. DMA Interrupt Terminal Count Request Status register (DMACIntTCStat - 0x5000 4004) Name Function IntTCStat Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request.
Page 571: Dma Raw Interrupt Terminal Count Status Register
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Table 531. DMA Interrupt Error Clear register (DMACIntErrClr - 0x5000 4010) Name Function IntErrClr Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect.
Page 572: Dma Software Burst Request Register
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Table 534. DMA Enabled Channel register (DMACEnbldChns - 0x5000 401C) Name Function EnabledChannels Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled.
Page 573: Dma Software Last Burst Request Register
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller 5.11 DMA Software Last Burst Request register (DMACSoftLBReq - 0x5000 4028) The DMACSoftLBReq Register is read/write and enables DMA last burst requests to be generated by software. A DMA request can be generated for each source by writing a 1 to the corresponding register bit.
Page 574: Dma Synchronization Register (Dmacsync - 0X5000 4034)
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Table 539. DMA Configuration register (DMACConfig - 0x5000 4030) Name Function DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled. AHB Master endianness configuration: 0 = little-endian mode (default).
Page 575: Dma Channel Registers
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Table 541. DMA Request Select register (DMAReqSel - 0x4000 C1C4) …continued Name Function DMASEL11 Selects the DMA request for GPDMA input 11: 0 - UART1 RX is selected. 1 - Timer 1match 1 is selected.
Page 576: Dma Channel Destination Address Registers (Dmaccxdestaddr - 0X5000 41X4)
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Note: The source and destination addresses must be aligned to the source and destination widths. Table 31–542 shows the bit assignments of the DMACCxSrcAddr Registers. Table 542. DMA Channel Source Address registers (DMACCxSrcAddr - 0x5000 41x0)
Page 577: Protection And Access Information
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller has processed the value read, the channel may have advanced. It is intended to be read only when a channel has stopped. Table 31–545 shows the bit assignments of the DMACCxControl Register.
Page 578: Dma Channel Configuration Registers (Dmaccxconfig - 0X5000 41X0)
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Table 545. DMA channel control registers (DMACCxControl - 0x5000 41xC) …continued Name Function 20:18 SWidth Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other.
Page 579 UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Table 546. DMA Channel Configuration registers (DMACCxConfig - 0x5000 41x0) Name Function Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled.
Page 580: Lock Control
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller 5.21.1 Lock control The lock control may set the lock bit by writing a 1 to bit 16 of the DMACCxConfig Register. When a burst occurs, the AHB arbiter will not de-grant the master during the burst until the lock is de-asserted.
Page 581: Setting Up A New Dma Transfer
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller • By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost if this method is used. • By using the active and halt bits in conjunction with the channel enable bit.
Page 582: Flow Control
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller 6.2 Flow control The device that controls the length of the packet is known as the flow controller. On the LPC17xx, the flow controller is always the DMA Controller, and the packet length is programmed by software before the DMA channel is enabled.
Page 583: Peripheral-To-Peripheral Dma Flow
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller – If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr, DMACCxDestAddr, DMACCxLLI, and DMACCxControl registers and go to back to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow sequence ends.
Page 584: Interrupt Requests
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller – If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr, DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to back to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow sequence ends.
Page 585: Word-Aligned Transfers Across A Boundary
UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller 6.4.1 Word-aligned transfers across a boundary The channel is configured for 16-transfer bursts, each transfer 32-bits wide, to a destination for which address incrementing is enabled. The start address for the current burst is 0x0C000024, the next boundary (calculated from the burst size and transfer width) is 0x0C000040.
Page 586 UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller 3. Write the first linked list item, previously written to memory, to the relevant channel in the DMA Controller. 4. Write the channel configuration information to the channel Configuration Register and set the Channel Enable bit.
Page 587 UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller • Source and destination burst sizes, 16 transfers. • Next LLI address, 0x20020. A chain of descriptors is built up, each one pointing to the next in the series. To initialize the DMA stream, the first LLI, 0x20000, is programmed into the DMA Controller.
Page 588: Introduction
UM10360 Chapter 32: LPC17xx Flash memory interface and programming Rev. 00.06 — 5 June 2009 User manual 1. Introduction The boot loader controls initial operation after reset and also provides the tools for programming the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system.
Page 589: Criterion For Valid User Code
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming Fig 134. Map of lower memory 3.1.1 Criterion for Valid User Code The reserved Cortex-M3 exception vector location 7 (offset 0x 001C in the vector table) should contain the 2’s complement of the check-sum of table entries 0 through 6. This causes the checksum of the first 8 table entries to be 0.
Page 590: Communication Protocol
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming the auto-baud routine waits again for a synchronization character. For auto-baud to work correctly in case of user invoked ISP, the CCLK frequency should be greater than or equal to 10 MHz.
Page 591: Interrupts During Iap
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 3.2.6 Interrupts during IAP The on-chip flash memory is not accessible during erase/write operations. When the user application code starts executing the interrupt vectors from the user flash area are active.
Page 592: Boot Process Flowchart
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 4. Boot process flowchart RESET INITIALIZE CRP1/2/3 ENABLED? ENABLE DEBUG WATCHDOG FLAG SET? USER CODE VALID? CRP3 ENABLED? EXECUTE INTERNAL USER CODE Enter ISP USER CODE VALID? MODE? (P2.10=LOW)
Page 593: Sector Numbers
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 5. Sector numbers Some IAP and ISP commands operate on "sectors" and specify sector numbers. The following table indicate the correspondence between sector numbers and memory addresses for LPC17xx devices containing 32, 64, 128, 256 and 512 kB of flash respectively.
Page 594: Code Read Protection (Crp)
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 6. Code Read Protection (CRP) Code Read Protection is a mechanism that allows user to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted.
Page 595: Isp Commands
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming Table 551. Code Read Protection hardware/software interaction CRP option User Code P2.10 pin at JTAG enabled LPC17xx partial flash Valid reset enters ISP update in ISP mode mode High...
Page 596: Unlock
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming Table 552. ISP command summary ISP Command Usage Described in Read Boot Code version K Table 32–566 Read serial number Table 32–567 Compare M <address1> <address2> <number of bytes>...

Page 597: Echo
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 7.3 Echo <setting> Table 556. ISP Echo command Command Input Setting: ON = 1 | OFF = 0 Return Code CMD_SUCCESS | PARAM_ERROR Description The default setting for echo command is ON. When ON the ISP command handler sends the received serial data back to the host.

Page 598: Prepare Sector(S) For Write Operation
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming "OK<CR><LF>" to continue further transmission. If the check-sum does not match then the host should respond with "RESEND<CR><LF>". In response the ISP command handler sends the data again. Table 558. ISP Read Memory command...

Page 599: Copy Ram To Flash
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 7.7 Copy RAM to Flash <flash address> <RAM address> <no of bytes> Table 560. ISP Copy command Command Input Flash Address(DST): Destination flash address where data bytes are to be written.

Page 600: Sector Number
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 7.9 Erase sector(s) <start sector number> <end sector number> Table 562. ISP Erase sector command Command Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number.
Page 601: Read Boot Code Version Number
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming Table 565. LPC17xx part identification numbers Device ASCII/dec coding Hex coding LPC1768 81719 0x13F37 LPC1766 81715 0x13F33 LPC1765 79667 0x13733 LPC1764 71970 0x11922 LPC1758 81716 0x13F34 LPC1756 71459 0x11723...
Page 602: Isp Return Codes
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 7.14 Compare <address1> <address2> <no of bytes> Table 568. ISP Compare command Command Input Address1 (DST): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.
Page 603: Iap Commands
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming Table 569. ISP Return Codes Summary Return Mnemonic Description Code ADDR_NOT_MAPPED Address is not mapped in the memory map. Count value is taken in to consideration where applicable. CMD_LOCKED Command is locked.
Page 604 UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming Setting function pointer: iap_entry=(IAP) IAP_LOCATION; Whenever you wish to call IAP you could use the following statement. iap_entry (command, result); The IAP call could be simplified further by using the symbol definition file feature supported by ARM Linker in ADS (ARM Developer Suite).
Page 605: Prepare Sector(S) For Write Operation
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming COMMAND CODE command PARAMETER 1 parameter table PARAMETER 2 ARM REGISTER r0 PARAMETER n ARM REGISTER r1 STATUS CODE RESULT 1 command result table RESULT 2 RESULT n Fig 136. IAP parameter passing 8.1 Prepare sector(s) for write operation...
Page 606: Copy Ram To Flash
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 8.2 Copy RAM to Flash Table 572. IAP Copy RAM to Flash command Command Copy RAM to Flash Input Command code: 51 Param0(DST): Destination flash address where data bytes are to be written. This address should be a 256 byte boundary.
Page 607: Blank Check Sector(S)
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 8.4 Blank check sector(s) Table 574. IAP Blank check sector(s) command Command Blank check sector(s) Input Command code: 53 Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number).
Page 608: Read Device Serial Number
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 8.7 Read device serial number Table 577. IAP Read device serial number command Command Read device serial number Input Command code: 58 Parameters: None Return Code CMD_SUCCESS | Result...
Page 609: Iap Status Codes
UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming Table 579. Re-invoke ISP Command Compare Return Code None Result None. Description This command is used to invoke the boot loader in ISP mode. It maps boot vectors, sets PCLK = CCLK / 4, configures UART0 pins Rx and Tx, resets...
Page 610: Chapter 33: Lpc17Xx Jtag, Serial Wire Debug, And Trace
UM10360 Chapter 33: LPC17xx JTAG, Serial Wire Debug, and Trace Rev. 00.06 — 5 June 2009 User manual 1. Features • Supports both standard JTAG and ARM Serial Wire Debug modes. • Direct debug access to all memories, registers, and peripherals. •...
Page 611: Debug Notes
UM10360 NXP Semiconductors Chapter 33: LPC17xx JTAG, Serial Wire Debug, and Trace Table 581. JTAG pin description Pin Name Type Description Input JTAG Test Clock. This pin is the clock for debug logic when in the JTAG debug mode. Input JTAG Test Mode Select.
Page 612 UM10360 NXP Semiconductors Chapter 33: LPC17xx JTAG, Serial Wire Debug, and Trace Another issue is that debug mode changes the way in which reduced power modes are handled by the Cortex-M3 CPU. This causes power modes at the device level to be different from normal modes operation.
Page 613: Chapter 34: Appendix: Cortex-M3 User Guide
UM10360 Chapter 34: Appendix: Cortex-M3 User Guide Rev. 00.06 — 5 June 2009 User manual 1. ARM Cortex-M3 User Guide: Introduction The material in this appendix is provided by ARM Limited for inclusion in the User Manuals of devices containing the Cortex-M3 CPU. Minimal changes have been made to reflect implementation options and other distinctions that apply specifically to LPC17xx devices.
Page 614: System Level Interface
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb instruction set, ensuring high code density and reduced program memory requirements.
Page 615: Cortex-M3 Processor Features And Benefits Summary
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide LPC17xx devices support JTAG and Serial Wire Debug, Serial Wire Viewer, and include the Embedded Trace Macrocell. See Section 33–1 for additional information. 1.1.3 Cortex-M3 processor features and benefits summary •...
Page 616: Arm Cortex-M3 User Guide: Instruction Set
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2. ARM Cortex-M3 User Guide: Instruction Set 2.1 Instruction set summary The processor implements a version of the Thumb instruction set. Table 34–584 lists the supported instructions. Note Table 34–584: •...
Page 617 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 584. Cortex-M3 instructions …continued Mnemonic Operands Brief description Flags Page Instruction Synchronization Barrier Section 34–2.10.5 If-Then condition block Section 34–2.9.3 Load Multiple registers, increment after Section 34–2.4.6 Rn{!}, reglist Load Multiple registers, decrement before Section 34–2.4.6...
Page 618 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 584. Cortex-M3 instructions …continued Mnemonic Operands Brief description Flags Page Signed Divide Section 34–2.6.3 SDIV {Rd,} Rn, Rm Send Event Section 34–2.10.9 Signed Multiply with Accumulate (32 x 32 + 64), Section 34–2.6.2...
Page 619: Intrinsic Functions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.2 Intrinsic functions ANSI cannot directly access some Cortex-M3 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, you might have to use inline assembler to access some instructions.
Page 620: Operands
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • Section 34–2.3.1 “Operands” • Section 34–2.3.2 “Restrictions when using PC or SP” • Section 34–2.3.3 “Flexible second operand” • Section 34–2.3.4 “Shift Operations” • Section 34–2.3.5 “Address alignment” • Section 34–2.3.6 “PC-relative expressions”...
Page 621: Shift Operations
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Remark: In the constants shown above, X and Y are hexadecimal digits. In addition, in a small number of instructions, constant can take a wider range of values. These are described in the individual instruction descriptions.
Page 622 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide The permitted shift lengths depend on the shift type and the instruction, see the individual instruction description or Section 34–2.3.3. If the shift length is 0, no shift occurs. Register shift operations update the carry flag except when the specified shift length is 0. The following sub-sections describe the various shift operations and how they affect the carry flag.
Page 623 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • If n is 33 or more and the carry flag is updated, it is updated to 0. Fig 139. LSR#3 2.3.4.3 LSL Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result.
Page 624: Address Alignment
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to bit[31] of Rm.
Page 625: Pc-Relative Expressions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned. To avoid accidental generation of...
Page 626 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Use the CBZ and CBNZ instructions to compare the value of a register against zero and branch on the result. This section describes: • Section 34–2.3.7.1 “The condition flags” • Section 34–2.3.7.2 “Condition code suffixes”.
Page 627: Instruction Width Selection
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 587. Condition code suffixes Suffix Flags Meaning N = 0 Positive or zero V = 1 Overflow V = 0 No overflow C = 1 and Z = 0 Higher, unsigned >...
Page 628 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.3.8.1 Example: Instruction width selection BCS.W label ; creates a 32-bit instruction even for a short branch ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same ; operation can be done by a 16-bit instruction UM10360_0 ©...
Page 629: Memory Access Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.4 Memory access instructions Table 34–588 shows the memory access instructions: Table 588. Memory access instructions Mnemonic Brief description Load PC-relative address Section 34–2.4.1 Clear Exclusive Section 34–2.4.9 CLREX Load Multiple registers Section 34–2.4.6...
Page 630: Adr
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.4.1 ADR Load PC-relative address. 2.4.1.1 Syntax ADR{cond} Rd, label where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. label is a PC-relative expression. See Section 34–2.3.6 “PC-relative...
Page 631: Ldr And Str, Immediate Offset
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.4.2 LDR and STR, immediate offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. 2.4.2.1 Syntax op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset op{type}{cond} Rt, [Rn, #offset]! ;...
Page 632 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide [Rn, #offset] • Pre-indexed addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn.
Page 633 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.4.2.5 Examples R8, [R10] ; Loads R8 from the address in R10. LDRNE R2, [R5, #960]! ; Loads (conditionally) R2 from a word ; 960 bytes above the address in R5, and ;...
Page 634: Ldr And Str, Register Offset
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.4.3 LDR and STR, register offset Load and Store with register offset. 2.4.3.1 Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}] where: op is one of: LDR: Load Register. STR: Store Register.
Page 635 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address • if the instruction is conditional, it must be the last instruction in the IT block.
Page 636: Ldr And Str, Unprivileged
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.4.4 LDR and STR, unprivileged Load and Store with unprivileged access. 2.4.4.1 Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where: op is one of: LDR: Load Register. STR: Store Register.
Page 637 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.4.4.5 Examples STRBTEQ R4, [R7] ; Conditionally store least significant byte in ; R4 to an address in R7, with unprivileged access LDRHT R2, [R2, #8] ; Load halfword value from an address equal to ;...
Page 638: Ldr, Pc-Relative
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.4.5 LDR, PC-relative Load register from memory. 2.4.5.1 Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label ; Load two words type is one of: B: unsigned byte, zero extend to 32 bits on loads.
Page 639 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address • if the instruction is conditional, it must be the last instruction in the IT block.
Page 640: Ldm And Stm
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.4.6 LDM and STM Load and Store Multiple registers. 2.4.6.1 Syntax op{addr_mode}{cond} Rn{!}, reglist where: op is one of: LDM: Load Multiple registers. STM: Store Multiple registers. addr_mode is any one of the following: IA: Increment address After each access.
Page 641 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist.
Page 642: Push And Pop
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.4.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. 2.4.7.1 Syntax PUSH{cond} reglist POP{cond} reglist where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.
Page 643: Ldrex And Strex
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.4.8 LDREX and STREX Load and Store Register Exclusive. 2.4.8.1 Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn]...
Page 644 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • do not use PC • do not use SP for Rd and Rt • for STREX, Rd must be different from both Rt and Rn • the value of offset must be a multiple of four in the range 0-1020.
Page 645: Clrex
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.4.9 CLREX Clear Exclusive. 2.4.9.1 Syntax CLREX{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.4.9.2 Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to perform the store.
Page 646: General Data Processing Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.5 General data processing instructions Table 34–591 shows the data processing instructions: Table 591. Data processing instructions Mnemonic Brief description Add with Carry Section 34–2.5.1 Section 34–2.5.1 Section 34–2.5.1 ADDW Logical AND Section 34–2.5.2...
Page 647: Add, Adc, Sub, Sbc, And Rsb
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.5.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. 2.5.1.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only...
Page 648 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide – Rn must also be SP – any shift in Operand2 must be limited to a maximum of 3 bits using LSL • Rn can be SP only in ADD and SUB •...
Page 649 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 96-bit subtraction: SUBS R6, R6, R9 ; subtract the least significant words SBCS R9, R2, R1 ; subtract the middle words with carry R2, R8, R11 ; subtract the most significant words with carry UM10360_0 ©...
Page 650: And, Orr, Eor, Bic, And Orn
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.5.2 AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. 2.5.2.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 where: op is one of: AND: logical AND.
Page 651 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide EORS R7, R11, #0x18181818 R0, R1, #0xab R7, R11, R14, ROR #4 ORNS R7, R11, R14, ASR #32 UM10360_0 © NXP B.V. 2009. All rights reserved. User manual Rev. 00.06 — 5 June 2009...
Page 652: Asr, Lsl, Lsr, Ror, And Rrx
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.5.3 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. 2.5.3.1 Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n...
Page 653 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.5.3.4 Condition flags If S is specified: • these instructions update the N and Z flags according to the result • the C flag is updated to the last bit shifted out, except when the shift length is 0, see Section 34–2.3.4 “Shift...
Page 654: Clz
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.5.4 CLZ Count Leading Zeros. 2.5.4.1 Syntax CLZ{cond} Rd, Rm where: cond is an optional condition code, see Section 34–2.3.7. Rd is the destination register. Rm is the operand register. 2.5.4.2 Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd.
Page 655: Cmp And Cmn
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.5.5 CMP and CMN Compare and Compare Negative. 2.5.5.1 Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see Section 34–2.3.7. Rn is the register holding the first operand.
Page 656: Mov And Mvn
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.5.6 MOV and MVN Move and Move NOT. 2.5.6.1 Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S is an optional suffix. If S is specified, the condition code flags are updated on the result...
Page 657 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.5.6.3 Restrictions You can use SP and PC only in the MOV instruction, with the following restrictions: • the second operand must be a register without shift • you must not specify the S suffix.
Page 658: Movt
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.5.7 MOVT Move Top. 2.5.7.1 Syntax MOVT{cond} Rd, #imm16 where: cond is an optional condition code, see Section 34–2.3.7. Rd is the destination register. imm16 is a 16-bit immediate constant. 2.5.7.2 Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register.
Page 659: Rev, Rev16, Revsh, And Rbit
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.5.8 REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. 2.5.8.1 Syntax op{cond} Rd, Rn where: op is any of: REV Reverse byte order in a word. REV16 Reverse byte order in each halfword independently.
Page 660: Tst And Teq
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.5.9 TST and TEQ Test bits and Test Equivalence. 2.5.9.1 Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rn is the register holding the first operand.
Page 661: Multiply And Divide Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.6 Multiply and divide instructions Table 34–592 shows the multiply and divide instructions: Table 592. Multiply and divide instructions Mnemonic Brief description Multiply with Accumulate, 32-bit result Section 34–2.6.1 Multiply and Subtract, 32-bit result Section 34–2.6.1...
Page 662: Mul, Mla, And Mls
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.6.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. 2.6.1.1 Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ;...
Page 663 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.6.1.5 Examples R10, R2, R5 ; Multiply, R10 = R2 x R5 R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 x R1) + R5 MULS R0, R2, R2 ;...
Page 664: Umull, Umlal, Smull, And Smlal
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.6.2 UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. 2.6.2.1 Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL: Unsigned Long Multiply.
Page 665 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.6.2.5 Examples UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 x R6 SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 x R8 UM10360_0 © NXP B.V. 2009. All rights reserved.
Page 666: Sdiv And Udiv
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.6.3 SDIV and UDIV Signed Divide and Unsigned Divide. 2.6.3.1 Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.
Page 667: Saturating Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.7 Saturating instructions This section describes the saturating instructions, SSAT and USAT. 2.7.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. 2.7.1.1 Syntax...
Page 668 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • otherwise, the result returned is the same as the value to be saturated. If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the instruction sets the Q flag to 1 in the APSR.
Page 669: Bitfield Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.8 Bitfield instructions Table 34–593 shows the instructions that operate on adjacent sets of bits in registers or bitfields: Table 593. Packing and unpacking instructions Mnemonic Brief description Bit Field Clear Section 34–2.8.1...
Page 670: Bfc And Bfi
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.8.1 BFC and BFI Bit Field Clear and Bit Field Insert. 2.8.1.1 Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.
Page 671: Sbfx And Ubfx
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.8.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. 2.8.2.1 Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see Section 34–2.3.7 “Conditional...
Page 672: Sxt And Uxt
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.8.3 SXT and UXT Sign extend and Zero extend. 2.8.3.1 Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: B: Extends an 8-bit value to a 32-bit value.
Page 673 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.8.3.5 Examples SXTH R4, R6, ROR #16 ; Rotate R6 right by 16 bits, then obtain the lower ; halfword of the result and then sign extend to ; 32 bits and write the result to R4.
Page 674: Branch And Control Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.9 Branch and control instructions Table 34–594 shows the branch and control instructions: Table 594. Branch and control instructions Mnemonic Brief description Branch Section 34–2.9.1 Branch with Link Section 34–2.9.1 Branch indirect with Link Section 34–2.9.1...
Page 675: B, Bl, Bx, And Blx
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.9.1 B, BL, BX, and BLX Branch instructions. 2.9.1.1 Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: B is branch (immediate). BL is branch with link (immediate). BX is branch indirect (register).
Page 676 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.9.1.3 Restrictions The restrictions are: • do not use PC in the BLX instruction • for BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address created by changing bit[0] to 0 •...
Page 677: Cbz And Cbnz
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.9.2 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. 2.9.2.1 Syntax CBZ Rn, label CBNZ Rn, label where: Rn is the register holding the operand. label is the branch destination.
Page 678 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.9.3 IT If-Then condition instruction. 2.9.3.1 Syntax IT{x{y{z}}} cond where: x specifies the condition switch for the second instruction in the IT block. y specifies the condition switch for the third instruction in the IT block.
Page 679 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • CPSID and CPSIE. Other restrictions when using an IT block are: • a branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction inside the IT block. These are: –...
Page 680 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide ; Next instruction is conditional R0, R0, R1 ; Syntax error: no condition code used in IT block UM10360_0 © NXP B.V. 2009. All rights reserved. User manual Rev. 00.06 — 5 June 2009...
Page 681: Tbb And Tbh
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.9.4 TBB and TBH Table Branch Byte and Table Branch Halfword. 2.9.4.1 Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: Rn is the register containing the address of the table of branch lengths.
Page 682 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the ; branch table BranchTable_H ((CaseA - BranchTable_H)/2) ; CaseA offset calculation ((CaseB - BranchTable_H)/2) ; CaseB offset calculation ((CaseC - BranchTable_H)/2) ;...
Page 683: Miscellaneous Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10 Miscellaneous instructions Table 34–596 shows the remaining Cortex-M3 instructions: Table 596. Miscellaneous instructions Mnemonic Brief description Breakpoint Section 34–2.10.1 BKPT Change Processor State, Disable Interrupts Section 34–2.10.2 CPSID Change Processor State, Enable Interrupts Section 34–2.10.2...
Page 684: Bkpt
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10.1 BKPT Breakpoint. 2.10.1.1 Syntax BKPT #imm where: imm is an expression evaluating to an integer in the range 0-255 (8-bit value). 2.10.1.2 Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
Page 685: Cps
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10.2 CPS Change Processor State. 2.10.2.1 Syntax CPSeffect iflags where: effect is one of: IE Clears the special purpose register. ID Sets the special purpose register iflags is a sequence of one or more flags: i Set or clear PRIMASK.
Page 686: Dmb
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10.3 DMB Data Memory Barrier. 2.10.3.1 Syntax DMB{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.10.3.2 Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction.
Page 687: Dsb
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10.4 DSB Data Synchronization Barrier. 2.10.4.1 Syntax DSB{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.10.4.2 Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes.
Page 688: Isb
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10.5 ISB Instruction Synchronization Barrier. 2.10.5.1 Syntax ISB{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.10.5.2 Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from cache or memory again, after the ISB instruction has been completed.
Page 689: Mrs
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10.6 MRS Move the contents of a special register to a general-purpose register. 2.10.6.1 Syntax MRS{cond} Rd, spec_reg where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register.
Page 690: Msr
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10.7 MSR Move the contents of a general-purpose register into the specified special register. 2.10.7.1 Syntax MSR{cond} spec_reg, Rn where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.
Page 691: Nop
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10.8 NOP No Operation. 2.10.8.1 Syntax NOP{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.10.8.2 Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage.
Page 692: Sev
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10.9 SEV Send Event. 2.10.9.1 Syntax SEV{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.10.9.2 Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system.
Page 693: Svc
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10.10 SVC Supervisor Call. 2.10.10.1 Syntax SVC{cond} #imm where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. imm is an expression evaluating to an integer in the range 0-255 (8-bit value).
Page 694: Wfe
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10.11 WFE Wait For Event. 2.10.11.1 Syntax WFE{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution” 2.10.11.2 Operation WFE is a hint instruction. If the event register is 0, WFE suspends execution until one of the following events occurs: •...
Page 695: Wfi
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 2.10.12 WFI Wait for Interrupt. 2.10.12.1 Syntax WFI{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.10.12.2 Operation WFI is a hint instruction that suspends execution until one of the following events occurs: •...
Page 696: Arm Cortex-M3 User Guide: Processor
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 3. ARM Cortex-M3 User Guide: Processor 3.1 Programmers model This section describes the Cortex-M3 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks.
Page 697: Core Registers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 597. Summary of processor mode, execution privilege level, and stack use options Processor Used to Privilege level for Stack used mode execute software execution Thread Applications Privileged or Main stack or process...
Page 698 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 598. Core register set summary Name Type Required Reset Description privilege value EPSR Privileged Table 34–602 0x01000000 PRIMASK Privileged Table 34–603 0x00000000 FAULTMASK Privileged Table 34–604 0x00000000 BASEPRI Privileged Table 34–605...
Page 699 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide The PSR bit assignments are: Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example: •...
Page 700 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 600. APSR bit assignments Bits Name Function [31] Negative or less than flag: 0 = operation result was positive, zero, greater than, or equal 1 = operation result was negative or less than.
Page 701 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 601. IPSR bit assignments Bits Name Function [31:9] Reserved [8:0] ISR_NUMBER This is the number of the current exception: 0 = Thread mode 1 = Reserved 2 = NMI 3 = Hard fault...
Page 702 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are ignored. Fault handlers can examine EPSR value in the stacked PSR to indicate the operation that is at fault.
Page 703 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Base Priority Mask Register: The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. See the register summary in Table 34–598...
Page 704: Exceptions And Interrupts
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 3.1.4 Exceptions and interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset.
Page 705 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide The following sections give more information about the CMSIS: • Section 34–3.5.4 • Section 36–1.2 “Intrinsic functions” • Section 37–1.2.1 “The CMSIS mapping of the Cortex-M3 NVIC registers” • Section 37–1.2.10.1 “NVIC programming hints”.
Page 706: Memory Model
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 3.2 Memory model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. The memory map is: The regions for SRAM and peripherals include bit-band regions.
Page 707 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • Normal: The processor can re-order transactions for efficiency, or perform speculative reads. • Device: The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. • Strongly-ordered: The processor preserves transaction order relative to all other transactions.
Page 708: Behavior Of Memory Accesses
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide ‘<‘ means that accesses are observed in program order, that is, A1 is always observed before A2. 3.2.3 Behavior of memory accesses The behavior of accesses to each region in the memory map is: Table 607.
Page 709: Bit-Banding
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. See Section 36–1.10.3 “DMB”. • The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute.
Page 710 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide The memory map has two 32MB alias regions that map to two 1MB bit-band regions: • accesses to the 32MB SRAM alias region map to the 1MB SRAM bit-band region, as shown in Table 34–608...
Page 711 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF: 0x23FFFFFC = 0x22000000 + (0xFFFFF*32) + (7*4). • The alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000: 0x22000000 = 0x22000000 + (0*32) + (0 *4).
Page 712: Memory Endianness
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 3.2.6 Memory endianness The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word.
Page 713: Programming Hints For The Synchronization Primitives
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform a guaranteed read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location.
Page 714 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide __ldrex((volatile char *) 0xFF); UM10360_0 © NXP B.V. 2009. All rights reserved. User manual Rev. 00.06 — 5 June 2009 714 of 808...
Page 715: Exception Model
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 3.3 Exception model This section describes the exception model. 3.3.1 Exception states Each exception is in one of the following states: • Inactive The exception is not active and not pending.
Page 716 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide A memory management fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled.
Page 717: Exception Handlers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 611. Properties of the different exception types Exception Exception Priority Vector address Activation number number type or offset Bus fault Configurable Synchronous when 0x00000014 precise, asynchronous when imprecise Usage fault...
Page 718: Vector Table
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 3.3.4 Vector table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 34–144 shows the order of the exception vectors in the vector table.
Page 719: Interrupt Priority Grouping
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • Section 37–1.3.9 “System Handler Priority Registers” • Section 37–1.2.7 “Interrupt Priority Registers”. Remark: Configurable priority values are in the range 0 to 31. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception.
Page 720 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide – there is no pending exception with sufficient priority to be serviced – the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred.
Page 721 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide The stack frame includes the return address. This is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes.
Page 722 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 612. Exception return behavior EXC_RETURN[3:0] Description b1001 Return to Thread mode. Exception return gets state from MSP. Execution uses MSP after return. b1101 Return to Thread mode. Exception return gets state from PSP.
Page 723: Fault Handling
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 3.4 Fault handling Faults are a subset of the exceptions, see Section 34–3.3. The following generate a fault: • a bus error on: – an instruction fetch or vector table load –...
Page 724: Fault Escalation And Hard Faults
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 3.4.2 Fault escalation and hard faults All faults exceptions except for hard fault have configurable exception priority, see Section 37–1.3.9 “System Handler Priority Registers”. Software can disable execution of the handlers for these faults, see Section 37–1.3.10 “System Handler Control and State...
Page 725: Lockup
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 3.4.4 Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in lockup state it does not execute any instructions.
Page 726: Power Management
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 3.5 Power management Note: NXP devices based on the Cortex-M3 processor, including the LPC17xx, support additional reduced power modes. See Section 4–8 “Power control” information on all available reduced power modes.
Page 727: Wakeup From Sleep Mode
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 3.5.1.3 Sleep-on-exit If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of an exception handler it returns to Thread mode and immediately enters sleep mode.
Page 728: Power Management Programming Hints
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 3.5.4 Power management programming hints ANSI C cannot directly generate the WFI and WFE instructions. The CMSIS provides the following intrinsic functions for these instructions: void __WFE(void) // Wait for Event...
Page 729: Arm Cortex-M3 User Guide: Peripherals
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 4. ARM Cortex-M3 User Guide: Peripherals 4.1 About the Cortex-M3 peripherals The address map of the Private peripheral bus (PPB) is: Table 615. Core peripheral register regions Address Core peripheral Description...
Page 730: Nested Vectored Interrupt Controller
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 4.2 Nested Vectored Interrupt Controller This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: • Up to 112 interrupts. The number of interrupts implemented is device dependent.
Page 731: Interrupt Set-Enable Registers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. For more information see the description of the NVIC_SetPriority function in Section 34–4.2.10.1 “NVIC programming hints”. Table 34–617...
Page 732: Interrupt Set-Pending Registers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 619. ICER bit assignments Bits Name Function [31:0] CLRENA Interrupt clear-enable bits. Write: 0 = no effect 1 = disable interrupt. Read: 0 = interrupt disabled 1 = interrupt enabled.
Page 733: Interrupt Active Bit Registers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 621. ICPR bit assignments Bits Name Function [31:0] CLRPEND Interrupt clear-pending bits. Write: 0 = no effect 1 = removes pending state an interrupt. Read: 0 = interrupt is not pending 1 = interrupt is pending.
Page 734: Software Trigger Interrupt Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 623. IPR bit assignments Bits Name Function [31:24] Priority, byte offset 3 Each priority field holds a priority value, 0-31. The lower the value, the greater the priority of the corresponding interrupt.
Page 735: Nvic Design Hints And Tips
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide When the processor enters the ISR, it automatically removes the pending state from the interrupt, see Section 34–4.2.9.1. For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again.
Page 736 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 4.2.10.1 NVIC programming hints Software uses the CPSIE I and CPSID I instructions to enable and disable interrupts. The CMSIS provides the following intrinsic functions for these instructions: void __disable_irq(void) // Disable Interrupts...
Page 737: System Control Block
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 4.3 System control block The System control block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. The system control block registers are: Table 626.
Page 738: Cpuid Base Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 627. ACTLR bit assignments Bits Name Function [31:3] Reserved DISFOLD When set to 1, disables IT folding. see Section 34–4.3.2.1 for more information. DISDEFWBUF When set to 1, disables write buffer use during default memory map accesses.
Page 739 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide – whether there are preempted active exceptions – the exception number of the highest priority pending exception – whether any interrupts are pending. See the register summary in Table 34–626, and the Type descriptions in Table 34–629, for...
Page 740: Vector Table Offset Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 629. ICSR bit assignments Bits Name Type Function [25] PENDSTCLR SysTick exception clear-pending bit. Write: 0 = no effect 1 = removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown.
Page 741: Memory System Ordering Of Memory Accesses
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 630. VTOR bit assignments Bits Name Function [31:30] Reserved. [29:8] TBLOFF Vector table base offset field. It contains bits[29:8] of the offset of the table base from the bottom of the memory map.
Page 742: System Control Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 631. AIRCR bit assignments Bits Name Type Function SYSRESETREQ System reset request: 0 = no system reset request 1 = asserts a signal to the outer system that requests a reset.
Page 743: Configuration And Control Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 633. SCR bit assignments Bits Name Function [31:5] Reserved. SEVONPEND Send Event on Pending bit: 0 = only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 1 = enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
Page 744: System Handler Priority Registers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 634. CCR bit assignments Bits Name Function [31:10] Reserved. STKALIGN Indicates stack alignment on exception entry: 0 = 4-byte aligned 1 = 8-byte aligned. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment.
Page 745: System Handler Control And State Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 635. System fault handler priority fields Handler Field Register description Memory management fault PRI_4 Table 34–636 Bus fault PRI_5 Usage fault PRI_6 SVCall PRI_11 Table 34–637 PendSV PRI_14 Table 34–638...
Page 746 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 639. SHCSR bit assignments Bits Name Function [31:19] Reserved [18] USGFAULTENA Usage fault enable bit, set to 1 to enable [17] BUSFAULTENA Bus fault enable bit, set to 1 to enable...
Page 747: Configurable Fault Status Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 4.3.11 Configurable Fault Status Register The CFSR indicates the cause of a memory management fault, bus fault, or usage fault. See the register summary in Table 34–626 for its attributes. The bit assignments are: The following subsections describe the subregisters that make up the CFSR: •...
Page 748 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 640. MMFSR bit assignments Bits Name Function MUNSTKERR Memory manager fault on unstacking for a return from exception: 0 = no unstacking fault 1 = unstack for an exception return has caused one or more access violations.
Page 749 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 641. BFSR bit assignments Bits Name Function STKERR Bus fault on stacking for exception entry: 0 = no stacking fault 1 = stacking for an exception entry has caused one or more bus faults.
Page 750 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 642. UFSR bit assignments Bits Name Function [15:10] Reserved. DIVBYZERO Divide by zero usage fault: 0 = no divide by zero fault, or divide by zero trapping not enabled 1 = the processor has executed an SDIV or UDIV instruction with a divisor of 0.
Page 751: Hard Fault Status Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 4.3.12 Hard Fault Status Register The HFSR gives information about events that activate the hard fault handler. See the register summary in Table 34–626 for its attributes. This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0.
Page 752: System Control Block Design Hints And Tips
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 645. BFAR bit assignments Bits Name Function [31:0] ADDRESS When the BFARVALID bit of the BFSR is set to 1, this field holds the address of the location that generated the bus fault When an unaligned access faults the address in the BFAR is the one requested by the instruction, even if it is not the address of the fault.
Page 753: System Timer, Systick
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 4.4 System timer, SysTick The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the LOAD register on the next clock edge, then counts down on subsequent clocks.
Page 754: Systick Reload Value Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 4.4.2 SysTick Reload Value Register The LOAD register specifies the start value to load into the VAL register. See the register summary in Table 34–646 for its attributes. The bit assignments are shown in Table 34–648.
Page 755: Systick Design Hints And Tips
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 650. CALIB register bit assignments Bits Name Function [30] SKEW Indicates whether the value of TENMS is precise. This can affect the suitability of SysTick as a software real time clock. This value is factory...
Page 756: Memory Protection Unit
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 4.5 Memory protection unit This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: •...
Page 757: Mpu Type Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 651. Memory attributes summary Memory type Shareability Other attributes Description Non-shared Memory-mapped peripherals that only a single processor uses. Normal Shared Non-cacheable Normal memory that is shared Write-through between several processors.
Page 758: Mpu Control Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 653. TYPE register bit assignments Bits Name Function [15:8] DREGION Indicates the number of supported MPU data regions: 0x08 = Eight MPU regions. [7:0] Reserved. SEPARATE Indicates support for unified or separate instruction and date memory maps: 0 = unified.
Page 759: Mpu Region Number Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide • For privileged accesses, the default memory map is as described in Section 35–1.2 “Memory model”. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map.
Page 760: Mpu Region Attribute And Size Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 656. RBAR bit assignments [31:N] ADDR Region base address field. The value of N depends on the region size. For more information see Section 34–4.5.4.1. [(N-1):5 Reserved. VALID MPU Region Number valid bit:...
Page 761 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 657. RASR bit assignments Bits Name Function [31:29] Reserved. [28] Instruction access disable bit: 0 = instruction fetches enabled 1 = instruction fetches disabled. [27] Reserved. [26:24] Access permission field, see Table 34–661.
Page 762: Mpu Access Permission Attributes
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 4.5.6 MPU access permission attributes This section describes the MPU access permission attributes. The access permission bits, TEX, C, B, S, AP, and XN, of the RASR, control access to the corresponding memory region.
Page 763: Mpu Mismatch
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Table 661. AP encoding AP[2:0] Privileged Unprivileged Description permissions permissions No access No access All accesses generate a permission fault No access Access from privileged software only Writes by unprivileged software generate a...
Page 764 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ;...
Page 765 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Use an STM instruction to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ;...
Page 766: Mpu Design Hints And Tips
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 4.5.9 MPU design hints and tips To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers: •...
Page 767: Arm Cortex-M3 User Guide: Glossary
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide 5. ARM Cortex-M3 User Guide: Glossary Abort — A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory.
Page 768 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Condition field — A four-bit field in an instruction that specifies a condition under which the instruction can execute. Context — The environment that each process operates in for a multitasking operating system.
Page 769 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Index register — In some load and store instruction descriptions, the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to memory.
Page 770 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 User Guide Should Be Zero or Preserved (SBZP) — Write as 0, or all 0s for bit fields, by software, or preserved by writing the same value back that has been previously read from the same field on the same processor.
Page 771 UM10360 Chapter 35: LPC17xx Supplementary information Rev. 00.06 — 5 June 2009 User manual 1. Abbreviations Table 663. Abbreviations Acronym Description Analog-to-Digital Converter Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection Controller Area Network Digital-to-Analog Converter Debug Communication Channel Direct Memory Access Digital Signal Processing...
Page 772 Trademarks Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without Notice: All referenced brands, product names, service names and trademarks limitation specifications and product descriptions, at any time and without are the property of their respective owners.
Page 773 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Notes continued >> UM10360_0 © NXP B.V. 2009. All rights reserved. User manual Rev. 00.06 — 5 June 2009 773 of 808...
Page 774 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 3. Tables Table 1. Ordering information .....6 0x400F C0A4) bit description....43 Table 2.
Page 775 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Table 61. Pin function select register 4 (PINSEL4 - address Table 84. Fast GPIO port output Set byte and half-word 0x4002 C010) bit description ....81 accessible register description.
Page 776 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 0x5000 0000) bit description ... . .120 (RxConsumeIndex - address 0x5000 0118) bit Table 108.MAC Configuration register 2 (MAC2 - address description ......131 0x5000 0004) bit description .
Page 777 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Table 156.Receive Status HashCRC Word ...144 allocation ......197 Table 157.Receive status information word.
Page 778 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Table 204.USB UDCA Head register (USBUDCAH - address Table 230.USB (OHCI) related acronyms and abbreviations 0x5000 C280) bit description ... . .207 used in this chapter .
Page 779 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information U3IER - 0x4009 C004 when DLAB = 0) bit address 0x4001 0004 when DLAB = 0) bit description ......274 description .
Page 780 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Table 299.CAN Global Status Register (CAN1GSR - address address 0x4004 0000) bit description ..347 0x4004 4008, CAN2GSR - address 0x4004 8008) Table 318.Central Receive Status Register (CANRxSR - bit description .
Page 781: I2C0Adr[0, 1, 2, 3]- 0X4001 C0[0C, 20, 24, 28]; I
UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Table 345:SPI Test Control Register (SPTCR - address I2C1CONCLR - 0x4005 C018; I 0x4002 0010) bit description ... . .385 I2C2CONCLR - 0x400A 0018) bit description 416 Table 346:SPI Test Status Register (SPTSR - address Table 366.I...
Page 782 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Table 384.Pin descriptions ..... . .447 0x4009 0028, 0x4009 4028) bit description . . 470 Table 385.I2S register map .
Page 783 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Table 441.MCPWM Capture Control set address ....518 Table 462.Encoder state transitions (MCCAPCON_SET - 0x400B 8010) bit Table 463.Encoder direction ..... 519 description .
Page 784 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 0x4002 4000) bit description ... . .536 0x4003 4034) bit description ... . . 555 Table 491.Clock Control Register (CCR - address...
Page 785 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information (DMACCxConfig - 0x5000 41x0) ..579 Table 588.Memory access instructions....629 Table 547.Transfer type bits .
Page 786 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Table 635.System fault handler priority fields ..745 Table 636.SHPR1 register bit assignments...745 Table 637.SHPR2 register bit assignments...745 Table 638.SHPR3 register bit assignments.
Page 787 Fig 1. LPC1768 simplified block diagram... . .7 Fig 42. Clocking and power control....267 Fig 2.
Page 788 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Single and b) Continuous Transfer) ..390 reference clock ......460 Fig 76.
Page 789: Table Of Contents
UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 5. Contents Chapter 1: LPC17xx Introductory information Introduction ......3 Architectural overview .
Page 790 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information PLL1 Configuration register (PLL1CFG - Power control ......50 0x400F C0A4) .
Page 791 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 5.10 Pin Mode select register 1 (PINMODE1 - 5.16 Open Drain Pin Mode select register 0 0x4002 C044) ......83 (PINMODE_OD0 - 0x4002 C068) .
Page 792 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 11.2 MAC Configuration Register 2 (MAC2 - 12.10 Transmit Number of Descriptors Register 0x5000 0004) ......121 (TxDescriptorNumber - 0x5000 0124) .
Page 793 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 17.5 Transmission retry ....164 17.16 Statistics counters ....175 17.6...
Page 794 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 10.6.1 USB Command Code register (USBCmdCode - 12.4 Read Current Frame Number (Command: 0xF5, 0x5000 C210) ..... . . 204 Data: read 1 or 2 bytes) .
Page 795 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 15.5.3 Transferring the data ....232 15.7 Auto Length Transfer Extraction (ATLE) mode 15.5.4 Optimizing descriptor fetch ....232 operation .
Page 796 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Chapter 14: LPC17xx UART0/2/3 Basic configuration ....270 UARTn Line Control Register (U0LCR - 0x4000 C00C, U2LCR - 0x4009 800C, U3LCR - Features .
Page 797 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 4.16 UART1 Fractional Divider Register (U1FDR - 4.19 UART1 RS-485 Address Match register 0x4001 0028) ......308 (U1RS485ADRMATCH - 0x4001 0050) .
Page 798 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 11.4 FullCAN mode ..... . . 349 16.2.1 FullCAN message interrupt enable bit ..362 16.2.2...
Page 799 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Chapter 18: LPC17xx SSP0/1 interface Basic configuration ....387 SSPn Control Register 0 (SSP0CR0 - 0x4008 8000, SSP1CR0 - 0x4003 0000).
Page 800 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information C Data buffer register (I2DATA_BUFFER: I 9.7.1 Initialization ......437 I2CDATA_BUFFER - 0x4001 C02C;...
Page 801 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Receive FIFO register (I2SRXFIFO - 5.10 Receive Clock Rate register (I2SRXRATE - 0x400A 800C)......451 0x400A 8024).
Page 802 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information System Timer Reload value register (STRELOAD System Timer Calibration value register - 0xE000 E014)..... . . 479 (STCALIB - 0xE000 E01C) .
Page 803 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information MCPWM Communication Pattern register (MCCP Pulse-width modulation ....509 - 0x400B 8040) ..... . . 508 Shadow registers and simultaneous updates 512 7.10...
Page 804 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 6.2.4 Alarm Mask Register (AMR - 0x4002 4010) . 537 Time Counter Group ....539 6.2.5...
Page 805 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information Features ......561 5.13 DMA Configuration register (DMACConfig - 0x5000 4030) .
Page 806 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 3.2.7 RAM used by ISP command handler ..591 7.10 Blank check sector(s) <sector number> <end 3.2.8 RAM used by IAP command handler ..591 sector number>...
Page 807 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 2.6.2 UMULL, UMLAL, SMULL, and SMLAL..664 3.3.3 Exception handlers ....717 2.6.3...
Page 808 UM10360 NXP Semiconductors Chapter 35: LPC17xx Supplementary information 4.4.1 SysTick Control and Status Register ..753 4.5.3 MPU Region Number Register ..759 4.4.2 SysTick Reload Value Register... 754 4.5.4...

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