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9.2.2.1
Master Priority Register (XBAR_MPRn)
The Master Priority Register (MPR) resides in each slave port and sets the priority of each master port on
a per slave port basis, e.g., MPR0 sets priority for each master port for slave port 0.
MPR0: Address: XBAR_Base (0xFFF0_4000) + 0x0000
MPR1: Address: XBAR_Base (0xFFF0_4000) + 0x0100
MPR2: Address: XBAR_Base (0xFFF0_4000) + 0x0200
MPR7: Address: XBAR_Base (0xFFF0_4000) + 0x0700
0
1
R
0
MSTR7
W
Reset
0
1
16
17
R
0
0
W
Reset
0
0
= not implemented
Table 9-3. XBAR Master Priority Register Field Descriptions
Field
0
Reserved
This bit is reserved for future expansion. It is read as zero and should be written with zero for upward
compatibility.
1:3
Master 7 Priority
MSTR7
These bits set the arbitration priority for master port 7 (EBI) on the associated slave port.
These bits are initialized by hardware reset. The reset value is 111.
000: This master has the highest priority when accessing the slave port.
...
111: This master has the lowest priority when accessing the slave port.
4
Reserved
This bit is reserved for future expansion. It is read as zero and should be written with zero for upward
compatibility.
5:7
Master 6 Priority
MSTR6
These bits set the arbitration priority for master port 6 (FlexRay) on the associated slave port.
These bits are initialized by hardware reset. The reset value is 110.
000: This master has the highest priority when accessing the slave port.
...
111: This master has the lowest priority when accessing the slave port.
Freescale Semiconductor
2
3
4
5
6
0
MSTR6
0
0
0
0
1
18
19
20
21
22
0
0
0
0
0
0
0
0
0
0
Figure 9-3. Master Priority Register (XBAR_MPRn)
MPC5644A Microcontroller Reference Manual, Rev. 6
Multi-Layer AHB Crossbar Switch (XBAR)
7
8
9
10
11
0
0
0
0
1
0
0
0
0
23
24
25
26
27
0
0
MSTR1
0
0
0
0
1
Description
Access: Supervisor
12
13
14
15
0
MSTR4
0
0
1
0
28
29
30
31
0
MSTR0
0
0
0
0
197
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