NXP Semiconductors MPC5644A Reference Manual page 919

operation. V Flag is calculated using ALU adder output (that is, it is not affected by 1-bit shift/rotate
operations).
Operation size
8 bits
16 bits
24 bits
1
For V-flag definition on the absolute operation, see
2
BS is taken after any inversion by the BINV field, but not added to the carry bit (CIN field)
Zero Flag (Z)
Zero flag equal to 1 indicates that the result from the ALU, limited to the operation size, is zero, regardless
of the operation performed, whether the result is written, or where it is written. It depends on the operation
size, as shown in Table 24-62.
Operation size
24.5.8.2.2 ALU ADD Operation with and without shifting
ADD operation is selected by ALUOP or ALUOPI fields and when none of them is available in a
1
microinstruction format
SHF, ALUOP or ALUOPI fields. See
describes how CIN and BINV fields change ADD operation behavior.
ALU adder output can be 1-bit shifted or 1-bit rotated right as follows:
Shift right:
if BINV==1
result[23:0] = adder_output[24:1]
else
1. ALU operations only occur on formats where a destination field is found (T2ABD/T2D).
Freescale Semiconductor
Table 24-61. Overflow flag on addition
(AS[7] & BS[7] & !alu_adder_output[7]) | (!AS[7] & !BS[7] & alu_adder_output[7])
(AS[15] & BS[15] &!alu_adder_output[15]) |
(!AS[15] & !BS[15] & alu_adder_output[15])
(AS[23] & BS[23] &!alu_adder_output[23]) |
(!AS[23] & !BS[23] & alu_adder_output[23])
Table 24-62. Zero Flag – Z
8 bits
16 bits
24 bits Z = (result[23:0] == 0x000000)
. Optionally, result can be shifted or rotated right by 1 bit, which is selected by
Section 24.5.9, Microinstruction
Table 24-63. Types of ADD operations
BINV CIN
1 1
1 0
0 0
0 1
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Time Processing Unit (eTPU2)
1
– V
2
Value
Section 24.5.8.2.8, Absolute value
Value
Z = (result[7:0] == 0x00)
Z = (result[15:0] == 0x0000)
set, for more details.
Operation (adder output)
AS + BS
AS + BS + 1
AS - BS
AS - BS - 1
operation.
Table 24-63
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