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Address: REACM_BASE (0xC3FC_7000) + (from 0x0380 to 0x0388)
0
1
2
R
0
0
0
W
Reset
0
0
0
16
17
18
R
W
Reset
0
0
0
Figure 23-13. REACM Hold-off Timer Bank Registers (REACM_HOTBK)
Field
0–19
Reserved, should be cleared.
20–31
Hold-off Timer Value
HOLD_OFF[11:0]
The HOLD_OFFT[11:0] value is one element of the Hold-off Timer Register Bank. Up to three
values can be stored within the Hold-off Timer Bank.
Note: When using the hold-off timer for sequence advance, the counted time (considering
23.3.12 REACM Threshold Bank Register (REACM_THBK)
The REACM Threshold Bank Register (REACM_THBK) holds the value to be used for comparison
against results received from the ADC. Based on that comparison the reaction channel decides the Channel
output value to be either HOD or LOD.
Address: REACM_BASE (0xC3FC_7000) + (from 0x0400 to 0x045C)
0
1
2
R
0
0
0
W
Reset
0
0
0
16
17
18
R
W
Reset
0
0
0
Figure 23-14. REACM Threshold Bank Register (REACM_THBK)
Freescale Semiconductor
3
4
5
6
0
0
0
0
0
0
0
0
19
20
21
22
0
0
0
0
Table 23-15. REACM_HOTBK field descriptions
prescaler) must be greater than 64 clock cycles.
3
4
5
6
0
0
0
0
0
0
0
0
19
20
21
22
THRESHOLD_VALUE[15:0]
0
0
0
0
MPC5644A Microcontroller Reference Manual, Rev. 6
7
8
9
10
11
0
0
0
0
0
0
0
0
23
24
25
26
27
HOLD_OFF[11:0]
0
0
0
0
Description
7
8
9
10
11
0
0
0
0
0
0
0
0
23
24
25
26
27
0
0
0
0
Reaction Module (REACM)
Access: User read/write
12
13
14
15
0
0
0
0
0
0
0
0
0
0
28
29
30
31
0
0
0
0
0
Access: User read/write
12
13
14
15
0
0
0
0
0
0
0
0
0
0
28
29
30
31
0
0
0
0
0
711
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