Table of Contents
Advertisement
Address
EBI_BASE+0x8
EBI_BASE+0xC
EBI_BASE+0x10
EBI_BASE+0x14
EBI_BASE+0x18
EBI_BASE+0x1C
EBI_BASE+0x20
EBI_BASE+0x24
EBI_BASE+0x28
EBI_BASE+0x2C
EBI_BASE+0x30 –
EBI_BASE+0x3C
EBI_BASE+0x40
EBI_BASE+0x44
EBI_BASE+0x48
EBI_BASE+0x4C
EBI_BASE+0x50
EBI_BASE+0x54
EBI_BASE+0x58
EBI_BASE+0x5C
14.4.1
Register Descriptions
Other than the exceptions noted below, EBI registers must not be written
while a transaction to the EBI (from internal master) is in progress (or within
2 CLKOUT cycles after a transaction has just completed, to allow internal
state machines to go IDLE). In those cases, the behavior is undefined.
Exceptions that can be written while an EBI transaction is in progress:
- All bits in EBI_TESR
See
Section 14.6.1, Booting from external memory
information.
Freescale Semiconductor
Table 14-4. EBI Address Map (continued)
EBI Transfer Error Status Register (EBI_TESR)
EBI Bus Monitor Control Register (EBI_BMCR)
EBI Base Register Bank 0 (EBI_BR0)
EBI Option Register Bank 0 (EBI_OR0)
EBI Base Register Bank 1 (EBI_BR1)
EBI Option Register Bank 1 (EBI_OR1)
EBI Base Register Bank 2 (EBI_BR2)
EBI Option Register Bank 2 (EBI_OR2)
EBI Base Register Bank 3 (EBI_BR3)
EBI Option Register Bank 3 (EBI_OR3)
EBI Calibration Base Register Bank 0 (EBI_CAL_BR0)
EBI Calibration Option Register Bank 0 (EBI_CAL_OR0)
EBI Calibration Base Register Bank 1 (EBI_CAL_BR1)
EBI Calibration Option Register Bank 1 (EBI_CAL_OR1)
EBI Calibration Base Register Bank 2 (EBI_CAL_BR2)
EBI Calibration Option Register Bank 2 (EBI_CAL_OR2)
EBI Calibration Base Register Bank 3 (EBI_CAL_BR3)
EBI Calibration Option Register Bank 3 (EBI_CAL_OR3)
NOTE
MPC5644A Microcontroller Reference Manual, Rev. 6
External Bus Interface (EBI)
Use
Reserved
for related application
285
Advertisement
Table of Contents
