NXP Semiconductors LPC2917 Preliminary Data Sheet

1. Introduction

1.1 About this document

This document lists detailed information about the LPC2917/19 device. It focuses on
factual information like pinning, characteristics etc. Short descriptions are used to outline
the concept of the features and functions. More details and background on developing
applications for this device are given in the LPC2917/19 User Manual (see
explicit references are made to the User Manual.

1.2 Intended audience

This document is written for engineers evaluating and/or developing systems, hard-
and/or software for the LPC2917/19. Some basic knowledge of ARM processors and
architecture and ARM968E-S in particular is assumed (see

2. General description

2.1 Architectural overview

The LPC2917/19 consists of:
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The LPC2917/19 configures the ARM968E-S processor in little-endian byte order. All
peripherals run at their own clock frequency to optimize the total system power
consumption. The AHB2VPB bridge used in the subsystems contains a write-ahead buffer
one transaction deep. This implies that when the ARM968E-S issues a buffered write
action to a register located on the VPB side of the bridge, it continues even though the
actual write may not yet have taken place. Completion of a second write to the same
subsystem will not be executed until the first write is finished.
LPC2917/19
ARM9 microcontroller with CAN and LIN
Rev. 1.01 — 15 November 2007
An ARM968E-S processor with real-time emulation support
An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the
on-chip memory controllers
Two DTL buses (a universal NXP interface) for interfacing to the interrupt controller
and the Power, Clock and Reset Control cluster (also called subsystem)
Three VLSI Peripheral Buses (VPB - a compatible superset of ARM's AMBA
advanced peripheral bus) for connection to on-chip peripherals clustered in
subsystems.
Preliminary data sheet
Ref. 1). No
Ref. 2).