Features - NXP Semiconductors MPC5644A Reference Manual

System
bus
(XBAR)
Note: V is the only externally visible power supply that is necessary for the programming and erasing
PP
of the flash array (see
12.1.2

Features

The flash memory module has these major features:
• Support for a 64-bit data bus for instruction fetch
• Support for a 32-bit data bus for CPU loads and DMA access. Byte, halfword, word and
doubleword reads are supported. Only aligned word and doubleword writes are supported.
• Configurable read buffering and line prefetch support. Device flash has 2 sets of 4 line read
buffers—1 set for the 128-bit wide low- and medium-address space and 1 set for the 256-bit wide
high address space.
Freescale Semiconductor
V
SS
Flash_A memory module
Flash memory
interface
Flash core
Flash bus
interface
unit
(FBIU)
Flash memory
interface
Flash core
V
SS
Section 12.2, External signal
Figure 12-2. Flash system block diagram
MPC5644A Microcontroller Reference Manual, Rev. 6
V V
FLASH_A DD
(MI)
Control/status
registers
Flash_B memory module
(MI)
Control/status
registers
V V
FLASH_B DD
description).
Flash memory
Slave
bus
Slave
bus
219