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Enhanced Time Processing Unit (eTPU2)
•
Match channel's internal registers MatchA or MatchB;
•
Capture time base value to channel's internal registers, CaptureA and/or CaptureB, when a match
recognition or an Input transition detection occurs. For more information on channel events refer
to
Section 24.5.5, Enhanced
The TCR1 and TCR2 counters are accessible by the microcode for read and write operations. Its current
value is used for getting the current time, and the captured values are used for channel relative time
calculations of future events. When they are written at the same time they are incremented from any clock
source, the written value prevails.
TCR1 with ETPU_TBCR[TCR1CS] = 0 and TCR2 values are updated in T2 and read in T4 (see
Section 24.7.1, Microcycle and I/O
updated on both T2 and T4, when ETPU_TBCR[TCR1CS] = 1. Both TCR1 and TCR2 values can be
imported from or exported to the STAC bus. When their values are imported (STAC Clients), these
registers are written from the STAC bus and can only be read by microcode. For information on STAC
bus protocol and definition of STAC modules refer to IPI STAC and
The TCR2 counters between the two engines are out of phase by 1 system clock, even when Time Bases
are shared between them through STAC. It also applies to TCR1 counters if ETPU_TBCR[TCR1CS] = 0,
but they can be in phase otherwise.
24.5.6.1
Timer Count Register 1 – TCR1
TCR1 can be used in the following modes:
•
Internally Clocked Mode
•
Externally Clocked Mode
•
STAC Bus Client Mode
The host program can read TCR1 time base through the ETPU_TB1R (see
– eTPU Time Base 1 (TCR1) Visibility
The TCR1 bus runs through all the local engine channels. In channels which select TCR1 as MatchA
and/or MatchB source, when its value is greater or equal to the programmed match value, a Match A and/or
Match B event occurs on that channel. A recognized match event sets its related Match Recognition Latch
1 or 2, and according to the Predefined Channel Modes (PDCM) it may generate a channel service request.
For details on eTPU channels refer to
24.5.6.1.1
Externally clocked mode
TCR1 can be driven externally by the TCRCLK input, after the digital filter. The TCR1 clock source is
configured by the TCR1CTL bit, as shown in
selection, please refer to
886
Channels.
timing). TCR1 can also work at full-speed system clock, and so be
Register).
Section 24.5.5, Enhanced
Figure
Section 24.4.3.1, ETPU_TBCR – eTPU Time Base Configuration
MPC5644A Microcontroller Reference Manual, Rev. 6
Section 24.5.6.3, STAC
Section 24.4.3.2, ETPU_TB1R
Channels.
24-49. For more information on clock source
Interface.
Register.
Freescale Semiconductor
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