NXP Semiconductors MPC5644A Reference Manual page 677

MODE [6] = 1
internal counter
due to B1 match cycle n-1
Output pin
FLAG set event
FLAG pin/register
FLAG clear
A1/B1 load signal
A1 value
A2 value
B1 value
EDPOL = 0
B2 value
Prescaler ratio = 4
Figure 22-32. OPWFMB A1 and B1 registers update and flags
Figure 22-33 describes the operation of the Output Disable feature in OPWFMB mode. Differently from
the OPWFM mode, the output disable forces the channel output flip-flop to EDPOL bit value. This
functionality targets applications that use active high signals and a high to low transition at A1 match. In
this case EDPOL should be set to 0. Note that both the channel and global prescalers are set to 0x0 (each
divide ratio is one), meaning that the channel internal counter transitions at every system clock cycle.
Freescale Semiconductor
cycle n
write to A2
Match A1 Match B1
0x8
0x6
0x4
0x2
0x1
1
0x2
1
0x2 0x4
0x8
0x8
MPC5644A Microcontroller Reference Manual, Rev. 6
Configurable Enhanced Modular IO Subsystem (eMIOS200)
cycle n+1
write to A2
Match A1
Match B1
write to B2
0x4 0x6
0x6
0x6
0x6
cycle n+2
Match B1
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