NXP Semiconductors MPC5644A Reference Manual page 917

24.5.8.1.8 CHAN Register
CHAN is a 5-bit register that can be used as source and destination in arithmetic operations. The contents
of CHAN register affects the execution of many channel-related microinstructions, because its number
indicates the selected channel. CHAN register must not be used to store temporary values in arithmetic
operations. For more details, refer to
24.5.8.1.9 Counter Registers: TCR1, TCR2, TPR and TRR
All these registers are 24-bit wide except TPR, which is a 16-bit register. They can be read or written in
arithmetic/logical operations, and have special-purpose uses for time base and angle mode operations. For
more information about those registers see
angle counter.
24.5.8.1.10 General Purpose Registers: A, B, C and D
A, B, C and D are 24-bit general purpose registers, which can be used to store intermediate values and do
not have other specific uses with any eTPU feature.
24.5.8.2 ALU and Post-ALU Shifter
The ALU executes 24-bit arithmetic and logical operations. ALU's output goes directly to a 1-bit shifter,
called post-ALU shifter, so it is possible, for example, to add and shift using only one microinstruction.
In some microinstruction formats, it is not possible to specify the operation executed by ALU. In these
cases ALU will always perform addition.
In formats which have the field ALUOP for ALU operation selection, all of them can be performed,
including add/subtract using C (carry) flag as ALU's carry-in, bitwise AND/OR/NOT/XOR, and
shift/rotate of 2, 4, 8 and 16 bits. See
Subtraction, inversion, increment and decrement can be performed by combinations of source inversion
and setting ALU's carry-in to 1.
ALU always performs 24-bit operations on its inputs, called A-source and B-source, and outputs a 24-bit
result. 8-, and 16-bit inputs are zero padded to 24 bits. Likewise, ALU 24-bit output is always truncated to
the destination register size.
24.5.8.2.1 ALU Flags
Four flags—Carry, Negative, Overflow, Zero—described below, are related to ALU and post-ALU shift
operations. Operation size and shifting affect flags generation logic. Operation size determines the result
boundary to be used for flags generation. Operation size is determined by size of sources and destination
(see Section 24.5.9.2.3, Flags sampling
Section 24.5.9.2.3, Flags sampling
Conditional/Unconditional
Conditional ALU/MDU operation
Freescale Semiconductor
Section , Channel Selection Register –
Section 24.5.6, Time
Section 24.5.9.2.10, ALU/MDU Operation
control). For more information about flag generation, see
control. ALU flags can be used as branch condition (see
branch) or conditional ALU/MDU operation (see
execution).
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Time Processing Unit (eTPU2)
CHAN.
Bases, and Section 24.5.7, EAC – eTPU
Selection.
Section 24.5.9.2.7,
Section ,
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