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- Page 1 K30 Sub-Family Reference Manual Supports: MK30DX128VLL7, MK30DX256VLL7, MK30DX64VMC7, MK30DX128VMC7, MK30DX256VMC7 Document Number: K30P100M72SF1RM Rev. 1.1, Dec 2012...
- Page 2 K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Page 3: Table Of Contents
Contents Section number Title Page Chapter 1 About This Document Overview..................................49 1.1.1 Purpose.................................49 1.1.2 Audience..............................49 Conventions..................................49 1.2.1 Numbering systems............................49 1.2.2 Typographic notation...........................50 1.2.3 Special terms..............................50 Chapter 2 Introduction Overview..................................51 Module Functional Categories............................51 2.2.1 ARM Cortex-M4 Core Modules........................52 2.2.2 System Modules............................53 2.2.3 Memories and Memory Interfaces.......................54 2.2.4... - Page 4 Section number Title Page Core modules................................59 3.2.1 ARM Cortex-M4 Core Configuration......................59 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration..............61 3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration............67 3.2.4 JTAG Controller Configuration........................69 System modules................................69 3.3.1 SIM Configuration............................69 3.3.2 System Mode Controller (SMC) Configuration...................70 3.3.3 PMC Configuration............................71 3.3.4...
- Page 5 Section number Title Page 3.5.5 System Register File Configuration......................93 3.5.6 VBAT Register File Configuration......................94 3.5.7 EzPort Configuration...........................94 Security..................................96 3.6.1 CRC Configuration............................96 K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
- Page 6 Section number Title Page Analog...................................96 3.7.1 16-bit SAR ADC with PGA Configuration....................96 3.7.2 CMP Configuration............................106 3.7.3 12-bit DAC Configuration...........................108 3.7.4 VREF Configuration............................109 Timers...................................110 3.8.1 PDB Configuration............................110 3.8.2 FlexTimer Configuration..........................113 3.8.3 PIT Configuration............................117 3.8.4 Low-power timer configuration........................118 3.8.5 CMT Configuration............................120 3.8.6 RTC configuration............................121 Communication interfaces............................122 3.9.1...
- Page 7 Section number Title Page SRAM memory map..............................144 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................145 4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map..................145 4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map..................149 Private Peripheral Bus (PPB) memory map........................152 Chapter 5 Clock Distribution Introduction...................................155 Programming model..............................155 High-Level device clocking diagram..........................155...
- Page 8 Section number Title Page Reset....................................168 6.2.1 Power-on reset (POR)..........................168 6.2.2 System reset sources............................168 6.2.3 MCU Resets..............................172 6.2.4 Reset Pin ..............................174 6.2.5 Debug resets..............................174 Boot....................................175 6.3.1 Boot sources..............................175 6.3.2 Boot options..............................175 6.3.3 FOPT boot options............................176 6.3.4 Boot sequence..............................177 Chapter 7 Power Management Introduction...................................179 Power modes.................................179 Entering and exiting power modes..........................181...
- Page 9 Section number Title Page Chapter 9 Debug Introduction...................................189 9.1.1 References..............................191 The Debug Port................................191 9.2.1 JTAG-to-SWD change sequence.........................192 9.2.2 JTAG-to-cJTAG change sequence.......................192 Debug Port Pin Descriptions............................193 System TAP connection..............................193 9.4.1 IR Codes...............................193 JTAG status and control registers..........................194 9.5.1 MDM-AP Control Register..........................195 9.5.2 MDM-AP Status Register..........................197 Debug Resets................................198...
- Page 10 Section number Title Page 10.2.4 Signal multiplexing constraints........................204 10.3 Pinout....................................205 10.3.1 K30 Signal Multiplexing and Pin Assignments...................205 10.3.2 K30 Pinouts..............................210 10.4 Module Signal Description Tables..........................212 10.4.1 Core Modules...............................212 10.4.2 System Modules............................213 10.4.3 Clock Modules.............................214 10.4.4 Memories and Memory Interfaces.......................214 10.4.5 Analog................................215 10.4.6 Timer Modules.............................216...
- Page 11 Section number Title Page 12.2.4 System Options Register 5 (SIM_SOPT5)....................247 12.2.5 System Options Register 7 (SIM_SOPT7)....................248 12.2.6 System Device Identification Register (SIM_SDID)...................250 12.2.7 System Clock Gating Control Register 1 (SIM_SCGC1)................251 12.2.8 System Clock Gating Control Register 2 (SIM_SCGC2)................252 12.2.9 System Clock Gating Control Register 3 (SIM_SCGC3)................253 12.2.10 System Clock Gating Control Register 4 (SIM_SCGC4)................255 12.2.11...
- Page 12 Section number Title Page Chapter 14 System Mode Controller 14.1 Introduction...................................279 14.2 Modes of operation...............................279 14.3 Memory map and register descriptions.........................281 14.3.1 Power Mode Protection register (SMC_PMPROT)..................281 14.3.2 Power Mode Control register (SMC_PMCTRL)..................283 14.3.3 VLLS Control register (SMC_VLLSCTRL)....................284 14.3.4 Power Mode Status register (SMC_PMSTAT)...................285 14.4 Functional description..............................286 14.4.1...
- Page 13 Section number Title Page Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.1 Introduction...................................307 16.1.1 Features................................307 16.1.2 Modes of operation............................308 16.1.3 Block diagram..............................309 16.2 LLWU signal descriptions............................310 16.3 Memory map/register definition...........................311 16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)....................312 16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)....................313 16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)....................314 16.3.4...
- Page 14 Section number Title Page 17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............330 17.2.3 Control Register (MCM_CR)........................331 Chapter 18 Crossbar Switch (AXBS) 18.1 Introduction...................................333 18.1.1 Features................................333 18.2 Memory Map / Register Definition..........................334 18.2.1 Priority Registers Slave (AXBS_PRSn)......................335 18.2.2 Control Register (AXBS_CRSn).........................338 18.2.3 Master General Purpose Control Register (AXBS_MGPCRn)..............340 18.3 Functional Description..............................340...
- Page 15 Section number Title Page 20.1.2 Features................................364 20.1.3 Modes of operation............................364 20.2 External signal description............................365 20.3 Memory map/register definition...........................365 20.3.1 Channel Configuration register (DMAMUX_CHCFGn)................366 20.4 Functional description..............................367 20.4.1 DMA channels with periodic triggering capability..................367 20.4.2 DMA channels with no triggering capability....................369 20.4.3 "Always enabled"...
- Page 16 Section number Title Page 21.3.10 Set START Bit Register (DMA_SSRT)......................404 21.3.11 Clear Error Register (DMA_CERR)......................405 21.3.12 Clear Interrupt Request Register (DMA_CINT)..................406 21.3.13 Interrupt Request Register (DMA_INT)......................406 21.3.14 Error Register (DMA_ERR)........................409 21.3.15 Hardware Request Status Register (DMA_HRS)..................411 21.3.16 Channel n Priority Register (DMA_DCHPRIn)..................414 21.3.17 TCD Source Address (DMA_TCDn_SADDR)...................415 21.3.18...
- Page 17 Section number Title Page 21.4.2 Error reporting and handling........................431 21.4.3 Channel preemption.............................433 21.4.4 Performance..............................433 21.5 Initialization/application information...........................438 21.5.1 eDMA initialization.............................438 21.5.2 Programming errors.............................440 21.5.3 Arbitration mode considerations........................440 21.5.4 Performing DMA transfers (examples)......................441 21.5.5 Monitoring transfer descriptor status......................445 21.5.6 Channel Linking............................446 21.5.7 Dynamic programming..........................448 Chapter 22...
- Page 18 Section number Title Page 22.4.6 EWM Interrupt.............................461 Chapter 23 Watchdog Timer (WDOG) 23.1 Introduction...................................463 23.2 Features..................................463 23.3 Functional overview..............................465 23.3.1 Unlocking and updating the watchdog......................466 23.3.2 Watchdog configuration time (WCT)......................467 23.3.3 Refreshing the watchdog..........................468 23.3.4 Windowed mode of operation........................468 23.3.5 Watchdog disabled mode of operation......................468 23.3.6 Low-power modes of operation........................469...
- Page 19 Section number Title Page 23.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................479 23.7.12 Watchdog Prescaler register (WDOG_PRESC)..................480 23.8 Watchdog operation with 8-bit access..........................480 23.8.1 General guideline............................480 23.8.2 Refresh and unlock operations with 8-bit access..................480 23.9 Restrictions on watchdog operation..........................481 Chapter 24 Multipurpose Clock Generator (MCG) 24.1 Introduction...................................485 24.1.1...
- Page 20 Section number Title Page 24.4.3 MCG Internal Reference Clocks........................507 24.4.4 External Reference Clock..........................507 24.4.5 MCG Fixed frequency clock ........................508 24.4.6 MCG PLL clock ............................508 24.4.7 MCG Auto TRIM (ATM)..........................509 24.5 Initialization / Application information........................510 24.5.1 MCG module initialization sequence......................510 24.5.2 Using a 32.768 kHz reference........................512 24.5.3 MCG mode switching..........................513...
- Page 21 Section number Title Page Chapter 26 RTC Oscillator 26.1 Introduction...................................535 26.1.1 Features and Modes.............................535 26.1.2 Block Diagram.............................535 26.2 RTC Signal Descriptions..............................536 26.2.1 EXTAL32 — Oscillator Input........................536 26.2.2 XTAL32 — Oscillator Output........................536 26.3 External Crystal Connections............................537 26.4 Memory Map/Register Descriptions..........................537 26.5 Functional Description..............................537 26.6 Reset Overview................................538...
- Page 22 Section number Title Page 27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL)................556 27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)................556 27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL)................557 27.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU)................557 27.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL)................558 27.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU)................558 27.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL)................559...
- Page 23 Section number Title Page 28.4.4 Flash Operation in Low-Power Modes......................590 28.4.5 Functional Modes of Operation........................590 28.4.6 Flash Reads and Ignored Writes........................590 28.4.7 Read While Write (RWW)...........................591 28.4.8 Flash Program and Erase..........................591 28.4.9 Flash Command Operations.........................591 28.4.10 Margin Read Commands..........................598 28.4.11 Flash Command Description........................599 28.4.12 Security................................620...
- Page 24 Section number Title Page 30.1.3 Modes of operation............................638 30.2 Memory map and register descriptions.........................638 30.2.1 CRC Data register (CRC_CRC)........................639 30.2.2 CRC Polynomial register (CRC_GPOLY)....................640 30.2.3 CRC Control register (CRC_CTRL)......................640 30.3 Functional description..............................641 30.3.1 CRC initialization/reinitialization........................641 30.3.2 CRC calculations............................642 30.3.3 Transpose feature............................643 30.3.4 CRC result complement..........................645 Chapter 31...
- Page 25 Section number Title Page 31.3.8 ADC Offset Correction Register (ADCx_OFS)...................665 31.3.9 ADC Plus-Side Gain Register (ADCx_PG)....................665 31.3.10 ADC Minus-Side Gain Register (ADCx_MG)....................666 31.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)............666 31.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............667 31.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............667 31.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)............668 31.3.15...
- Page 26 Section number Title Page 31.4.11 MCU Normal Stop mode operation......................690 31.4.12 MCU Low-Power Stop mode operation......................691 31.5 Initialization information..............................692 31.5.1 ADC module initialization example......................692 31.6 Application information..............................694 31.6.1 External pins and routing..........................694 31.6.2 Sources of error............................696 Chapter 32 Comparator (CMP) 32.1 Introduction...................................701 32.2...
- Page 27 Section number Title Page 32.11 Digital-to-analog converter block diagram........................726 32.12 DAC functional description............................726 32.12.1 Voltage reference source select........................726 32.13 DAC resets..................................727 32.14 DAC clocks...................................727 32.15 DAC interrupts................................727 Chapter 33 12-bit Digital-to-Analog Converter (DAC) 33.1 Introduction...................................729 33.2 Features..................................729 33.3 Block diagram................................729 33.4 Memory map/register definition...........................730 33.4.1...
- Page 28 Section number Title Page 34.1.4 VREF Signal Descriptions...........................741 34.2 Memory Map and Register Definition..........................742 34.2.1 VREF Trim Register (VREF_TRM)......................742 34.2.2 VREF Status and Control Register (VREF_SC)..................743 34.3 Functional Description..............................744 34.3.1 Voltage Reference Disabled, SC[VREFEN] = 0..................744 34.3.2 Voltage Reference Enabled, SC[VREFEN] = 1..................745 34.4 Initialization/Application Information..........................746 Chapter 35...
- Page 29 Section number Title Page 35.3.11 Pulse-Out n Enable Register (PDBx_POEN)....................760 35.3.12 Pulse-Out n Delay Register (PDBx_POnDLY)...................761 35.4 Functional description..............................761 35.4.1 PDB pre-trigger and trigger outputs......................761 35.4.2 PDB trigger input source selection......................763 35.4.3 DAC interval trigger outputs........................763 35.4.4 Pulse-Out's..............................764 35.4.5 Updating the delay registers.........................765 35.4.6 Interrupts..............................766 35.4.7...
- Page 30 Section number Title Page 36.3.9 Capture And Compare Status (FTMx_STATUS)..................786 36.3.10 Features Mode Selection (FTMx_MODE)....................788 36.3.11 Synchronization (FTMx_SYNC).........................790 36.3.12 Initial State For Channels Output (FTMx_OUTINIT).................793 36.3.13 Output Mask (FTMx_OUTMASK)......................794 36.3.14 Function For Linked Channels (FTMx_COMBINE)...................796 36.3.15 Deadtime Insertion Control (FTMx_DEADTIME)..................801 36.3.16 FTM External Trigger (FTMx_EXTTRIG)....................802 36.3.17...
- Page 31 Section number Title Page 36.4.10 Registers updated from write buffers......................846 36.4.11 PWM synchronization..........................848 36.4.12 Inverting...............................864 36.4.13 Software output control..........................865 36.4.14 Deadtime insertion............................867 36.4.15 Output mask..............................870 36.4.16 Fault control..............................871 36.4.17 Polarity control.............................874 36.4.18 Initialization..............................875 36.4.19 Features priority............................875 36.4.20 Channel trigger output..........................876 36.4.21 Initialization trigger............................877 36.4.22...
- Page 32 Section number Title Page 37.2 Signal description................................902 37.3 Memory map/register description..........................903 37.3.1 PIT Module Control Register (PIT_MCR)....................903 37.3.2 Timer Load Value Register (PIT_LDVALn)....................904 37.3.3 Current Timer Value Register (PIT_CVALn).....................905 37.3.4 Timer Control Register (PIT_TCTRLn)......................905 37.3.5 Timer Flag Register (PIT_TFLGn)......................906 37.4 Functional description..............................907 37.4.1 General operation............................907...
- Page 33 Section number Title Page 38.4.3 LPTMR prescaler/glitch filter........................918 38.4.4 LPTMR compare............................919 38.4.5 LPTMR counter............................919 38.4.6 LPTMR hardware trigger..........................920 38.4.7 LPTMR interrupt............................920 Chapter 39 Carrier Modulator Transmitter (CMT) 39.1 Introduction...................................921 39.2 Features..................................921 39.3 Block diagram................................922 39.4 Modes of operation...............................923 39.4.1 Wait mode operation............................924 39.4.2 Stop mode operation............................925 39.5...
- Page 34 Section number Title Page 39.7 Functional description..............................936 39.7.1 Clock divider..............................936 39.7.2 Carrier generator............................936 39.7.3 Modulator..............................939 39.7.4 Extended space operation..........................943 39.8 CMT interrupts and DMA............................945 Chapter 40 Real Time Clock (RTC) 40.1 Introduction...................................947 40.1.1 Features................................947 40.1.2 Modes of operation............................947 40.1.3 RTC Signal Descriptions..........................948 40.2 Register definition.................................948 40.2.1...
- Page 35 Section number Title Page 40.3.6 Register lock..............................963 40.3.7 Access control..............................963 40.3.8 Interrupt................................963 Chapter 41 CAN (FlexCAN) 41.1 Introduction...................................965 41.1.1 Overview..............................966 41.1.2 FlexCAN module features...........................967 41.1.3 Modes of operation............................968 41.2 FlexCAN signal descriptions............................970 41.2.1 CAN Rx ...............................970 41.2.2 CAN Tx ...............................970 41.3 Memory map/register definition...........................970 41.3.1...
- Page 36 Section number Title Page 41.3.17 Rx Individual Mask Registers (CANx_RXIMRn)..................1001 41.3.34 Message buffer structure..........................1002 41.3.35 Rx FIFO structure............................1008 41.4 Functional description..............................1010 41.4.1 Transmit process............................1011 41.4.2 Arbitration process............................1011 41.4.3 Receive process............................1015 41.4.4 Matching process............................1017 41.4.5 Move process...............................1022 41.4.6 Data coherence.............................1023 41.4.7 Rx FIFO...............................1027 41.4.8 CAN protocol related features........................1028...
- Page 37 Section number Title Page 42.2.4 SIN — Serial Input............................1049 42.2.5 SOUT — Serial Output..........................1049 42.2.6 SCK — Serial Clock............................1049 42.3 Memory Map/Register Definition..........................1049 42.3.1 Module Configuration Register (SPIx_MCR).....................1052 42.3.2 DSPI Transfer Count Register (SPIx_TCR)....................1055 42.3.3 DSPI Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)........1055 42.3.4 DSPI Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE)......1060 42.3.5...
- Page 38 Section number Title Page 42.5.5 Delay settings...............................1091 42.5.6 Calculation of FIFO pointer addresses......................1092 Chapter 43 Inter-Integrated Circuit (I2C) 43.1 Introduction...................................1095 43.1.1 Features................................1095 43.1.2 Modes of operation............................1096 43.1.3 Block diagram..............................1096 43.2 I2C signal descriptions..............................1097 43.3 Memory map and register descriptions.........................1097 43.3.1 I2C Address Register 1 (I2Cx_A1)......................1098 43.3.2 I2C Frequency Divider register (I2Cx_F)....................1099...
- Page 39 Section number Title Page 43.4.6 Interrupts..............................1119 43.4.7 Programmable input glitch filter........................1121 43.4.8 Address matching wakeup...........................1122 43.4.9 DMA support...............................1122 43.5 Initialization/application information...........................1123 Chapter 44 Universal Asynchronous Receiver/Transmitter (UART) 44.1 Introduction...................................1127 44.1.1 Features................................1127 44.1.2 Modes of operation............................1129 44.2 UART signal descriptions.............................1130 44.2.1 Detailed signal descriptions.........................1131 44.3 Memory map and registers............................1132...
- Page 40 Section number Title Page 44.3.17 UART FIFO Control Register (UARTx_CFIFO)..................1161 44.3.18 UART FIFO Status Register (UARTx_SFIFO)...................1162 44.3.19 UART FIFO Transmit Watermark (UARTx_TWFIFO)................1163 44.3.20 UART FIFO Transmit Count (UARTx_TCFIFO)..................1164 44.3.21 UART FIFO Receive Watermark (UARTx_RWFIFO)................1164 44.3.22 UART FIFO Receive Count (UARTx_RCFIFO)..................1165 44.3.23 UART 7816 Control Register (UARTx_C7816)..................1165 44.3.24...
- Page 41 Section number Title Page 44.3.46 UART CEA709.1-B Collision Pulse Width (UARTx_CPW)..............1181 44.3.47 UART CEA709.1-B Receive Indeterminate Time (UARTx_RIDT)............1181 44.3.48 UART CEA709.1-B Transmit Indeterminate Time (UARTx_TIDT)............1182 44.4 Functional description..............................1182 44.4.1 CEA709.1-B..............................1182 44.4.2 Transmitter..............................1192 44.4.3 Receiver...............................1198 44.4.4 Baud rate generation............................1207 44.4.5 Data format (non ISO-7816)........................1209 44.4.6 Single-wire operation...........................1212 44.4.7...
- Page 42 Section number Title Page Chapter 45 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) 45.1 Introduction...................................1231 45.1.1 Features................................1231 45.1.2 Block diagram..............................1231 45.1.3 Modes of operation............................1232 45.2 External signals................................1233 45.3 Memory map and register definition..........................1233 45.3.1 SAI Transmit Control Register (I2Sx_TCSR).....................1235 45.3.2 SAI Transmit Configuration 1 Register (I2Sx_TCR1)................1238 45.3.3...
- Page 43 Section number Title Page 45.4 Functional description..............................1256 45.4.1 SAI clocking..............................1256 45.4.2 SAI resets..............................1257 45.4.3 Synchronous modes.............................1258 45.4.4 Frame sync configuration..........................1259 45.4.5 Data FIFO..............................1260 45.4.6 Word mask register............................1261 45.4.7 Interrupts and DMA requests........................1261 Chapter 46 General-Purpose Input/Output (GPIO) 46.1 Introduction...................................1265 46.1.1 Features................................1265 46.1.2 Modes of operation............................1265...
- Page 44 Section number Title Page 47.3 Overview..................................1274 47.3.1 Electrode capacitance measurement unit.....................1274 47.3.2 Electrode scan unit............................1275 47.3.3 Touch detection unit.............................1276 47.4 Modes of operation...............................1276 47.4.1 TSI disabled mode............................1277 47.4.2 TSI active mode............................1277 47.4.3 TSI low-power mode...........................1277 47.4.4 Block diagram..............................1278 47.5 TSI signal descriptions..............................1279 47.5.1 TSI_IN[15:0]..............................1279 47.6...
- Page 45 Section number Title Page Chapter 48 LCD Controller (SLCD) 48.1 Introduction ..................................1299 48.1.1 Features................................1299 48.1.2 Modes of operation............................1300 48.1.3 Block diagram..............................1301 48.2 LCD signal descriptions..............................1302 48.2.1 LCD_P[63:0]..............................1303 48.2.2 VLL1, VLL2, VLL3............................1303 48.2.3 Vcap1, Vcap2...............................1303 48.3 Memory map and register definition..........................1303 48.3.1 LCD General Control Register (LCD_GCR)....................1304 48.3.2...
- Page 46 Section number Title Page 48.3.19 LCD Waveform register (LCD_WF51TO48)....................1323 48.3.20 LCD Waveform register (LCD_WF55TO52)....................1324 48.3.21 LCD Waveform register (LCD_WF59TO56)....................1324 48.3.22 LCD Waveform register (LCD_WF63TO60)....................1325 48.4 Functional description..............................1325 48.4.1 LCD controller driver description........................1326 48.4.2 WFyTOx registers............................1335 48.4.3 LCD display modes............................1336 48.4.4 LCD charge pump and power supply operation..................1338 48.4.5 Resets................................1343...
- Page 47 Section number Title Page 49.3 Register description..............................1369 49.3.1 Instruction register............................1369 49.3.2 Bypass register.............................1369 49.3.3 Device identification register........................1369 49.3.4 Boundary scan register..........................1370 49.4 Functional description..............................1371 49.4.1 JTAGC reset configuration..........................1371 49.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port....................1371 49.4.3 TAP controller state machine........................1371 49.4.4 JTAGC block instructions..........................1373 49.4.5...
- Page 48 K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Page 49: About This Document
Chapter 1 About This Document Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the Freescale K30 microcontroller. 1.1.2 Audience This document is primarily for system architects and software application developers who are using or considering using the K30 microcontroller in a system. Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems:... -
Page 50: Typographic Notation
Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers. -
Page 51: Introduction
Chapter 2 Introduction 2.1 Overview This chapter provides high-level descriptions of the modules available on the devices covered by this document. 2.2 Module Functional Categories The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail. Table 2-1. -
Page 52: Arm Cortex-M4 Core Modules
Module Functional Categories Table 2-1. Module functional categories (continued) Module category Description Clocks • Multiple clock generation options available from internally- and externally- generated clocks • System oscillator to provide clock source for the MCU • RTC oscillator to provide clock source for the RTC Security •... -
Page 53: System Modules
Chapter 2 Introduction Table 2-2. Core modules (continued) Module Description NVIC The ARMv7-M exception model and nested-vectored interrupt controller (NVIC) implement a relocatable vector table supporting many external interrupts, a single non-maskable interrupt (NMI), and priority levels. The NVIC replaces shadow registers with equivalent system and simplified programmability. -
Page 54: Memories And Memory Interfaces
Module Functional Categories Table 2-3. System modules (continued) Module Description Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer control descriptors for data movement via dual-address transfers for 8-, 16-, 32- and 128- bit data values. External watchdog monitor (EWM) The EWM is a redundant mechanism to the software watchdog module that monitors both internal and external system operation for fail conditions. -
Page 55: Security And Integrity Modules
Chapter 2 Introduction Table 2-5. Clock modules Module Description Multi-clock generator (MCG) The MCG provides several clock sources for the MCU that include: • Phase-locked loop (PLL) — Voltage-controlled oscillator (VCO) • Frequency-locked loop (FLL) — Digitally-controlled oscillator (DCO) • Internal reference clocks — Can be used as a clock source for other on-chip peripherals System oscillator The system oscillator, in conjunction with an external crystal or resonator,... -
Page 56: Timer Modules
Module Functional Categories 2.2.7 Timer modules The following timer modules are available on this device: Table 2-8. Timer modules Module Description Programmable delay block (PDB) • 16-bit resolution • 3-bit prescaler • Positive transition of trigger event signal initiates the counter •... -
Page 57: Communication Interfaces
Chapter 2 Introduction Table 2-8. Timer modules (continued) Module Description Carrier modulator timer (CMT) • Four CMT modes of operation: • Time with independent control of high and low times • Baseband • Frequency shift key (FSK) • Direct software control of CMT_IRO pin •... -
Page 58: Orderable Part Numbers
160 KB 128 KB 2 KB 32 KB MK30DX256VLL7 72 MHz LQFP 288 KB 256 KB 2 KB 64 KB MK30DX64VMC7 72 MHz MAPBGA 96 KB 64 KB 2 KB 16 KB MK30DX128VMC7 72 MHz MAPBGA 160 KB 128 KB... -
Page 59: Chip Configuration
Chapter 3 Chip Configuration 3.1 Introduction This chapter provides details on the individual modules of the microcontroller. It includes: • module block diagrams showing immediate connections within the device, • specific module-to-module interactions not necessarily discussed in the individual module chapters, and •... -
Page 60: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Core modules Debug Interrupts SRAM Upper ARM Cortex-M4 Crossbar switch Core SRAM Lower Figure 3-1. Core configuration Table 3-1. Reference links to related information Topic Related module Reference Full description ARM Cortex-M4 core, ARM Cortex-M4 Technical Reference Manual r0p1 System memory map System memory map Clocking Clock distribution... -
Page 61: Nested Vectored Interrupt Controller (Nvic) Configuration
Chapter 3 Chip Configuration Bus name Description System bus The system bus is connected to a separate master port on the crossbar. In addition, the system bus is tightly coupled to the upper half system RAM (SRAM_U). Private peripheral (PPB) bus The PPB provides access to these modules: •... -
Page 62: Freescale Semiconductor, Inc
Core modules Interrupts Module Nested Vectored Module Interrupt Controller (NVIC) Module Figure 3-2. NVIC configuration Table 3-2. Reference links to related information Topic Related module Reference Full description Nested Vectored ARM Cortex-M4 Technical Reference Manual Interrupt Controller (NVIC) System memory map System memory map Clocking Clock distribution... -
Page 63: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration • Vector number — the value stored on the stack when an interrupt is serviced. • IRQ number — non-core interrupt source count, which is the vector number minus The IRQ number is used within ARM's NVIC documentation. Table 3-4. -
Page 64: Freescale Semiconductor, Inc
Core modules Table 3-4. Interrupt vector assignments (continued) Address Vector NVIC NVIC Source module Source description non-IPR register register number number 0x0000_006C DMA channel 11 transfer complete 0x0000_0070 DMA channel 12 transfer complete 0x0000_0074 DMA channel 13 transfer complete 0x0000_0078 DMA channel 14 transfer complete 0x0000_007C DMA channel 15 transfer complete... -
Page 65: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration Table 3-4. Interrupt vector assignments (continued) Address Vector NVIC NVIC Source module Source description non-IPR register register number number 0x0000_00EC — — 0x0000_00F0 UART0 Single interrupt vector for UART LON sources 0x0000_00F4 UART0 Single interrupt vector for UART status sources 0x0000_00F8 UART0... -
Page 66: Freescale Semiconductor, Inc
Core modules Table 3-4. Interrupt vector assignments (continued) Address Vector NVIC NVIC Source module Source description non-IPR register register number number 0x0000_0160 — 0x0000_0164 — — 0x0000_0168 — — 0x0000_016C — — 0x0000_0170 — — 0x0000_0174 — — 0x0000_0178 — —... -
Page 67: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
Chapter 3 Chip Configuration Table 3-5. LPTMR interrupt vector assignment Address Vector NVIC NVIC Source module Source description non-IPR register register number number 0x0000_0194 Low Power Timer — 1. Indicates the NVIC's interrupt source number. 2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. -
Page 68: Freescale Semiconductor, Inc
Core modules Clock logic Wake-up requests Asynchronous Module Wake-up Interrupt Controller (AWIC) Module Figure 3-3. Asynchronous Wake-up Interrupt Controller configuration Table 3-6. Reference links to related information Topic Related module Reference System memory map System memory map Clocking Clock distribution Power management Power management Nested Vectored... -
Page 69: Jtag Controller Configuration
Chapter 3 Chip Configuration 3.2.4 JTAG Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. JTAG controller Figure 3-4. JTAGC Controller configuration Table 3-8. -
Page 70: System Mode Controller (Smc) Configuration
System modules Peripheral bridge Register access System integration module (SIM) Figure 3-5. SIM configuration Table 3-9. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock distribution Power management Power management 3.3.2 System Mode Controller (SMC) Configuration This section summarizes how the module has been configured in the chip. -
Page 71: Pmc Configuration
Chapter 3 Chip Configuration Table 3-10. Reference links to related information (continued) Topic Related module Reference Power management controller (PMC) Low-Leakage Wakeup LLWU Unit (LLWU) Reset Control Module Reset (RCM) 3.3.3 PMC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. -
Page 72: Low-Leakage Wake-Up Unit (Llwu) Configuration
System modules 3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 0 Register access Wake-up requests Low-Leakage Wake-up Module Unit (LLWU) -
Page 73: Mcm Configuration
Chapter 3 Chip Configuration Table 3-13. Wakeup sources for LLWU inputs Input Wakeup source Input Wakeup source LLWU_P0 PTE1/LLWU_P0 pin LLWU_P12 PTD0/LLWU_P12 pin LLWU_P1 PTE2/LLWU_P1 pin LLWU_P13 PTD2/LLWU_P13 pin LLWU_P2 PTE4/LLWU_P2 pin LLWU_P14 PTD4/LLWU_P14 pin LLWU_P3 PTA4/LLWU_P3 pin LLWU_P15 PTD6/LLWU_P15 pin LLWU_P4 PTA13/LLWU_P4 pin LLWU_M0IF... -
Page 74: Crossbar Switch Configuration
System modules 3.3.6 Crossbar Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Table 3-15. Reference links to related information Topic Related module Reference Full description Crossbar switch... -
Page 75: Peripheral Bridge Configuration
Chapter 3 Chip Configuration Slave module Slave port number Flash memory controller SRAM backdoor Peripheral bridge 0 Peripheral bridge 1/GPIO 1. See System memory map for access restrictions. 3.3.6.3 PRS register reset values The AXBS_PRSn registers reset to 0000_3210h. 3.3.7 Peripheral Bridge Configuration This section summarizes how the module has been configured in the chip. -
Page 76: Dma Request Multiplexer Configuration
System modules 3.3.7.2 Memory maps The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map AIPS1 Memory Map for the memory slot assignment for each module. 3.3.7.3 MPRA register Each of the two peripheral bridges supports up to 8 crossbar switch masters, each assigned to a MPROTx field in the MPRA register. -
Page 77: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration Peripheral bridge 0 Register access Requests Module Channel request DMA Request Module Multiplexer Module Figure 3-11. DMA request multiplexer configuration Table 3-17. Reference links to related information Topic Related module Reference Full description DMA request DMA Mux multiplexer System memory map System memory map... -
Page 78: Freescale Semiconductor, Inc
System modules Table 3-18. DMA request sources - MUX 0 (continued) Source Source module Source description number UART3 Transmit UART4 Receive UART4 Transmit Reserved — Reserved — Receive Transmit SPI0 Receive SPI0 Transmit SPI1 Receive SPI1 Transmit Reserved — Reserved —... -
Page 79: Dma Controller Configuration
Chapter 3 Chip Configuration Table 3-18. DMA request sources - MUX 0 (continued) Source Source module Source description number — Port control module Port A Port control module Port B Port control module Port C Port control module Port D Port control module Port E DMA MUX... -
Page 80: External Watchdog Monitor (Ewm) Configuration
System modules Peripheral bridge 0 Register access Transfers Requests DMA Controller Figure 3-12. DMA Controller configuration Table 3-19. Reference links to related information Topic Related module Reference Full description DMA Controller DMA Controller System memory map System memory map Register access Peripheral bridge AIPS-Lite 0 (AIPS-Lite 0) -
Page 81: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration Peripheral bridge 0 Register access Module signals External Watchdog Monitor (EWM) Figure 3-13. External Watchdog Monitor configuration Table 3-20. Reference links to related information Topic Related module Reference Full description External Watchdog Monitor (EWM) System memory map System memory map Clocking Clock distribution... -
Page 82: Watchdog Configuration
System modules 3.3.10.3 EWM_OUT pin state in low power modes During Wait, Stop and Power Down modes the EWM_OUT pin enters a high-impedance state. A user has the option to control the logic state of the pin using an external pull device or by configuring the internal pull device. -
Page 83: Clock Modules
Chapter 3 Chip Configuration Table 3-24. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Alt Clock Bus Clock Fast Test Clock Bus Clock System Bus Clock Bus Clock 3.3.11.2 WDOG low-power modes This table shows the WDOG low-power modes and the corresponding chip low-power modes. -
Page 84: Osc Configuration
Clock modules Peripheral bridge Register access Multipurpose Clock Generator (MCG) Figure 3-15. MCG configuration Table 3-26. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing... -
Page 85: Rtc Osc Configuration
Chapter 3 Chip Configuration Table 3-27. Reference links to related information (continued) Topic Related module Reference Power management Power management Signal multiplexing Port control Signal multiplexing Full description 3.4.2.1 OSC modes of operation with MCG The MCG's C2 register bits configure the oscillator frequency range. See the OSC and MCG chapters for more details. -
Page 86: Freescale Semiconductor, Inc
Memories and memory interfaces Peripheral bus controller 0 Register access Transfers Flash memory Figure 3-18. Flash memory configuration Table 3-29. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory System memory map System memory map Clocking Clock Distribution Transfers... -
Page 87: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration Device Program Block 0 (P- FlexNVM Block 1 FlexRAM FlexRAM flash (KB) Flash) (KB) (FlexNVM) (KB) address address address range range range MK30DX128VL 0x0000_0000 – 0x1000_0000 – 0x1400_0000 – 0x0003_FFFF 0x1000_7FFF 0x1400_07FF MK30DX256VL 0x0000_0000 – 0x1000_0000 – 0x1400_0000 –... -
Page 88: Flash Memory Controller Configuration
Memories and memory interfaces 3.5.1.5 Flash Modes The flash memory operates in NVM normal and NVM special modes. The flash memory enters NVM special mode when the EzPort is enabled (EZP_CS asserted during reset). Otherwise, flash memory operates in NVM normal mode. 3.5.1.6 Erase All Flash Contents In addition to software, the entire flash memory may be erased external to the flash memory in two ways:... -
Page 89: Sram Configuration
Chapter 3 Chip Configuration Peripheral bus controller 0 Register access Transfers Transfers Flash memory controller Figure 3-20. Flash memory controller configuration Table 3-30. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory controller controller System memory map System memory map Clocking... -
Page 90: Freescale Semiconductor, Inc
This device contains SRAM tightly coupled to the ARM Cortex-M4 core. The amount of SRAM for the devices covered in this document is shown in the following table. Device SRAM (KB) MK30DX128VLL7 MK30DX256VLL7 MK30DX64VMC7 MK30DX128VMC7 MK30DX256VMC7 3.5.3.2 SRAM Arrays The on-chip SRAM is split into two equally-sized logical arrays, SRAM_L and SRAM_U. -
Page 91: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration 0x2000_0000 – SRAM_size/2 SRAM_L 0x1FFF_FFFF 0x2000_0000 SRAM_U 0x2000_0000 + SRAM_size/2 - 1 Figure 3-22. SRAM blocks memory map For example, for a device containing 64 KB of SRAM the ranges are: • SRAM_L: 0x1FFF_8000 – 0x1FFF_FFFF •... -
Page 92: Sram Controller Configuration
Memories and memory interfaces SRAM_L Cortex-M4 core Crossbar switch non-core master Frontdoor Backdoor Code bus non-core master SRAM controller System bus non-core master SRAM_U Figure 3-23. SRAM access diagram The following simultaneous accesses can be made to different logical halves of the SRAM: •... -
Page 93: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Chapter 3 Chip Configuration Cortex-M4 core SRAM controller Transfers Crossbar switch Figure 3-24. SRAM controller configuration Table 3-32. Reference links to related information Topic Related module Reference System memory map System memory map Power management Power management Power management controller (PMC) Transfers SRAM SRAM... -
Page 94: Vbat Register File Configuration
Memories and memory interfaces 3.5.5.1 System Register file This device includes a 32-byte register file that is powered in all power modes. Also, it retains contents during low-voltage detect (LVD) events and is only reset during a power-on reset. 3.5.6 VBAT Register File Configuration This section summarizes how the module has been configured in the chip. -
Page 95: Ezport Configuration
Chapter 3 Chip Configuration 3.5.7 EzPort Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Module signals Transfers EzPort Figure 3-27. EzPort configuration Table 3-35. -
Page 96: Analog
Security 3.6 Security 3.6.1 CRC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Register access Figure 3-28. CRC configuration Table 3-36. Reference links to related information Topic Related module Reference... -
Page 97: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration Peripheral bus controller 0 Register access Module signals Transfers 16-bit SAR ADC Other peripherals Figure 3-29. 16-bit SAR ADC with PGA configuration Table 3-37. Reference links to related information Topic Related module Reference Full description 16-bit SAR ADC with 16-bit SAR ADC with PGA System memory map System memory map... -
Page 98: Freescale Semiconductor, Inc
Connections/Channel Assignment 3.7.1.3 Connections/Channel Assignment 3.7.1.3.1 ADC0 Connections/Channel Assignment NOTE As indicated by the following sections, each ADCx_DPx input and certain ADCx_DMx inputs may operate as single-ended ADC channels in single-ended mode. 3.7.1.3.1.1 ADC0 Channel Assignment for 121-Pin Package ADC Channel Channel Input signal Input signal... -
Page 99: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration ADC Channel Channel Input signal Input signal (SC1n[ADCH]) (SC1n[DIFF]= 1) (SC1n[DIFF]= 0) 10111 AD23 Reserved 12-bit DAC0 Output/ ADC0_SE23 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff) Bandgap (S.E) -
Page 100: Freescale Semiconductor, Inc
Connections/Channel Assignment ADC Channel Channel Input signal Input signal (SC1n[ADCH]) (SC1n[DIFF]= 1) (SC1n[DIFF]= 0) 01100 AD12 Reserved ADC0_SE12 01101 AD13 Reserved ADC0_SE13 01110 AD14 Reserved ADC0_SE14 01111 AD15 Reserved ADC0_SE15 10000 AD16 Reserved Reserved 10001 AD17 Reserved ADC0_SE17 10010 AD18 Reserved ADC0_SE18 10011... -
Page 101: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration 3.7.1.4.1 ADC1 Channel Assignment for 121-Pin Package ADC Channel Channel Input signal Input signal (SC1n[ADCH]) (SC1n[DIFF]= 1) (SC1n[DIFF]= 0) 00000 DAD0 ADC1_DP0 and ADC1_DM0 ADC1_DP0 00001 DAD1 ADC1_DP1 and ADC1_DM1 ADC1_DP1 00010 DAD2 PGA1_DP and PGA1_DM PGA1_DP 00011 DAD3... -
Page 102: Freescale Semiconductor, Inc
Connections/Channel Assignment 4. Interleaved with ADC0_DP0 5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details. 6. Interleaved with ADC0_SE8 7. Interleaved with ADC0_SE9 8. Interleaved with ADC0_DM3 9. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. -
Page 103: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration ADC Channel Channel Input signal Input signal (SC1n[ADCH]) (SC1n[DIFF]= 1) (SC1n[DIFF]= 0) 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff) Bandgap (S.E) 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110 AD30 Reserved... -
Page 104: Freescale Semiconductor, Inc
Connections/Channel Assignment ADC0 ADC0_SE8/ADC1_SE8 ADC0_SE9/ADC1_SE9 ADC1 Figure 3-31. ADC hardware interleaved channels integration 3.7.1.7 ADC and PGA Reference Options The ADC supports the following references: • VREFH/VREFL - connected as the primary reference option • 1.2 V VREF_OUT - connected as the V reference option ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC. -
Page 105: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration 3.7.1.8 ADC triggers The ADC supports both software and hardware triggers. The primary hardware mechanism for triggering the ADC is the PDB. The PDB itself can be triggered by other peripherals. For example: RTC (Alarm, Seconds) signal is connected to the PDB. The PDB trigger can receive the RTC (alarm/seconds) trigger input forcing ADC conversions in run mode (where PDB is enabled). -
Page 106: Cmp Configuration
Connections/Channel Assignment • Each PGA connects to the differential ADC channels • The PGA outputs differential pairs that are connected to ADC differential input • When the PGA is used, differential input from the pins is connected to differential input channel 2 on ADCx ADC0 ADC0_DP1 DAD1... -
Page 107: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration Peripheral bridge 0 Register access Module signals Other peripherals Figure 3-33. CMP configuration Table 3-39. Reference links to related information Topic Related module Reference Full description Comparator (CMP) Comparator System memory map System memory map Clocking Clock distribution Power management Power management... -
Page 108: 12-Bit Dac Configuration
Connections/Channel Assignment • VREF_OUT - V input • VDD - V input 3.7.2.3 External window/sample input Individual PDB pulse-out signals control each CMP Sample/Window timing. 3.7.3 12-bit DAC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. -
Page 109: Vref Configuration
Chapter 3 Chip Configuration 3.7.3.2 12-bit DAC Output The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. 3.7.3.3 12-bit DAC Reference For this device VREF_OUT and VDDA are selectable as the DAC reference. VREF_OUT is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input. -
Page 110: Timers
Timers 3.7.4.1 VREF Overview This device includes a voltage reference (VREF) to supply an accurate 1.2 V voltage output. The voltage reference can provide a reference voltage to external peripherals or a reference to analog peripherals, such as the ADC, DAC, or CMP. NOTE PMC_REGSC[BGEN] bit must be set if the VREF regulator is required to remain operating in VLPx modes. -
Page 111: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration Table 3-43. Reference links to related information (continued) Topic Related module Reference Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.8.1.1 PDB Instantiation 3.8.1.1.1 PDB Output Triggers Table 3-44. PDB output triggers Number of PDB channels for ADC trigger Number of pre-triggers per PDB channel Number of DAC triggers... -
Page 112: Freescale Semiconductor, Inc
Timers 3.8.1.2 PDB Module Interconnections PDB trigger outputs Connection Channel 0 triggers ADC0 trigger Channel 1 triggers ADC1 trigger and synchronous input 1 of FTM0 DAC triggers DAC0 trigger Pulse-out Pulse-out connected to each CMP module's sample/window input to control sample operation 3.8.1.3 Back-to-back acknowledgement connections In this MCU, PDB back-to-back operation acknowledgment connections are implemented as follows:... -
Page 113: Flextimer Configuration
Chapter 3 Chip Configuration 3.8.1.5 DAC External Trigger Input Connections In this MCU, the following DAC external trigger inputs are implemented. • DAC external trigger input 0: ADC0SC1A_COCO • DAC external trigger input 1: ADC1SC1A_COCO NOTE Application code can set the PDBx_DACINTCn[EXT] bit to allow DAC external trigger input when the corresponding ADC Conversion complete flag, ADCx_SC1n[COCO], is set. -
Page 114: Freescale Semiconductor, Inc
Timers Peripheral bus controller 0 Register access Module signals Transfers FlexTimer Other peripherals Figure 3-38. FlexTimer configuration Table 3-47. Reference links to related information Topic Related module Reference Full description FlexTimer FlexTimer System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing... -
Page 115: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration 3.8.2.2 External Clock Options By default each FTM is clocked by the internal bus clock (the FTM refers to it as system clock). Each module contains a register setting that allows the module to be clocked from an external clock instead. -
Page 116: Freescale Semiconductor, Inc
Timers • FTM0 hardware trigger 0 = CMP0 Output or FTM1 Match (when enabled in the FTM1 External Trigger (EXTTRIG) register) • FTM0 hardware trigger 1 = PDB channel 1 Trigger Output or FTM2 Match (when enabled in the FTM2 External Trigger (EXTTRIG) register) •... -
Page 117: Pit Configuration
Chapter 3 Chip Configuration FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: FTM1 CONF Register GTBEOUT = 0 FTM0 FTM Counter GTBEEN = 1 CONF Register gtb_in gtb_in... -
Page 118: Low-Power Timer Configuration
Timers Table 3-49. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Power management Power management 3.8.3.1 PIT/DMA Periodic Trigger Assignments The PIT generates periodic trigger events to the DMA Mux as shown in the table below. Table 3-50. -
Page 119: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration Peripheral bridge Register access Module signals Low-power timer Figure 3-41. LPT configuration Table 3-51. Reference links to related information Topic Related module Reference Full description Low-power timer Low-power timer System memory map System memory map Clocking Clock Distribution Power management Power management... -
Page 120: Cmt Configuration
Timers 3.8.4.2 LPTMR pulse counter input options The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input CMP0 output LPTMR_ALT1 pin LPTMR_ALT2 pin LPTMR_ALT3 pin 3.8.5 CMT Configuration... -
Page 121: Rtc Configuration
Chapter 3 Chip Configuration 3.8.5.2 IRO Drive Strength The IRO pad requires higher current drive than can be obtained from a single pad. For this device, the pin associated with the CMT_IRO signal is doubled bonded to two pads. The SOPT2[PTD7PAD] field in SIM module can be used to configure the pin associated with the CMT_IRO signal as a higher current output port pin. -
Page 122: Communication Interfaces
Communication interfaces RTC_CR[CLKO] RTC 32kHz clock RTC_CLKOUT RTC 1Hz clock SIM_SOPT2[RTCCLKOUTSEL] Figure 3-44. RTC_CLKOUT generation 3.9 Communication interfaces 3.9.1 CAN Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Register... -
Page 123: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration 3.9.1.1 Reset value of MDIS bit The CAN_MCR[MDIS] bit is set after reset. Therefore, FlexCAN module is disabled following a reset. 3.9.1.2 Number of message buffers Each FlexCAN module contains 16 message buffers. Each message buffer is 16 bytes. 3.9.1.3 FlexCAN Clocking 3.9.1.3.1 Clocking Options The FlexCAN module has a register bit CANCTRL[CLK_SRC] that selects between... -
Page 124: Spi Configuration
Communication interfaces Request Sources Error • Bit1 error • Bit0 error • Acknowledge error • Cyclic redundancy check (CRC) error • Form error • Stuffing error • Transmit error warning • Receive error warning Transmit Warning Transmit Warning Receive Warning Receive Warning Wake-up Wake-up... -
Page 125: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration Peripheral bridge Register access Module signals Figure 3-46. SPI configuration Table 3-55. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Signal Multiplexing Port control Signal Multiplexing 3.9.2.1 SPI Modules Configuration This device contains two SPI modules. -
Page 126: Freescale Semiconductor, Inc
Communication interfaces 3.9.2.4 TX FIFO size Table 3-56. SPI transmit FIFO size SPI Module Transmit FIFO size SPI0 SPI1 3.9.2.5 RX FIFO Size SPI supports up to 16-bit frame size during reception. Table 3-57. SPI receive FIFO size SPI Module Receive FIFO size SPI0 SPI1... -
Page 127: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration There is one way to wake from stop mode via the SPI, which is explained in the following section. 3.9.2.7.1 Using GPIO Interrupt to Wake from stop mode Here are the steps to use a GPIO to create a wakeup upon reception of SPI data in slave mode: 1. -
Page 128: I2C Configuration
Communication interfaces 3.9.3 I2C Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Register access Module signals Figure 3-47. I2C configuration Table 3-60. -
Page 129: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration Peripheral bridge Register access Module signals UART Figure 3-48. UART configuration Table 3-61. Reference links to related information Topic Related module Reference Full description UART UART System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control... -
Page 130: Freescale Semiconductor, Inc
Communication interfaces 3.9.4.2 UART wakeup The UART can be configured to generate an interrupt/wakeup on the first active edge that it receives. 3.9.4.3 UART interrupts The UART has multiple sources of interrupt requests. However, some of these sources are OR'd together to generate a single interrupt request. See below for the mapping of the individual interrupt sources to the interrupt request: The status interrupt combines the following interrupt sources: Source... -
Page 131: I2S Configuration
Chapter 3 Chip Configuration Source UART 0 UART 1 UART 2 UART 3 UART 4 Character wait — — — — timer (ISO7816) Block wait timer — — — — (ISO7816) Guard time — — — — violation (ISO7816) The LON status interrupt combines the following interrupt sources: Source UART 0 UART 1... -
Page 132: Freescale Semiconductor, Inc
Communication interfaces Peripheral bridge Register access Module signals Figure 3-49. I S configuration Table 3-62. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management Signal multiplexing Port control Signal Multiplexing 3.9.5.1 Instantiation information... -
Page 133: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration 3.9.5.2.2 Bit Clock The I S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can be generated internally from the audio master clock or supplied externally. The module also supports the option for synchronous operation between the receiver and transmitterproduct. -
Page 134: Human-Machine Interfaces
Human-machine interfaces 3.9.5.2.5 Clock gating and I S/SAI initialization The clock to the I S/SAI module can be gated using a bit in the SIM. To minimize power consumption, these bits are cleared after any reset, which disables the clock to the corresponding module. -
Page 135: Tsi Configuration
Chapter 3 Chip Configuration Peripheral bridge Register access Transfers Module signals GPIO controller Figure 3-50. GPIO configuration Table 3-64. Reference links to related information Topic Related module Reference Full description GPIO GPIO System memory map System memory map Clocking Clock Distribution Power management Power management Transfers... -
Page 136: Freescale Semiconductor, Inc
Human-machine interfaces Peripheral bridge Register access Module signals Touch sense input module Figure 3-51. TSI configuration Table 3-65. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control... -
Page 137: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration Table 3-66. TSI module functionality in MCU operation modes (continued) MCU operation mode TSI clock sources TSI operation mode Functional electrode Required when GENCS[TSIEN] pins GENCS[STPE] state is 1 VLPW Flash clock, Active mode Don’t care MCGIRCLK, OSCERCLK VLPS... -
Page 138: Segment Lcd Configuration
Human-machine interfaces 3.10.3 Segment LCD Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bus controller 0 Register access Module signals Segment LCD Figure 3-52. -
Page 139: Freescale Semiconductor, Inc
Chapter 3 Chip Configuration 3.10.3.2 LCD pin assignments Configure the mux control registers to assign the corresponding module function to a pin. For normal operation of the LCD, use ALT0 LCD functions. The ALT7 LCD functions are only available for LCD fault detection. See the Signal Multiplexing and Signal Descriptions chapter for the number of LCD pins... -
Page 140: Freescale Semiconductor, Inc
Human-machine interfaces 3.10.3.5 Segment LCD Interrupts The Segment LCD has multiple interrupt sources. However, all of these sources are OR'd together to generate a single interrupt request. Read the LFDSR and LGCR registers to determine the cause of the interrupt. K30 Sub-Family Reference Manual, Rev. -
Page 141: Introduction
Chapter 4 Memory Map 4.1 Introduction This device contains various memories and memory-mapped peripherals which are located in one 32-bit contiguous memory space. This chapter describes the memory and peripheral locations within that memory space. 4.2 System memory map The following table shows the high-level device memory map. Table 4-1. -
Page 142: Aliased Bit-Band Regions
System memory map Table 4-1. System memory map (continued) System 32-bit Address Range Destination Slave Access 0x4010_0000–0x41FF_FFFF Reserved – 0x4200_0000–0x43FF_FFFF Aliased to peripheral bridge (AIPS-Lite) and general purpose Cortex-M4 core input/output (GPIO) bitband only 0x4400_0000–0xDFFF_FFFF Reserved – 0xE000_0000–0xE00F_FFFF Private peripherals Cortex-M4 core only 0xE010_0000–0xFFFF_FFFF... -
Page 143: Flash Memory Map
Chapter 4 Memory Map Bit-band region Alias bit-band region Figure 4-1. Alias bit-band mapping NOTE Each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region. 4.3 Flash Memory Map The various flash memories and the flash registers are located at different base addresses as shown in the following figure. -
Page 144: Alternate Non-Volatile Irc User Trim Description
SRAM memory map Flash memory base address Registers Program flash base address Flash configuration field Program flash FlexNVM base address FlexNVM FlexRAM base address FlexRAM Figure 4-2. Flash memory map 4.3.1 Alternate Non-Volatile IRC User Trim Description The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. -
Page 145: Peripheral Bridge (Aips-Lite0 And Aips-Lite1) Memory Maps
Chapter 4 Memory Map 4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps The peripheral memory map is accessible via two slave ports on the crossbar switch in the 0x4000_0000–0x400F_FFFF region. The device implements two peripheral bridges (AIPS-Lite 0 and 1): •... -
Page 146: Freescale Semiconductor, Inc
Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4000_6000 — 0x4000_7000 — 0x4000_8000 DMA controller 0x4000_9000 DMA controller transfer control descriptors 0x4000_A000 — 0x4000_B000 — 0x4000_C000 —... -
Page 147: Freescale Semiconductor, Inc
Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4002_D000 SPI 1 0x4002_E000 — 0x4002_F000 I2S 0 0x4003_0000 — 0x4003_1000 — 0x4003_2000 0x4003_3000 — 0x4003_4000 — 0x4003_5000 — 0x4003_6000 Programmable delay block (PDB) 0x4003_7000 Periodic interrupt timers (PIT) 0x4003_8000... -
Page 148: Freescale Semiconductor, Inc
Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4005_4000 — 0x4005_5000 — 0x4005_6000 — 0x4005_7000 — 0x4005_8000 — 0x4005_9000 — 0x4005_A000 — 0x4005_B000 — 0x4005_C000 — 0x4005_D000 —... -
Page 149: Peripheral Bridge 1 (Aips-Lite 1) Memory Map
Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4007_B000 — 0x4007_C000 Low-leakage wakeup unit (LLWU) 0x4007_D000 Power management controller (PMC) 0x4007_E000 System Mode controller (SMC) 0x4007_F000 Reset Control Module (RCM) 4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map Table 4-3. -
Page 150: Freescale Semiconductor, Inc
Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot Module number 0x4009_A000 — 0x4009_B000 — 0x4009_C000 — 0x4009_D000 — 0x4009_E000 — 0x4009_F000 — 0x400A_0000 — 0x400A_1000 — 0x400A_2000 — 0x400A_3000 —... -
Page 151: Freescale Semiconductor, Inc
Chapter 4 Memory Map Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot Module number 0x400C_1000 — 0x400C_2000 — 0x400C_3000 — 0x400C_4000 — 0x400C_5000 — 0x400C_6000 — 0x400C_7000 — 0x400C_8000 — 0x400C_9000 — 0x400C_A000 — 0x400C_B000 —... -
Page 152: Private Peripheral Bus (Ppb) Memory Map
Private Peripheral Bus (PPB) memory map Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot Module number 0x400E_8000 — 0x400E_9000 — 0x400E_A000 UART 4 0x400E_B000 — 0x400E_C000 — 0x400E_D000 — 0x400E_E000 — 0x400E_F000 — 0x400F_0000 — 0x400F_1000 —... -
Page 153: Freescale Semiconductor, Inc
Chapter 4 Memory Map Table 4-4. PPB memory map (continued) System 32-bit Address Range Resource 0xE000_2000–0xE000_2FFF Flash Patch and Breakpoint (FPB) 0xE000_3000–0xE000_DFFF Reserved 0xE000_E000–0xE000_EFFF System Control Space (SCS) (for NVIC) 0xE000_F000–0xE003_FFFF Reserved 0xE004_0000–0xE004_0FFF Trace Port Interface Unit (TPIU) 0xE004_1000–0xE004_1FFF Reserved 0xE004_2000–0xE004_2FFF Reserved 0xE004_3000–0xE004_3FFF... -
Page 154: Freescale Semiconductor, Inc
Private Peripheral Bus (PPB) memory map K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 155: Clock Distribution
Chapter 5 Clock Distribution 5.1 Introduction The MCG module controls which clock source is used to derive the system clocks. The clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory. The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules. -
Page 156: Clock Definitions
Clock definitions Multiplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers — MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx 4 MHz IRC Clock options for MCGIRCLK some peripherals MCGFFCLK 32 kHz IRC (see note) Core / system clocks OUTDIV1 Bus clock OUTDIV2 MCGOUTCLK Flash clock OUTDIV4 MCGFLLCLK... -
Page 157: Device Clock Summary
Chapter 5 Clock Distribution Clock name Description System clock MCGOUTCLK divided by OUTDIV1 clocks the crossbar switch and bus masters directly connected to the crossbar. In addition, this clock is used for UART0 and UART1. Bus clock MCGOUTCLK divided by OUTDIV2 clocks the bus slaves and peripheral (excluding memories) Flash clock MCGOUTCLK divided by OUTDIV4 clocks the flash memory... -
Page 158: Internal Clocking Requirements
Internal clocking requirements Table 5-1. Clock Summary (continued) Clock name Run mode VLPR mode Clock source Clock is disabled when… clock frequency clock frequency Flash clock Up to 25 MHz Up to 1 MHz MCGOUTCLK clock In all stop modes divider Internal reference 30-40 kHz or 2 MHz... -
Page 159: Clock Divider Values After Reset
Chapter 5 Clock Distribution The following are a few of the more common clock configurations for this device: Option 1: Clock Frequency Core clock 50 MHz System clock 50 MHz Bus clock 50 MHz Flash clock 25 MHz Option 2: Clock Frequency Core clock... -
Page 160: Clock Gating
Clock Gating 5.5.2 VLPR mode clocking The clock dividers cannot be changed while in VLPR mode. They must be programmed prior to entering VLPR mode to guarantee: • the core/system and bus clocks are less than or equal to 4 MHz, and •... -
Page 161: Pmc 1-Khz Lpo Clock
Chapter 5 Clock Distribution Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks Watchdog timer Bus clock — Clocks Bus clock MCGOUTCLK, MCGPLLCLK, — MCGFLLCLK, MCGIRCLK, OSCERCLK, EXTAL32K Bus clock OSCERCLK — Memory and memory interfaces Flash Controller System clock Flash clock... -
Page 162: Wdog Clocking
Module clocks 5.7.1 PMC 1-kHz LPO clock The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all modes of operation, including all low power modes. This 1-kHz source is commonly referred to as LPO clock or 1-kHz LPO clock. 5.7.2 WDOG clocking The WDOG may be clocked from two clock sources as shown in the following figure. -
Page 163: Port Digital Filter Clocking
Chapter 5 Clock Distribution 5.7.4 PORT digital filter clocking The digital filters in each of the PORTx modules can be clocked as shown in the following figure. NOTE In stop mode, the digital input filters are bypassed unless they are configured to run from the 1 kHz LPO clock source. Bus clock PORTx digital input filter clock... -
Page 164: Flexcan Clocking
Module clocks 5.7.6 FlexCAN clocking The clock for the FlexCAN's protocol engine can be selected as shown in the following figure. OSCERCLK FlexCAN clock Bus clock CANx_CTRL1[CLKSRC] Figure 5-6. FlexCAN clock generation 5.7.7 UART clocking UART0 and UART1 modules operate from the core/system clock, which provides higher performance level for these modules. -
Page 165: Tsi Clocking
Chapter 5 Clock Distribution The MCLK and BCLK source options appear in the following figure. I2S/SAI Clock Generation MCLK_OUT I2Sx_TCR2/RCR2 BCLK_OUT MCGPLLCLK Fractional Clock OSC0ERCLK MCLK Clock Divider SYSCLK BCLK MCLK_IN BUSCLK Divider BCLK_IN [MSEL] [DIV] [BCD] I2Sx_MCR[MOE] I2Sx_MDR[FRACT,DIVIDE] I2Sx_MCR[MICS] Figure 5-7. -
Page 166: Freescale Semiconductor, Inc
Module clocks TSI clock in low-power mode ERCLK32K TSI_GENCS[LPCLKS] Figure 5-9. TSI low-power clock generation K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 167: Reset And Boot
Chapter 6 Reset and Boot 6.1 Introduction The following reset sources are supported in this MCU: Table 6-1. Reset sources Reset sources Description POR reset • Power-on reset (POR) System resets • External pin reset (PIN) • Low-voltage detect (LVD) •... -
Page 168: Reset
Reset 6.2 Reset This section discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (V ), the POR circuit causes a POR reset condition. -
Page 169: Freescale Semiconductor, Inc
Chapter 6 Reset and Boot Note that the nTRST signal is initially configured as disabled, however once configured to its JTAG functionality its associated input pin is configured as: • nTRST in PU 6.2.2.1 External pin reset (PIN) On this device, RESET is a dedicated pin. This pin is open drain and has an internal pullup device. -
Page 170: Freescale Semiconductor, Inc
Reset 6.2.2.2 Low-voltage detect (LVD) The chip includes a system for managing low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip voltage. -
Page 171: Freescale Semiconductor, Inc
Chapter 6 Reset and Boot 6.2.2.5 Multipurpose clock generator loss-of-clock (LOC) The MCG module supports an external reference clock. If the C6[CME] bit in the MCG module is set, the clock monitor is enabled. If the external reference falls below f or f , as controlled by the C2[RANGE] field loc_low... -
Page 172: Mcu Resets
Reset 6.2.2.9 Lockup reset (LOCKUP) The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor’s built in system state protection hardware. The LOCKUP condition causes a system reset and also causes the RCM's SRS1[LOCKUP] bit to set. -
Page 173: Freescale Semiconductor, Inc
Chapter 6 Reset and Boot 6.2.3.2 POR Only The POR Only reset asserts on the POR reset source only. It resets the PMC and System Register File. The POR Only reset also causes all other reset types (except VBAT POR) to occur. 6.2.3.3 Chip POR not VLLS The Chip POR not VLLS reset asserts on POR and LVD reset sources. -
Page 174: Reset Pin
Reset 6.2.3.7 Chip Reset Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET pin has also negated. It resets the remaining modules (the modules not reset by other reset types). 6.2.4 Reset Pin For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash initialization has completed. -
Page 175: Boot
Chapter 6 Reset and Boot 6.2.5.3 Resetting the Debug subsystem Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug modules. However, as explained below, using the CDBGRSTREQ bit does not reset all debug-related registers. CDBGRSTREQ resets the debug-related registers within the following modules: •... -
Page 176: Fopt Boot Options
Boot The device can be in single chip (default) or serial flash programming mode (EzPort). While in single chip mode the device can be in run or various low power modes mentioned in Power mode transitions. Table 6-2. Mode select decoding EzPort chip select (EZP_CS) Description Serial flash programming mode (EzPort) -
Page 177: Boot Sequence
Chapter 6 Reset and Boot Table 6-3. Flash Option Register (FTFL_FOPT) Bit Definitions (continued) Field Value Definition LPBOOT Low-power boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at reset exit for higher divide values that produce lower power consumption at reset exit. -
Page 178: Freescale Semiconductor, Inc
Boot 7. When the system exits reset, the processor sets up the stack, program counter (PC), and link register (LR). The processor reads the start SP (SP_main) from vector-table offset 0. The core reads the start PC from vector-table offset 4. LR is set to 0xFFFF_FFFF. -
Page 179: Power Management
Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Power modes The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed. Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention, partial power down or full power down of certain logic and/or memory. -
Page 180: Freescale Semiconductor, Inc
Power modes Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method Normal Wait - Allows peripherals to function while the core is in sleep mode, reducing Sleep Interrupt via WFI power. NVIC remains sensitive to interrupts; peripherals continue to be clocked. -
Page 181: Entering And Exiting Power Modes
Chapter 7 Power Management Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method BAT (backup The chip is powered down except for the VBAT supply. The RTC and Power-up battery only) the 32-byte VBAT register file for customer-critical data remain Sequence powered. -
Page 182: Power Mode Transitions
Power mode transitions 7.4 Power mode transitions The following figure shows the power mode transitions. Any reset always brings the chip back to the normal run state. In run, wait, and stop modes active power regulation is enabled. The VLPx modes are limited in frequency, but offer a lower power operating mode than normal modes. -
Page 183: Power Modes Shutdown Sequencing
Chapter 7 Power Management 7.5 Power modes shutdown sequencing When entering stop or other low-power modes, the clocks are shut off in an orderly sequence to safely place the chip in the targeted low-power state. All low-power entry sequences are initiated by the core executing an WFI instruction. The ARM core's outputs, SLEEPDEEP and SLEEPING, trigger entry to the various low-power modes: •... -
Page 184: Freescale Semiconductor, Inc
Module Operation in Low Power Modes • powered = Memory is powered to retain contents. • low power = Flash has a low power state that retains configuration registers to support faster wakeup. • OFF = Modules are powered off; module is in reset state upon wakeup. •... -
Page 185: Freescale Semiconductor, Inc
Chapter 7 Power Management Table 7-2. Module operation in low power modes (continued) Modules Stop VLPR VLPW VLPS VLLSx Communication interfaces UART static, wakeup 125 kbps 125 kbps static, wakeup static on edge on edge static 1 Mbps 1 Mbps static static static, address... -
Page 186: Clock Gating
Clock Gating 9. TSI wakeup from LLS and VLLSx modes is limited to a single selectable pin. 7.7 Clock Gating To conserve power, the clocks to most modules can be turned off using the SCGCx registers in the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module. -
Page 187: Security
Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits. -
Page 188: Security Interactions With Other Modules
Security Interactions with other Modules 8.3 Security Interactions with other Modules The flash security settings are used by the SoC to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. 8.3.1 Security Interactions with EzPort When flash security is active the MCU can still boot in EzPort mode. -
Page 189: Introduction
Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM coresight architecture and is configured in each device to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. Four debug interfaces are supported: •... -
Page 190: Freescale Semiconductor, Inc
Introduction Cortex-M4 INTNMI Interrupts Sleep INTISR[239:0] NVIC Core SLEEPING Debug Trigger SLEEPDEEP Instr. Data Trace port (serial wire or multi-pin) TPIU AWIC Private Peripheral Bus (internal) Table I-code bus Code bus D-code bus Matrix System bus SWJ-DP AHB-AP JTAG MDM-AP Figure 9-1. -
Page 191: References
Chapter 9 Debug Table 9-1. Debug Components Description (continued) Module Description FPB (Flash Patch and Breakpoints) The FPB implements hardware breakpoints and patches code and data from code space to system space. The FPB unit contains two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space. -
Page 192: Jtag-To-Swd Change Sequence
The Debug Port IR==BYPASS or IDC ODE 4’b1111 or 4’b0000 jtag_updateinstr[3:0] To Test J TAGC Resources nTRST TC K TRACES WO (1’b1 = 4-pin J TAG) CJ TAG (1’b0 = 2-pin cJ TAG) TDI TDO PEN nSYS_TDO nSYS_TDI 1’b1 nTRST nSYS_TRST S WCLKTCK TC K... -
Page 193: Debug Port Pin Descriptions
Chapter 9 Debug 2. Set the control level to 2 via zero-bit scans 3. Execute the Store Format (STFMT) command (00011) to set the scan format register to 1149.7 scan format 9.3 Debug Port Pin Descriptions The debug port pins default after POR to their JTAG functionality with the exception of JTAG_TRST_b and can be later reassigned to their alternate functionalities. -
Page 194: Ir Codes
JTAG status and control registers 9.4.1 IR Codes Table 9-3. JTAG Instructions Instruction Code[3:0] Instruction Summary IDCODE 0000 Selects device identification register for shift SAMPLE/PRELOAD 0010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation SAMPLE 0011 Selects boundary scan register for shifting and sampling without disturbing functional operation... -
Page 195: Mdm-Ap Control Register
Chapter 9 Debug Table 9-4. MDM-AP Register Summary (continued) MDM-AP Status Register 0x0100_0000 Status 0x0100_0004 Control MDM-AP Control Register 0x0100_00FC Read-only identification register that always reads as 0x001C_0000 DPACC APACC Data[31:0] A[3:2] RnW Data[31:0] A[3:2] RnW SWJ-DP See the ARM Debug Interface v5p1 Supplement. Generic Debug Port (DP) -
Page 196: Freescale Semiconductor, Inc
JTAG status and control registers 9.5.1 MDM-AP Control Register Table 9-5. MDM-AP Control register assignments Name Secure Description Flash Mass Erase in Progress Set to cause mass erase. Cleared by hardware after mass erase operation completes. When mass erase is disabled (via MEEN and SEC settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset. -
Page 197: Mdm-Ap Status Register
Chapter 9 Debug Table 9-5. MDM-AP Control register assignments (continued) Name Secure Description LLS, VLLSx Status Acknowledge Set this bit to acknowledge the DAP LLS and VLLS Status bits have been read. This acknowledge automatically clears the status bits. This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. -
Page 198: Debug Resets
Debug Resets Table 9-6. MDM-AP Status register assignments (continued) Name Description Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled. 0 Disabled 1 Enabled LP Enabled Decode of LPLLSM control bits to indicate that VLPS, LLS, or VLLSx are the selected power mode the next time the ARM Core enters Deep Sleep. -
Page 199: Ahb-Ap
Chapter 9 Debug • JTAG_TRST_b from an external signal. This signal is optional and may not be available in all packages. • Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the TCLK domain that allows the debugger to reset the debug logic. •... -
Page 200: Itm
9.8 ITM The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can generate packets. -
Page 201: Debug In Low Power Modes
Chapter 9 Debug • It contains four comparators that you can configure as a hardware watchpoint, a PC sampler event trigger, or a data address sampler event trigger. The first comparator, DWT_COMP0, can also compare against the clock cycle counter, CYCCNT. The second comparator, DWT_COMP1, can also be used as a data comparator. -
Page 202: Debug Module State In Low Power Modes
Debug & Security NOTE When using cJTAG and entering LLS mode, the cJTAG controller must be reset on exit from LLS mode. Going into a VLLSx mode causes all the debug controls and settings to be reset. To give time to the debugger to sync up with the HW, the MDM-AP Control register can be configured hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation. -
Page 203: Signal Multiplexing And Signal Descriptions
Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin. -
Page 204: Port Control And Interrupt Module Features
Signal Multiplexing Integration Table 10-1. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Register access Peripheral bus Peripheral bridge controller 10.2.1 Port control and interrupt module features • Five 32-pin ports NOTE Not all pins are available on the device. See the following section for details. -
Page 205: Pinout
Chapter 10 Signal Multiplexing and Signal Descriptions 10.2.4 Signal multiplexing constraints 1. A given peripheral function must be assigned to a maximum of one package pin. Do not program the same function to more than one pin. 2. To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other. -
Page 206: Freescale Semiconductor, Inc
Pinout Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP ADC0_DP1 ADC0_DP1 ADC0_DP1 ADC0_DM1 ADC0_DM1 ADC0_DM1 ADC1_DP1 ADC1_DP1 ADC1_DP1 ADC1_DM1 ADC1_DM1 ADC1_DM1 PGA0_DP/ PGA0_DP/ PGA0_DP/ ADC0_DP0/ ADC0_DP0/ ADC0_DP0/ ADC1_DP3 ADC1_DP3 ADC1_DP3 PGA0_DM/ PGA0_DM/ PGA0_DM/ ADC0_DM0/ ADC0_DM0/ ADC0_DM0/ ADC1_DM3 ADC1_DM3... -
Page 207: Freescale Semiconductor, Inc
Chapter 10 Signal Multiplexing and Signal Descriptions Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP PTA4/ NMI_b/ TSI0_CH5 PTA4/ FTM0_CH1 NMI_b EZP_CS_b LLWU_P3 EZP_CS_b LLWU_P3 PTA5 DISABLED PTA5 FTM0_CH2 CMP2_OUT I2S0_TX_ JTAG_TRST_ BCLK PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX... -
Page 208: Freescale Semiconductor, Inc
Pinout Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP PTB11 LCD_P11/ LCD_P11/ PTB11 SPI1_SCK UART3_TX FTM0_FLT2 LCD_P11 ADC1_SE15 ADC1_SE15 PTB16 LCD_P12/ LCD_P12/ PTB16 SPI1_SOUT UART0_RX EWM_IN LCD_P12 TSI0_CH9 TSI0_CH9 PTB17 LCD_P13/ LCD_P13/ PTB17 SPI1_SIN UART0_TX EWM_OUT_b LCD_P13 TSI0_CH10... -
Page 209: Freescale Semiconductor, Inc
Chapter 10 Signal Multiplexing and Signal Descriptions Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP PTC10 LCD_P30/ LCD_P30/ PTC10 I2C1_SCL I2S0_RX_FS LCD_P30 ADC1_SE6b ADC1_SE6b PTC11/ LCD_P31/ LCD_P31/ PTC11/ I2C1_SDA I2S0_RXD1 LCD_P31 LLWU_P11 ADC1_SE7b ADC1_SE7b LLWU_P11 —... -
Page 210: K30 Pinouts
Pinout Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort LQFP — — — — — 10.3.2 K30 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. -
Page 211: Freescale Semiconductor, Inc
Chapter 10 Signal Multiplexing and Signal Descriptions PTE0 VLL3 PTE1/LLWU_P0 PTE2/LLWU_P1 PTC3/LLWU_P7 PTE3 PTC2 PTE4/LLWU_P2 PTC1/LLWU_P6 PTE5 PTC0 PTE6 PTB23 PTB22 PTB21 PTE16 PTB20 PTE17 PTB19 PTE18 PTB18 PTE19 PTB17 ADC0_DP1 PTB16 PTB11 ADC0_DM1 PTB10 ADC1_DP1 PTB9 ADC1_DM1 PTB8 PGA0_DP/ADC0_DP0/ADC1_DP3 PTB7 PGA0_DM/ADC0_DM0/ADC1_DM3 PTB3... -
Page 212: Module Signal Description Tables
Module Signal Description Tables PTD4/ PTC4/ PTD7 PTD5 PTC19 PTC14 PTC13 PTC8 VLL1 VLL2 VLL3 LLWU_P14 LLWU_P8 PTD6/ PTC3/ PTD3 PTC18 PTC12 PTC7 PTC0 PTB16 VCAP2 LLWU_P15 LLWU_P7 PTD2/ PTC11/ PTC6/ PTC17 PTC10 PTC2 PTB19 PTB11 VCAP1 LLWU_P13 LLWU_P11 LLWU_P10 PTD0/ PTC5/ PTC1/... -
Page 213: Core Modules
Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.1 Core Modules Table 10-2. JTAG Signal Descriptions Chip signal name Module signal Description name JTAG_TMS JTAG_TMS/ JTAG Test Mode Selection SWD_DIO JTAG_TCLK JTAG_TCLK/ JTAG Test Clock SWD_CLK JTAG_TDI JTAG_TDI JTAG Test Data Input JTAG_TDO JTAG_TDO/ JTAG Test Data Output... -
Page 214: System Modules
Module Signal Description Tables 10.4.2 System Modules Table 10-5. System Signal Descriptions Chip signal name Module signal Description name — Non-maskable interrupt NOTE: Driving the NMI signal low forces a non-maskable interrupt, if the NMI function is selected on the corresponding pin. -
Page 215: Memories And Memory Interfaces
Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.4 Memories and Memory Interfaces Table 10-9. EzPort Signal Descriptions Chip signal name Module signal Description name EZP_CLK EZP_CK EzPort Clock Input EZP_CS EZP_CS EzPort Chip Select Input EZP_DI EZP_D EzPort Serial Data In Input EZP_DO EZP_Q... -
Page 216: Freescale Semiconductor, Inc
Module Signal Description Tables Table 10-11. ADC 1 Signal Descriptions (continued) Chip signal name Module signal Description name VSSA Analog Ground Table 10-12. CMP 0 Signal Descriptions Chip signal name Module signal Description name CMP0_IN[5:0] IN[5:0] Analog voltage inputs CMP0_OUT CMPO Comparator output Table 10-13. -
Page 217: Timer Modules
Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.6 Timer Modules Table 10-17. FTM 0 Signal Descriptions Chip signal name Module signal Description name FTM_CLKIN[1:0] EXTCLK External clock. FTM external clock can be selected to drive the FTM counter. FTM0_CH[7:0] FTM channel (n), where n can be 7-0 FTM0_FLT[3:0] FAULTj Fault input (j), where j can be 3-0... -
Page 218: Communication Interfaces
Module Signal Description Tables Table 10-21. PDB 0 Signal Descriptions Chip signal name Module signal Description name PDB0_EXTRG EXTRG External Trigger Input Source If the PDB is enabled and external trigger input source is selected, a positive edge on the EXTRG signal resets and starts the counter. Table 10-22. -
Page 219: Freescale Semiconductor, Inc
Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-26. SPI 1 Signal Descriptions Chip signal name Module signal Description name SPI1_PCS0 PCS0/SS Peripheral Chip Select 0 output SPI1_PCS[3:1] PCS[3:1] Peripheral Chip Select 1 – 3 SPI1_SIN Serial Data In SPI1_SOUT SOUT Serial Data Out SPI1_SCK... -
Page 220: Freescale Semiconductor, Inc
Module Signal Description Tables Table 10-31. UART 2 Signal Descriptions Chip signal name Module signal Description name UART2_CTS Clear to send UART2_RTS Request to send UART2_TX Transmit data UART2_RX Receive data Table 10-32. UART 3 Signal Descriptions Chip signal name Module signal Description name... -
Page 221: Human-Machine Interfaces (Hmi)
Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.8 Human-Machine Interfaces (HMI) Table 10-35. GPIO Signal Descriptions Chip signal name Module signal Description name PTA[31:0] PORTA31–PORTA0 General-purpose input/output PTB[31:0] PORTB31–PORTB0 General-purpose input/output PTC[31:0] PORTC31–PORTC0 General-purpose input/output PTD[31:0] PORTD31–PORTD0 General-purpose input/output PTE[31:0] PORTE31–PORTE0 General-purpose input/output 1. -
Page 222: Freescale Semiconductor, Inc
Module Signal Description Tables K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 223: Port Control And Interrupts (Port)
Chapter 11 Port control and interrupts (PORT) 11.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 11.1.1 Overview The port control and interrupt (PORT) module provides support for port control, and external interrupt functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state. -
Page 224: External Signal Description
Introduction • Individual drive strength field supporting high and low drive strength on selected pins • Individual slew rate field supporting fast and slow slew rates on selected pins • Individual input passive filter field supporting enable and disable of the individual input passive filter on selected pins •... -
Page 225: Detailed Signal Description
Chapter 11 Port control and interrupts (PORT) NOTE Not all pins within each port are implemented on each device. 11.1.3 Detailed signal description The following table contains the detailed signal description for the PORT interface. Table 11-2. PORT interface—detailed signal description Signal Description PORTx[31:0]... -
Page 226: Freescale Semiconductor, Inc
Introduction PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_9034 Pin Control Register n (PORTA_PCR13) See section 11.14.1/231 4004_9038 Pin Control Register n (PORTA_PCR14) See section 11.14.1/231 4004_903C Pin Control Register n (PORTA_PCR15) See section 11.14.1/231 4004_9040... -
Page 227: Freescale Semiconductor, Inc
Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_A034 Pin Control Register n (PORTB_PCR13) See section 11.14.1/231 4004_A038 Pin Control Register n (PORTB_PCR14) See section 11.14.1/231 4004_A03C Pin Control Register n (PORTB_PCR15) See section... -
Page 228: Freescale Semiconductor, Inc
Introduction PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_B034 Pin Control Register n (PORTC_PCR13) See section 11.14.1/231 4004_B038 Pin Control Register n (PORTC_PCR14) See section 11.14.1/231 4004_B03C Pin Control Register n (PORTC_PCR15) See section 11.14.1/231 4004_B040... -
Page 229: Freescale Semiconductor, Inc
Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_C034 Pin Control Register n (PORTD_PCR13) See section 11.14.1/231 4004_C038 Pin Control Register n (PORTD_PCR14) See section 11.14.1/231 4004_C03C Pin Control Register n (PORTD_PCR15) See section... -
Page 230: Freescale Semiconductor, Inc
Introduction PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_D034 Pin Control Register n (PORTE_PCR13) See section 11.14.1/231 4004_D038 Pin Control Register n (PORTE_PCR14) See section 11.14.1/231 4004_D03C Pin Control Register n (PORTE_PCR15) See section 11.14.1/231 4004_D040 Pin Control Register n (PORTE_PCR16) -
Page 231: Freescale Semiconductor, Inc
Chapter 11 Port control and interrupts (PORT) 11.14.1 Pin Control Register n (PORTx_PCRn) Address: Base address + 0h offset + (4d × i), where i=0d to 31d IRQC Reset Reset * Notes: • Refer to the Signal Multiplexing and Signal Descriptions chapter for the reset value of this device.x = Undefined at reset. PORTx_PCRn field descriptions Field Description... -
Page 232: Freescale Semiconductor, Inc
Introduction PORTx_PCRn field descriptions (continued) Field Description 1100 Interrupt when logic one. Others Reserved. Lock Register Pin Control Register fields [15:0] are not locked. Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. 14–11 This field is reserved. -
Page 233: Freescale Semiconductor, Inc
Chapter 11 Port control and interrupts (PORT) PORTx_PCRn field descriptions (continued) Field Description Slew Rate Enable This bit is read only for pins that do not support a configurable slew rate. Slew rate configuration is valid in all digital pin muxing modes. Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. -
Page 234: Freescale Semiconductor, Inc
Introduction 11.14.3 Global Pin Control High Register (PORTx_GPCHR) Only 32-bit writes are supported to this register. Address: Base address + 84h offset GPWE GPWD Reset PORTx_GPCHR field descriptions Field Description 31–16 Global Pin Write Enable GPWE Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD. If a selected Pin Control Register is locked then the write to that register is ignored. -
Page 235: Functional Description
Chapter 11 Port control and interrupts (PORT) PORTx_ISFR field descriptions (continued) Field Description Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. -
Page 236: Freescale Semiconductor, Inc
Introduction The configuration of each pin control register is retained when the PORT module is disabled. 11.1.5.2 Global pin control The two global pin control registers allow a single register write to update the lower half of the pin control register on up to sixteen pins, all with the same value. Registers that are locked cannot be written using the global pin control registers. -
Page 237: Freescale Semiconductor, Inc
Chapter 11 Port control and interrupts (PORT) The PORT module generates a single DMA request that asserts when the interrupt status flag is set for any enabled DMA request in that port. The DMA request negates after the DMA transfer is completed, because that clears the interrupt status flags for all enabled DMA requests. -
Page 238: Freescale Semiconductor, Inc
Introduction K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 239: System Integration Module (Sim)
Chapter 12 System Integration Module (SIM) 12.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The System Integration Module (SIM) provides system control and chip configuration registers. 12.1.1 Features Features of the SIM include: •... -
Page 240: Memory Map And Register Definition
Memory map and register definition 12.2 Memory map and register definition The SIM module contains many fields for selecting the clock source and dividers for various module clocks. See the Clock Distribution chapter for more information, including block diagrams and clock definitions. NOTE The SIM_SOPT1 and SIM_SOPT1CFG registers are located at a different base address than the other SIM registers. -
Page 241: System Options Register 1 (Sim_Sopt1)
Chapter 12 System Integration Module (SIM) 12.2.1 System Options Register 1 (SIM_SOPT1) NOTE The SOPT1 register is only reset on POR or LVD. Address: 4004_7000h base + 0h offset = 4004_7000h OSC32KSEL Reset RAMSIZE Reserved Reset * Notes: • Reset value loaded during System Reset from Flash IFR. SIM_SOPT1 field descriptions Field Description... -
Page 242: System Options Register 2 (Sim_Sopt2)
Memory map and register definition SIM_SOPT1 field descriptions (continued) Field Description 0100 Undefined 0101 32 KBytes 0110 Undefined 0111 64 KBytes 1000 Undefined 1001 Undefined 1010 Undefined 1011 Undefined 1100 Undefined 1101 Undefined 1110 Undefined 1111 Undefined 11–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. -
Page 243: Freescale Semiconductor, Inc
Chapter 12 System Integration Module (SIM) SIM_SOPT2 field descriptions Field Description 31–30 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 29–28 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 27–22 This field is reserved. -
Page 244: System Options Register 4 (Sim_Sopt4)
Memory map and register definition SIM_SOPT2 field descriptions (continued) Field Description RTC clock out select RTCCLKOUTSEL Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the RTC_CLKOUT pin. RTC 1 Hz clock is output on the RTC_CLKOUT pin. RTC 32.768kHz clock is output on the RTC_CLKOUT pin. -
Page 245: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Chapter 12 System Integration Module (SIM) SIM_SOPT4 field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. FlexTimer 2 External Clock Pin Select FTM2CLKSEL Selects the external pin used to drive the clock to the FTM2 module. NOTE: The selected pin must also be configured for the FTM2 module external clock function through the appropriate pin control register in the port control module. -
Page 246: Freescale Semiconductor, Inc
Memory map and register definition SIM_SOPT4 field descriptions (continued) Field Description FTM2 Fault 0 Select FTM2FLT0 Selects the source of FTM2 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate PORTx pin control register. -
Page 247: System Options Register 5 (Sim_Sopt5)
Chapter 12 System Integration Module (SIM) 12.2.4 System Options Register 5 (SIM_SOPT5) Address: 4004_7000h base + 1010h offset = 4004_8010h Reset UART1RXSR UART1TXSR UART0RXSR UART0TXSR Reset SIM_SOPT5 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 7–6 UART 1 receive data source select UART1RXSRC... -
Page 248: System Options Register 7 (Sim_Sopt7)
Memory map and register definition 12.2.5 System Options Register 7 (SIM_SOPT7) Address: 4004_7000h base + 1018h offset = 4004_8018h Reset ADC1TRGSEL ADC0TRGSEL Reset SIM_SOPT7 field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. ADC1 alternate trigger enable ADC1ALTTRGEN Enable alternative conversion triggers for ADC1. -
Page 249: Freescale Semiconductor, Inc
Chapter 12 System Integration Module (SIM) SIM_SOPT7 field descriptions (continued) Field Description 0110 PIT trigger 2 0111 PIT trigger 3 1000 FTM0 trigger 1001 FTM1 trigger 1010 FTM2 trigger 1011 Unused 1100 RTC alarm 1101 RTC seconds 1110 Low-power timer trigger 1111 Unused ADC0 alternate trigger enable... -
Page 250: System Device Identification Register (Sim_Sdid)
Memory map and register definition 12.2.6 System Device Identification Register (SIM_SDID) Address: 4004_7000h base + 1024h offset = 4004_8024h Reset REVID FAMID PINID Reset * Notes: • x = Undefined at reset. SIM_SDID field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. -
Page 251: System Clock Gating Control Register 1 (Sim_Scgc1)
Chapter 12 System Integration Module (SIM) SIM_SDID field descriptions (continued) Field Description 3–0 Pincount identification PINID Specifies the pincount of the device. 0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 64-pin 0110 80-pin 0111 81-pin 1000 100-pin 1001 Reserved 1010... -
Page 252: System Clock Gating Control Register 2 (Sim_Scgc2)
Memory map and register definition SIM_SCGC1 field descriptions (continued) Field Description 23–22 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. 20–12 This field is reserved. -
Page 253: System Clock Gating Control Register 3 (Sim_Scgc3)
Chapter 12 System Integration Module (SIM) SIM_SCGC2 field descriptions Field Description 31–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. DAC0 Clock Gate Control DAC0 This bit controls the clock gate to the DAC0 module. -
Page 254: Freescale Semiconductor, Inc
Memory map and register definition SIM_SCGC3 field descriptions (continued) Field Description ADC1 Clock Gate Control ADC1 This bit controls the clock gate to the ADC1 module. Clock disabled Clock enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. -
Page 255: System Clock Gating Control Register 4 (Sim_Scgc4)
Chapter 12 System Integration Module (SIM) 12.2.10 System Clock Gating Control Register 4 (SIM_SCGC4) Address: 4004_7000h base + 1034h offset = 4004_8034h VREF CMP Reset I2C1 I2C0 CMT EWM Reset SIM_SCGC4 field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 1. -
Page 256: Freescale Semiconductor, Inc
Memory map and register definition SIM_SCGC4 field descriptions (continued) Field Description Clock disabled Clock enabled UART1 Clock Gate Control UART1 This bit controls the clock gate to the UART1 module. Clock disabled Clock enabled UART0 Clock Gate Control UART0 This bit controls the clock gate to the UART0 module. Clock disabled Clock enabled 9–8... -
Page 257: System Clock Gating Control Register 5 (Sim_Scgc5)
Chapter 12 System Integration Module (SIM) 12.2.11 System Clock Gating Control Register 5 (SIM_SCGC5) Address: 4004_7000h base + 1038h offset = 4004_8038h Reset Reset SIM_SCGC5 field descriptions Field Description 31–19 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. -
Page 258: Freescale Semiconductor, Inc
Memory map and register definition SIM_SCGC5 field descriptions (continued) Field Description Clock disabled Clock enabled Port A Clock Gate Control PORTA This bit controls the clock gate to the Port A module. Clock disabled Clock enabled 8–7 This field is reserved. Reserved This read-only field is reserved and always has the value 1. -
Page 259: System Clock Gating Control Register 6 (Sim_Scgc6)
Chapter 12 System Integration Module (SIM) 12.2.12 System Clock Gating Control Register 6 (SIM_SCGC6) Address: 4004_7000h base + 103Ch offset = 4004_803Ch Reset SPI1 SPI0 FTFL Reset SIM_SCGC6 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. -
Page 260: Freescale Semiconductor, Inc
Memory map and register definition SIM_SCGC6 field descriptions (continued) Field Description Clock disabled Clock enabled PIT Clock Gate Control This bit controls the clock gate to the PIT module. Clock disabled Clock enabled PDB Clock Gate Control This bit controls the clock gate to the PDB module. Clock disabled Clock enabled This field is reserved. -
Page 261: System Clock Gating Control Register 7 (Sim_Scgc7)
Chapter 12 System Integration Module (SIM) SIM_SCGC6 field descriptions (continued) Field Description 8–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. FlexCAN0 Clock Gate Control FLEXCAN0 This bit controls the clock gate to the FlexCAN0 module. Clock disabled Clock enabled 3–2... -
Page 262: System Clock Divider Register 1 (Sim_Clkdiv1)
Memory map and register definition SIM_SCGC7 field descriptions (continued) Field Description Clock disabled Clock enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. 12.2.14 System Clock Divider Register 1 (SIM_CLKDIV1) NOTE The CLKDIV1 register cannot be written to when the device is in VLPR mode. -
Page 263: Freescale Semiconductor, Inc
Chapter 12 System Integration Module (SIM) SIM_CLKDIV1 field descriptions Field Description 31–28 Clock 1 output divider value OUTDIV1 This field sets the divide value for the core/system clock. At the end of reset, it is loaded with either 0000 or 0111 depending on FTFL_FOPT[LPBOOT]. 0000 Divide-by-1. -
Page 264: System Clock Divider Register 2 (Sim_Clkdiv2)
Memory map and register definition SIM_CLKDIV1 field descriptions (continued) Field Description 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. -
Page 265: Flash Configuration Register 1 (Sim_Fcfg1)
Chapter 12 System Integration Module (SIM) 12.2.16 Flash Configuration Register 1 (SIM_FCFG1) The reset value of EESIZE and DEPART are based on user programming in user IFR via the PGMPART flash command. Address: 4004_7000h base + 104Ch offset = 4004_804Ch NVMSIZE PFSIZE EESIZE... -
Page 266: Freescale Semiconductor, Inc
Memory map and register definition SIM_FCFG1 field descriptions (continued) Field Description This field specifies the amount of program flash memory available on the device . Undefined values are reserved. 0101 64 KB of program flash memory, 2 KB protection region 0111 128 KB of program flash, 4 KB protection region 1001... -
Page 267: Flash Configuration Register 2 (Sim_Fcfg2)
Chapter 12 System Integration Module (SIM) 12.2.17 Flash Configuration Register 2 (SIM_FCFG2) Address: 4004_7000h base + 1050h offset = 4004_8050h MAXADDR0 MAXADDR1 Reset Reset * Notes: • Reset value loaded during System Reset from Flash IFR. SIM_FCFG2 field descriptions Field Description This field is reserved. -
Page 268: Unique Identification Register High (Sim_Uidh)
Memory map and register definition SIM_FCFG2 field descriptions (continued) Field Description This field concatenated with leading zeros plus the FlexNVM base address indicates the first invalid address of the FlexNVM (flash block 1). For example, if MAXADDR1 = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value for a device with 256 KB FlexNVM. -
Page 269: Unique Identification Register Mid Low (Sim_Uidml)
Chapter 12 System Integration Module (SIM) 12.2.20 Unique Identification Register Mid Low (SIM_UIDML) Address: 4004_7000h base + 105Ch offset = 4004_805Ch 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: •... -
Page 270: Freescale Semiconductor, Inc
Functional description K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 271: Introduction
Chapter 13 Reset Control Module (RCM) 13.1 Introduction This chapter describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. 13.2 Reset memory map and register descriptions The Reset Control Module (RCM) registers provide reset status information and reset filter control. -
Page 272: Freescale Semiconductor, Inc
Reset memory map and register descriptions • LVD (without POR) — 0x02 • VLLS mode wakeup due to RESET pin assertion — 0x41 • VLLS mode wakeup due to other wakeup sources — 0x01 • Other reset — a bit is set if its corresponding reset source caused the reset Address: 4007_F000h base + 0h offset = 4007_F000h Read... -
Page 273: System Reset Status Register 1 (Rcm_Srs1)
Chapter 13 Reset Control Module (RCM) RCM_SRS0 field descriptions (continued) Field Description Reset not caused by a loss of external clock. Reset caused by a loss of external clock. Low-Voltage Detect Reset If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is also set by POR. -
Page 274: Reset Pin Filter Control Register (Rcm_Rpfc)
Reset memory map and register descriptions RCM_SRS1 field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Stop Mode Acknowledge Error Reset SACKERR Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more peripherals to acknowledge within approximately one second to enter stop mode. -
Page 275: Reset Pin Filter Width Register (Rcm_Rpfw)
Chapter 13 Reset Control Module (RCM) NOTE The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled or when entering any low leakage stop mode . Address: 4007_F000h base + 4h offset = 4007_F004h Read RSTFLTSS RSTFLTSRW... -
Page 276: Freescale Semiconductor, Inc
Reset memory map and register descriptions RCM_RPFW field descriptions Field Description 7–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 4–0 Reset Pin Filter Bus Clock Select RSTFLTSEL Selects the reset pin bus clock filter width. 00000 Bus clock filter count is 1 00001... -
Page 277: Mode Register (Rcm_Mr)
Chapter 13 Reset Control Module (RCM) 13.2.5 Mode Register (RCM_MR) This register includes read-only status flags to indicate the state of the mode pins during the last Chip Reset. Address: 4007_F000h base + 7h offset = 4007_F007h Read EZP_MS Write Reset RCM_MR field descriptions Field... -
Page 278: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Reset memory map and register descriptions K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 279: Introduction
Chapter 14 System Mode Controller 14.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The system mode controller (SMC) is responsible for sequencing the system into and out of all low power stop and run modes. Specifically, it monitors events to trigger transitions between power modes while controlling the power, clocks, and memories of the system to achieve the power consumption and functionality of that mode. -
Page 280: Freescale Semiconductor, Inc
Modes of operation ARM CPU mode MCU mode Sleep Wait Deep Sleep Stop Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the Freescale MCU documentation normally uses wait and stop. In addition, Freescale MCUs also augment stop, wait, and run modes in a number of ways. -
Page 281: Memory Map And Register Descriptions
Chapter 14 System Mode Controller Table 14-1. Power modes (continued) Mode Description VLLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic. -
Page 282: Freescale Semiconductor, Inc
Memory map and register descriptions If the MCU is configured for a disallowed or reserved power mode, the MCU remains in its current power mode. For example, if the MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and the RUNM bits remain 00b, indicating the MCU is still in Normal Run mode. -
Page 283: Power Mode Control Register (Smc_Pmctrl)
Chapter 14 System Mode Controller 14.3.2 Power Mode Control register (SMC_PMCTRL) The PMCTRL register controls entry into low-power run and stop modes, provided that the selected power mode is allowed via an appropriate setting of the protection (PMPROT) register. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. -
Page 284: Vlls Control Register (Smc_Vllsctrl)
Memory map and register descriptions SMC_PMCTRL field descriptions (continued) Field Description 2–0 Stop Mode Control STOPM When written, controls entry into the selected stop mode when Sleep-Now or Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. -
Page 285: Power Mode Status Register (Smc_Pmstat)
Chapter 14 System Mode Controller SMC_VLLSCTRL field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 2–0 VLLS Mode Control VLLSM Controls which VLLS sub-mode to enter if STOPM=VLLS. Reserved VLLS1 VLLS2... -
Page 286: Functional Description
Functional description SMC_PMSTAT field descriptions (continued) Field Description 001_0000 Current power mode is VLPS 010_0000 Current power mode is LLS 100_0000 Current power mode is VLLS 14.4 Functional description 14.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal run state. -
Page 287: Freescale Semiconductor, Inc
Chapter 14 System Mode Controller Figure 14-5. Power mode state diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 14-7. Power mode transition triggers Transition # From Trigger conditions WAIT Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. -
Page 288: Freescale Semiconductor, Inc
Functional description Table 14-7. Power mode transition triggers (continued) Transition # From Trigger conditions STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note. STOP Interrupt or Reset VLPR Reduce system, bus and core frequency to 2 MHz or less, Flash access limited to 1 MHz. -
Page 289: Power Mode Entry/Exit Sequencing
Chapter 14 System Mode Controller Table 14-7. Power mode transition triggers (continued) Transition # From Trigger conditions PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Wakeup from enabled LLWU input source or RESET pin. VLPR PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is... -
Page 290: Freescale Semiconductor, Inc
Functional description Reset Control Low - Module Leakage (RCM) Wakeup (LLWU) Stop/Wait LP exit LP exit System Bus masters low power bus (non-CPU) Clock Mode CCM low power bus Control Bus slaves low power bus Controller Module (SMC) (CCM) PMC low power bus Flash low power bus MCG enable System... -
Page 291: Run Modes
Chapter 14 System Mode Controller 14.4.2.2 Stop mode exit sequence Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR): 1. -
Page 292: Freescale Semiconductor, Inc
Functional description 14.4.3 Run modes The device contains two different run modes: • Run • Very Low-Power Run (VLPR) 14.4.3.1 RUN mode This is the normal operating mode for the device. This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR): •... -
Page 293: Wait Modes
Chapter 14 System Mode Controller in the MCG module, the module clock enables in the SIM, or any clock divider registers. To reenter Normal Run mode, clear RUNM. The PMSTAT register is a read-only status register that can be used to determine when the system has completed an exit to RUN mode. -
Page 294: Stop Modes
Functional description VLPR mode restrictions also apply to VLPW. When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. A system reset will cause an exit from VLPW mode, returning the device to normal RUN mode. -
Page 295: Freescale Semiconductor, Inc
Chapter 14 System Mode Controller A module capable of providing an asynchronous interrupt to the device takes the device out of STOP mode and returns the device to normal RUN mode. Refer to the device's Power Management chapter for peripheral, I/O, and memory operation in STOP mode. When an interrupt request occurs, the CPU exits STOP mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. -
Page 296: Freescale Semiconductor, Inc
Functional description Before entering LLS mode, the user should configure the low-leakage wakeup (LLWU) module to enable the desired wakeup sources. The available wakeup sources in LLS are detailed in the chip configuration details for this device. After wakeup from LLS, the device returns to normal RUN mode with a pending LLWU module interrupt. -
Page 297: Debug In Low Power Modes
Chapter 14 System Mode Controller When entering VLLS, each I/O pin is latched as configured before executing VLLS. Because all digital logic in the MCU is powered off, all port and peripheral data is lost during VLLS. This information must be restored before the ACKISO bit in the PMC is set. -
Page 298: Freescale Semiconductor, Inc
Functional description The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge (VLLDBGACK) bit that is set to release the ARM core being held in reset following a VLLS recovery. The debugger reinitializes all debug IP, and then asserts the VLLDBGACK control bit to allow the RCM to release the ARM core from reset and allow CPU operation to begin. -
Page 299: Introduction
Chapter 15 Power Management Controller 15.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), and low voltage detect system. 15.2 Features The PMC features include: •... -
Page 300: Lvd Reset Operation
Low-voltage detect (LVD) system • The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF bit is set when the supply voltage falls below the selected trip point (VLVD). The LVDF bit is cleared by writing one to the LVDACK bit, but only if the internal supply has returned above the trip point;... -
Page 301: I/O Retention
Chapter 15 Power Management Controller 15.4 I/O retention When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full regulation, and releases the logic from state retention mode. -
Page 302: Freescale Semiconductor, Inc
Memory map and register descriptions While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect systems that must have LVD always on, configure the SMC's power mode protection register (PMPROT) to disallow any very low power or low leakage modes from being enabled. -
Page 303: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
Chapter 15 Power Management Controller PMC_LVDSC1 field descriptions (continued) Field Description Low trip point selected (V LVDL High trip point selected (V LVDH Reserved Reserved 15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2) This register contains status and control bits to support the low voltage warning function. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC2 settings. -
Page 304: Regulator Status And Control Register (Pmc_Regsc)
Memory map and register descriptions PMC_LVDSC2 field descriptions (continued) Field Description Low-Voltage Warning Interrupt Enable LVWIE Enables hardware interrupt requests for LVWF. Hardware interrupt disabled (use polling) Request a hardware interrupt when LVWF = 1 4–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. -
Page 305: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Chapter 15 Power Management Controller PMC_REGSC field descriptions (continued) Field Description BGEN controls whether the bandgap is enabled in lower power modes of operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage reference in low power modes of operation, set BGEN to continue to enable the bandgap operation. -
Page 306: Freescale Semiconductor, Inc
Memory map and register descriptions K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 307: Introduction
Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The LLWU module allows the user to select up to 16 external pin sources and up to 8 internal modules as a wakeup source from low-leakage power modes. -
Page 308: Modes Of Operation
Introduction • External pin wakeup inputs, each of which is programmable as falling-edge, rising- edge, or any change • Wakeup inputs that are activated if enabled after MCU enters a low-leakage power mode • Optional digital filters provided to qualify an external pin detect and RESET pin detect. -
Page 309: Block Diagram
Chapter 16 Low-Leakage Wakeup Unit (LLWU) When theRESET pin filter or wakeup pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within 5 LPO clock cycles of an active edge, the edge event will be detected by the LLWU. For RESET pin filtering, this means that there is no restart to the minimum LPO cycle duration as the filtering transitions from a non-low leakage filter, which is implemented in the RCM, to the LLWU filter. -
Page 310: Llwu Signal Descriptions
LLWU signal descriptions enter low leakge mode WUME7 LLWU_MWUF7 occurred Interrupt module Module7 interrupt flag flag detect (LLWU_M7IF) Internal module sources LLWU_MWUF0 occurred Interrupt module Module0 interrupt flag flag detect (LLWU_M0IF) FILT1[FILTSEL] WUME0 FILT1[FILTE] LLWU_P15 Pin filter 1 wakeup occurred Edge Synchronizer Pin filter 1... -
Page 311: Memory Map/Register Definition
Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.3 Memory map/register definition The LLWU includes the following registers: • Five 8-bit wakeup source enable registers • Enable external pin input sources • Enable internal peripheral sources • Three 8-bit wakeup flag registers •... -
Page 312: Llwu Pin Enable 1 Register (Llwu_Pe1)
Memory map/register definition 16.3.1 LLWU Pin Enable 1 register (LLWU_PE1) LLWU_PE1 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P3-LLWU_P0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. -
Page 313: Llwu Pin Enable 2 Register (Llwu_Pe2)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_PE1 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 16.3.2 LLWU Pin Enable 2 register (LLWU_PE2) LLWU_PE2 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P7-LLWU_P4. -
Page 314: Llwu Pin Enable 3 Register (Llwu_Pe3)
Memory map/register definition LLWU_PE2 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 1–0 Wakeup Pin Enable For LLWU_P4 WUPE4 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection... -
Page 315: Llwu Pin Enable 4 Register (Llwu_Pe4)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_PE3 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 3–2 Wakeup Pin Enable For LLWU_P9 WUPE9 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection... -
Page 316: Llwu Module Enable Register (Llwu_Me)
Memory map/register definition LLWU_PE4 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 5–4 Wakeup Pin Enable For LLWU_P14 WUPE14 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection... -
Page 317: Freescale Semiconductor, Inc
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_ME field descriptions Field Description Wakeup Module Enable For Module 7 WUME7 Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 6 WUME6 Enables an internal module as a wakeup source input. -
Page 318: Llwu Flag 1 Register (Llwu_F1)
Memory map/register definition 16.3.6 LLWU Flag 1 register (LLWU_F1) LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. -
Page 319: Llwu Flag 2 Register (Llwu_F2)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_F1 field descriptions (continued) Field Description Wakeup Flag For LLWU_P4 WUF4 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF4. LLWU_P4 input was not a wakeup source LLWU_P4 input was a wakeup source Wakeup Flag For LLWU_P3... -
Page 320: Freescale Semiconductor, Inc
Memory map/register definition NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. -
Page 321: Llwu Flag 3 Register (Llwu_F3)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_F2 field descriptions (continued) Field Description Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF10. LLWU_P10 input was not a wakeup source LLWU_P10 input was a wakeup source Wakeup Flag For LLWU_P9 WUF9... -
Page 322: Freescale Semiconductor, Inc
Memory map/register definition LLWU_F3 field descriptions Field Description Wakeup flag For module 7 MWUF7 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Module 7 input was not a wakeup source Module 7 input was a wakeup source Wakeup flag For module 6... -
Page 323: Llwu Pin Filter 1 Register (Llwu_Filt1)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_F3 field descriptions (continued) Field Description Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Module 0 input was not a wakeup source Module 0 input was a wakeup source 16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1) LLWU_FILT1 is a control and status register that is used to enable/disable the digital... -
Page 324: Llwu Pin Filter 2 Register (Llwu_Filt2)
Memory map/register definition LLWU_FILT1 field descriptions (continued) Field Description 3–0 Filter Pin Select FILTSEL Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 Select LLWU_P0 for filter 1111 Select LLWU_P15 for filter 16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2) LLWU_FILT2 is a control and status register that is used to enable/disable the digital filter 2 features for an external pin. -
Page 325: Llwu Reset Enable Register (Llwu_Rst)
Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_FILT2 field descriptions (continued) Field Description 3–0 Filter Pin Select FILTSEL Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 Select LLWU_P0 for filter 1111 Select LLWU_P15 for filter 16.3.11 LLWU Reset Enable register (LLWU_RST) LLWU_RST is a control register that is used to enable/disable the digital filter for the external pin detect and RESET pin. -
Page 326: Functional Description
Functional description 16.4 Functional description This on-chip peripheral module is called a low-leakage wakeup unit (LLWU) module because it allows internal peripherals and external input pins as a source of wakeup from low-leakage modes. It is operational only in LLS and VLLSx modes. The LLWU module contains pin enables for each external pin and internal module. -
Page 327: Vlls Modes
Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.4.2 VLLS modes In the case of a wakeup due to external pin or internal module wakeup, recovery is always via a reset flow and the RCM_SRS[WAKEUP] is set indicating the low-leakage mode was active. State retention data is lost and I/O will be restored after PMC_REGSC[ACKISO] has been written. -
Page 328: Freescale Semiconductor, Inc
Functional description K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 329: Miscellaneous Control Module (Mcm)
Chapter 17 Miscellaneous Control Module (MCM) 17.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 17.1.1 Features The MCM includes the following features: •... -
Page 330: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
Memory map/register descriptions 17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) PLASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the device’s crossbar switch. Address: E008_0000h base + 8h offset = E008_0008h Read Write Reset MCM_PLASC field descriptions Field Description 15–8... -
Page 331: Control Register (Mcm_Cr)
Chapter 17 Miscellaneous Control Module (MCM) MCM_PLAMC field descriptions (continued) Field Description A bus master connection to AXBS input port n is absent A bus master connection to AXBS input port n is present 17.2.3 Control Register (MCM_CR) CR defines the arbitration and protection schemes for the two system RAM arrays. NOTE Bits 23-0 are undefined after reset. -
Page 332: Freescale Semiconductor, Inc
Memory map/register descriptions MCM_CR field descriptions (continued) Field Description Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the SRAM_L array. Round robin Special round robin (favors SRAM backoor accesses over the processor) Fixed priority. Processor has highest, backdoor has lowest Fixed priority. -
Page 333: Crossbar Switch (Axbs)
Chapter 18 Crossbar Switch (AXBS) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure. -
Page 334: Memory Map / Register Definition
Memory Map / Register Definition 18.2 Memory Map / Register Definition Each slave port of the crossbar switch contains configuration registers. Read- and write- transfers require two bus clock cycles. The registers can be read from and written to only in supervisor mode. -
Page 335: Priority Registers Slave (Axbs_Prsn)
Chapter 18 Crossbar Switch (AXBS) AXBS memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_4710 Control Register (AXBS_CRS7) 0000_0000h 18.2.2/338 4000_4800 Master General Purpose Control Register (AXBS_MGPCR0) 0000_0000h 18.2.3/340 4000_4900 Master General Purpose Control Register (AXBS_MGPCR1) 0000_0000h 18.2.3/340 4000_4A00... -
Page 336: Freescale Semiconductor, Inc
Memory Map / Register Definition * Notes: • See the device configuration details for the reset value of this register. AXBS_PRSn field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 30–28 Master 7 Priority. -
Page 337: Freescale Semiconductor, Inc
Chapter 18 Crossbar Switch (AXBS) AXBS_PRSn field descriptions (continued) Field Description This master has level 5 priority when accessing the slave port. This master has level 6 priority when accessing the slave port. This master has level 7 priority when accessing the slave port. This master has level 8, or lowest, priority when accessing the slave port. -
Page 338: Control Register (Axbs_Crsn)
Memory Map / Register Definition AXBS_PRSn field descriptions (continued) Field Description This master has level 4 priority when accessing the slave port. This master has level 5 priority when accessing the slave port. This master has level 6 priority when accessing the slave port. This master has level 7 priority when accessing the slave port. -
Page 339: Freescale Semiconductor, Inc
Chapter 18 Crossbar Switch (AXBS) AXBS_CRSn field descriptions (continued) Field Description Fixed priority Round-robin, or rotating, priority Reserved Reserved 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–4 Parking Control PCTL Determines the slave port’s parking control. -
Page 340: Master General Purpose Control Register (Axbs_Mgpcrn)
Functional Description 18.2.3 Master General Purpose Control Register (AXBS_MGPCRn) The MGPCR controls only whether the master’s undefined length burst accesses are allowed to complete uninterrupted or whether they can be broken by requests from higher priority masters. The MGPCR can be accessed only in Supervisor mode with 32-bit accesses. -
Page 341: Register Coherency
Chapter 18 Crossbar Switch (AXBS) port, the requesting master simply sees wait states inserted until the targeted slave port can service the master's request. The latency in servicing the request depends on each master's priority level and the responding peripheral's access time. Because the crossbar switch appears to be just another slave to the master device, the master device has no knowledge of whether it actually owns the slave port it is targeting. -
Page 342: Arbitration
Functional Description The MGPCRx[AULB] bits are the exception to this rule. The update of these bits is only recognized when the master on that master port runs an IDLE cycle, even though the slave bus cycle to write them will have already terminated successfully. If the MGPCRx[AULB] bits are written between two burst accesses, the new AULB encodings do not take effect until an IDLE cycle is initiated by the master on that master port. -
Page 343: Freescale Semiconductor, Inc
Chapter 18 Crossbar Switch (AXBS) continued burst, or the ninth beat of the second burst from the master's perspective, is taken, all beats of the burst are once again open for arbitration until the master loses control of the slave port. Assume the master again loses control of the slave port on the fifth beat of the third now continued burst, or the 10th beat of the second burst from the master's perspective. -
Page 344: Freescale Semiconductor, Inc
Functional Description Table 18-29. How AXBS grants control of a slave port to a master (continued) When Then AXBS grants control to the requesting master The requesting master's priority level is lower than the current At the conclusion of one of the following cycles: master. -
Page 345: Initialization/Application Information
Chapter 18 Crossbar Switch (AXBS) 18.4 Initialization/application information No initialization is required by or for the crossbar switch. Hardware reset ensures all the register bits used by the crossbar switch are properly initialized to a valid state. However, settings and priorities may be programmed to achieve maximum system performance. K30 Sub-Family Reference Manual, Rev. -
Page 346: Freescale Semiconductor, Inc
Initialization/application information K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 347: Peripheral Bridge (Aips-Lite)
Chapter 19 Peripheral Bridge (AIPS-Lite) 19.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The peripheral bridge converts the crossbar switch interface to an interface that can access a majority of peripherals on the device. The peripheral bridge supports up to 128 peripherals . -
Page 348: General Operation
Memory map/register definition 19.1.2 General operation The peripherals connected to the peripheral bridge are modules that contain readable/ writable control and status registers. The system masters read and write these registers through the peripheral bridge. The peripheral bridge generates the following as inputs to the peripherals: •... -
Page 349: Freescale Semiconductor, Inc
Chapter 19 Peripheral Bridge (AIPS-Lite) AIPS memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_0000 Master Privilege Register A (AIPS0_MPRA) Undefined 19.2.1/350 4000_0020 Peripheral Access Control Register (AIPS0_PACRA) 4444_4444h 19.2.2/352 4000_0024 Peripheral Access Control Register (AIPS0_PACRB) 4444_4444h 19.2.2/352 4000_0028... -
Page 350: Master Privilege Register A (Aipsx_Mpra)
Memory map/register definition 19.2.1 Master Privilege Register A (AIPSx_MPRA) The MPRA specifies identical 4-bit fields defining the access-privilege level associated with a bus master in the device to various peripherals. The register provides one field per bus master. NOTE At reset, the default value loaded into the MPRA fields is device-specific. -
Page 351: Freescale Semiconductor, Inc
Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_MPRA field descriptions (continued) Field Description This master is not trusted for read accesses. This master is trusted for read accesses. Master Trusted For Writes MTW0 Determines whether the master is trusted for write accesses. This master is not trusted for write accesses. -
Page 352: Peripheral Access Control Register (Aipsx_Pacrn)
Memory map/register definition AIPSx_MPRA field descriptions (continued) Field Description Accesses from this master are forced to user-mode. Accesses from this master are not forced to user-mode. 19–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–12 This field is reserved. -
Page 353: Freescale Semiconductor, Inc
Chapter 19 Peripheral Bridge (AIPS-Lite) Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 PACR65 PACR66 PACR67 PACR68 PACR69... -
Page 354: Freescale Semiconductor, Inc
Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. -
Page 355: Freescale Semiconductor, Inc
Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. -
Page 356: Freescale Semiconductor, Inc
Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. -
Page 357: Peripheral Access Control Register (Aipsx_Pacrn)
Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. -
Page 358: Freescale Semiconductor, Inc
Memory map/register definition Address: Base address + 40h offset + (4d × i), where i=0d to 11d Reset Reset * Notes: • x = Undefined at reset. AIPSx_PACRn field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. -
Page 359: Freescale Semiconductor, Inc
Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . This peripheral allows write accesses. -
Page 360: Freescale Semiconductor, Inc
Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . This peripheral allows write accesses. -
Page 361: Freescale Semiconductor, Inc
Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . This peripheral allows write accesses. -
Page 362: Functional Description
Functional description AIPSx_PACRn field descriptions (continued) Field Description Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . This peripheral allows write accesses. -
Page 363: Direct Memory Access Multiplexer (Dmamux)
Chapter 20 Direct Memory Access Multiplexer (DMAMUX) 20.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 20.1.1 Overview The direct memory access multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 16 DMA channels. This process is illustrated in the following figure. K30 Sub-Family Reference Manual, Rev. -
Page 364: Features
Introduction DMA Channel #0 DMAMUX Source #1 DMA Channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA Channel #n Trigger #z Figure 20-1. DMAMUX block diagram 20.1.2 Features The DMA channel MUX provides these features: •... -
Page 365: External Signal Description
Chapter 20 Direct Memory Access Multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger. -
Page 366: Channel Configuration Register (Dmamux_Chcfgn)
Memory map/register definition DMAMUX memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4002_1009 Channel Configuration register (DMAMUX_CHCFG9) 20.3.1/366 4002_100A Channel Configuration register (DMAMUX_CHCFG10) 20.3.1/366 4002_100B Channel Configuration register (DMAMUX_CHCFG11) 20.3.1/366 4002_100C Channel Configuration register (DMAMUX_CHCFG12) 20.3.1/366 4002_100D Channel Configuration register (DMAMUX_CHCFG13) 20.3.1/366... -
Page 367: Functional Description
Chapter 20 Direct Memory Access Multiplexer (DMAMUX) DMAMUX_CHCFGn field descriptions (continued) Field Description Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) Triggering is enabled. -
Page 368: Freescale Semiconductor, Inc
Functional description Source #1 Source #2 Source #3 DMA Channel #0 Trigger #1 DMA Channel #1 Trigger #2 Source #x DMA Channel #3 Trigger #4 Always #1 Always #y Figure 20-19. DMA MUX triggered channels The DMA channel triggering capability allows the system to "schedule" regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor. -
Page 369: Dma Channels With No Triggering Capability
Chapter 20 Direct Memory Access Multiplexer (DMAMUX) Peripheral Request Trigger DMA Request Figure 20-21. DMA MUX channel triggering: ignored trigger This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations: •... -
Page 370: Initialization/Application Information
Initialization/application information • Performing DMA transfers to/from GPIO—Moving data from/to one or more GPIO pins, either unthrottled (that is as fast as possible), or periodically (using the DMA triggering capability). • Performing DMA transfers from memory to memory—Moving data from memory to memory, typically as fast as possible, sometimes with software activation. -
Page 371: Reset
Chapter 20 Direct Memory Access Multiplexer (DMAMUX) 20.5.1 Reset The reset state of each individual bit is shown in Memory map/register definition. In summary, after reset, all channels are disabled and must be explicitly enabled before use. 20.5.2 Enabling and configuring sources To enable a source with periodic triggering: 1. -
Page 372: Freescale Semiconductor, Inc
Initialization/application information *CHCONFIG2 = 0x00; *CHCONFIG2 = 0xC5; To enable a source without periodic triggering: 1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel. 3. -
Page 373: Freescale Semiconductor, Inc
Chapter 20 Direct Memory Access Multiplexer (DMAMUX) 1. Disable the DMA channel in the DMA and re-configure the channel for the new source. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel. 3. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] bits are set. -
Page 374: Freescale Semiconductor, Inc
Initialization/application information K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 375: Direct Memory Access Controller (Edma)
Chapter 21 Direct Memory Access Controller (eDMA) 21.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor. -
Page 376: Block Parts
Introduction eDMA Write Address Write Data Transfer Control Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 21-1. eDMA block diagram 21.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory. -
Page 377: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) Table 21-1. eDMA engine submodules Submodule Function Address path This block implements registered versions of two channel transfer control descriptors, channel x and channel y, and manages all master bus-address calculations. All the channels provide the same functionality. -
Page 378: Features
Introduction Table 21-2. Transfer control descriptor memory Submodule Description Memory controller This logic implements the required dual-ported controller, managing accesses from the eDMA engine as well as references from the internal peripheral bus. As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled. -
Page 379: Modes Of Operation
Chapter 21 Direct Memory Access Controller (eDMA) • Channel completion reported via optional interrupt requests • One interrupt per channel, optionally asserted at completion of major iteration count • Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller •... -
Page 380: Freescale Semiconductor, Inc
Memory map/register definition • The first region defines a number of registers providing control functions • The second region corresponds to the local transfer control descriptor memory Each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. -
Page 381: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_8034 Hardware Request Status Register (DMA_HRS) 0000_0000h 21.3.15/411 4000_8100 Channel n Priority Register (DMA_DCHPRI3) See section 21.3.16/414 4000_8101 Channel n Priority Register (DMA_DCHPRI2) -
Page 382: Freescale Semiconductor, Inc
Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Beginning Minor Loop Link, Major Loop Count 4000_901E Undefined 21.3.31/427 (Channel Linking Disabled) (DMA_TCD0_BITER_ELINKNO) 4000_9020 TCD Source Address (DMA_TCD1_SADDR) Undefined 21.3.17/415 4000_9024... -
Page 383: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_9056 DMA_TCD2_CITER_ELINKNO Undefined 21.3.27/422 TCD Last Destination Address Adjustment/Scatter Gather 4000_9058 Undefined 21.3.28/423 Address (DMA_TCD2_DLASTSGA) 4000_905C TCD Control and Status (DMA_TCD2_CSR) Undefined 21.3.29/424 TCD Beginning Minor Loop Link, Major Loop Count... -
Page 384: Freescale Semiconductor, Inc
Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Last Source Address Adjustment 4000_908C Undefined 21.3.23/420 (DMA_TCD4_SLAST) 4000_9090 TCD Destination Address (DMA_TCD4_DADDR) Undefined 21.3.24/420 TCD Signed Destination Address Offset 4000_9094 Undefined 21.3.25/421... -
Page 385: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_90C6 TCD Transfer Attributes (DMA_TCD6_ATTR) Undefined 21.3.19/416 TCD Minor Byte Count (Minor Loop Disabled) 4000_90C8 Undefined 21.3.20/417 (DMA_TCD6_NBYTES_MLNO) TCD Signed Minor Loop Offset (Minor Loop Enabled and... -
Page 386: Freescale Semiconductor, Inc
Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Beginning Minor Loop Link, Major Loop Count 4000_90FE (Channel Linking Enabled) Undefined 21.3.30/426 (DMA_TCD7_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count 4000_90FE Undefined 21.3.31/427... -
Page 387: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Signed Destination Address Offset 4000_9134 Undefined 21.3.25/421 (DMA_TCD9_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_9136 Undefined 21.3.26/421... -
Page 388: Freescale Semiconductor, Inc
Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Minor Byte Count (Minor Loop Disabled) 4000_9168 Undefined 21.3.20/417 (DMA_TCD11_NBYTES_MLNO) TCD Signed Minor Loop Offset (Minor Loop Enabled and 4000_9168 Undefined 21.3.21/417... -
Page 389: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Beginning Minor Loop Link, Major Loop Count 4000_919E (Channel Linking Enabled) Undefined 21.3.30/426 (DMA_TCD12_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count 4000_919E (Channel Linking Disabled) Undefined... -
Page 390: Freescale Semiconductor, Inc
Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_91D0 TCD Destination Address (DMA_TCD14_DADDR) Undefined 21.3.24/420 TCD Signed Destination Address Offset 4000_91D4 Undefined 21.3.25/421 (DMA_TCD14_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_91D6 Undefined 21.3.26/421... -
Page 391: Control Register (Dma_Cr)
Chapter 21 Direct Memory Access Controller (eDMA) 21.3.1 Control Register (DMA_CR) The CR defines the basic operating configuration of the DMA. Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For fixed-priority arbitration, the highest priority channel requesting service is selected to execute. -
Page 392: Error Status Register (Dma_Es)
Memory map/register definition DMA_CR field descriptions (continued) Field Description sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the ES register and generating an optional error interrupt. -
Page 393: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) • An illegal setting in the transfer-control descriptor, or • An illegal priority register setting in fixed-arbitration • An error termination to a bus master read or write cycle See the Error Reporting and Handling section for more details. Address: 4000_8000h base + 4h offset = 4000_8004h Reset ERRCHN... -
Page 394: Enable Request Register (Dma_Erq)
Memory map/register definition DMA_ES field descriptions (continued) Field Description Source Offset Error No source offset configuration error The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. Destination Address Error No destination address configuration error The last recorded error was a configuration error detected in the TCDn_DADDR field. -
Page 395: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) DMA request input signals and this enable request flag must be asserted before a channel’s hardware service request is accepted. The state of the DMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request. -
Page 396: Freescale Semiconductor, Inc
Memory map/register definition DMA_ERQ field descriptions (continued) Field Description Enable DMA Request 9 ERQ9 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Enable DMA Request 8 ERQ8 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Enable DMA Request 7 ERQ7... -
Page 397: Enable Error Interrupt Register (Dma_Eei)
Chapter 21 Direct Memory Access Controller (eDMA) 21.3.4 Enable Error Interrupt Register (DMA_ EEI ) The EEI register provides a bit map for the 16 channels to enable the error interrupt signal for each channel. The state of any given channel’s error interrupt enable is directly affected by writes to this register;... -
Page 398: Freescale Semiconductor, Inc
Memory map/register definition DMA_EEI field descriptions (continued) Field Description Enable Error Interrupt 11 EEI11 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 10 EEI10 The error signal for corresponding channel does not generate an error interrupt... -
Page 399: Clear Enable Error Interrupt Register (Dma_Ceei)
Chapter 21 Direct Memory Access Controller (eDMA) 21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI) The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI to disable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be cleared. -
Page 400: Set Enable Error Interrupt Register (Dma_Seei)
Memory map/register definition 21.3.6 Set Enable Error Interrupt Register (DMA_SEEI) The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be set. -
Page 401: Clear Enable Request Register (Dma_Cerq)
Chapter 21 Direct Memory Access Controller (eDMA) 21.3.7 Clear Enable Request Register (DMA_CERQ) The CERQ provides a simple memory-mapped mechanism to clear a given bit in the ERQ to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be cleared. -
Page 402: Set Enable Request Register (Dma_Serq)
Memory map/register definition 21.3.8 Set Enable Request Register (DMA_SERQ) The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be set. -
Page 403: Clear Done Status Bit Register (Dma_Cdne)
Chapter 21 Direct Memory Access Controller (eDMA) 21.3.9 Clear DONE Status Bit Register (DMA_CDNE) The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. -
Page 404: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Memory map/register definition 21.3.10 Set START Bit Register (DMA_SSRT) The SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. -
Page 405: Clear Error Register (Dma_Cerr)
Chapter 21 Direct Memory Access Controller (eDMA) 21.3.11 Clear Error Register (DMA_CERR) The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the ERR to be cleared. -
Page 406: Clear Interrupt Request Register (Dma_Cint)
Memory map/register definition 21.3.12 Clear Interrupt Request Register (DMA_CINT) The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the INT to be cleared. -
Page 407: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) The state of any given channel’s interrupt request is directly affected by writes to this register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit position clears the corresponding channel’s interrupt request. -
Page 408: Freescale Semiconductor, Inc
Memory map/register definition DMA_INT field descriptions (continued) Field Description Interrupt Request 11 INT11 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 10 INT10 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 9 INT9... -
Page 409: Error Register (Dma_Err)
Chapter 21 Direct Memory Access Controller (eDMA) 21.3.14 Error Register (DMA_ ERR ) The ERR provides a bit map for the 16 channels, signaling the presence of an error for each channel. The eDMA engine signals the occurrence of an error condition by setting the appropriate bit in this register. -
Page 410: Freescale Semiconductor, Inc
Memory map/register definition DMA_ERR field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Error In Channel 15 ERR15 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred Error In Channel 14 ERR14 An error in the corresponding channel has not occurred... -
Page 411: Hardware Request Status Register (Dma_Hrs)
Chapter 21 Direct Memory Access Controller (eDMA) DMA_ERR field descriptions (continued) Field Description An error in the corresponding channel has not occurred An error in the corresponding channel has occurred Error In Channel 3 ERR3 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred Error In Channel 2 ERR2... -
Page 412: Freescale Semiconductor, Inc
Memory map/register definition HRS9 HRS8 HRS7 HRS6 HRS5 HRS4 HRS3 HRS2 HRS1 HRS0 Reset DMA_HRS field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Hardware Request Status Channel 15 HRS15 A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present... -
Page 413: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) DMA_HRS field descriptions (continued) Field Description A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present Hardware Request Status Channel 5 HRS5 A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present Hardware Request Status Channel 4... -
Page 414: Channel N Priority Register (Dma_Dchprin)
Memory map/register definition 21.3.16 Channel n Priority Register (DMA_DCHPRIn) When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel . The channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next priority, then 2, 3, etc. -
Page 415: Tcd Source Address (Dma_Tcdn_Saddr)
Chapter 21 Direct Memory Access Controller (eDMA) 21.3.17 TCD Source Address (DMA_TCDn_SADDR) Address: 4000_8000h base + 1000h offset + (32d × i), where i=0d to 15d SADDR x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset * Notes: •... -
Page 416: Tcd Transfer Attributes (Dma_Tcdn_Attr)
Memory map/register definition 21.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR) Address: 4000_8000h base + 1006h offset + (32d × i), where i=0d to 15d Read SMOD SSIZE DMOD DSIZE Write Reset * Notes: • x = Undefined at reset. DMA_TCDn_ATTR field descriptions Field Description 15–11... -
Page 417: Tcd Minor Byte Count (Minor Loop Disabled) (Dma_Tcdn_Nbytes_Mlno)
Chapter 21 Direct Memory Access Controller (eDMA) 21.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO) TCD word 2's register definition depends on the status of minor loop mapping. If minor loop mapping is disabled (CR[EMLM] = 0), TCD word 2 is defined as follows. If minor loop mapping is enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions for TCD word 2's register definition. -
Page 418: Tcd Signed Minor Loop Offset (Minor Loop And Offset Enabled Dma_Tcdn_Nbytes_Mloffyes)
Memory map/register definition Address: 4000_8000h base + 1008h offset + (32d × i), where i=0d to 15d NBYTES Reset NBYTES Reset * Notes: • x = Undefined at reset. DMA_TCDn_NBYTES_MLOFFNO field descriptions Field Description Source Minor Loop Offset Enable SMLOE Selects whether the minor loop offset is applied to the source address upon minor loop completion. -
Page 419: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) If minor loop mapping is enabled and SMLOE and DMLOE are cleared then refer to the TCD_NBYTES_MLOFFNO register description. Address: 4000_8000h base + 1008h offset + (32d × i), where i=0d to 15d MLOFF Reset MLOFF... -
Page 420: Tcd Last Source Address Adjustment (Dma_Tcdn_Slast)
Memory map/register definition 21.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST) Address: 4000_8000h base + 100Ch offset + (32d × i), where i=0d to 15d SLAST x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset * Notes: •... -
Page 421: Tcd Signed Destination Address Offset (Dma_Tcdn_Doff)
Chapter 21 Direct Memory Access Controller (eDMA) 21.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF) Address: 4000_8000h base + 1014h offset + (32d × i), where i=0d to 15d Read DOFF Write Reset * Notes: • x = Undefined at reset. DMA_TCDn_DOFF field descriptions Field Description... -
Page 422: Tcd Current Minor Loop Link, Major Loop Count (Channel Linking Disabled Dma_Tcdn_Citer_Elinkno)
Memory map/register definition DMA_TCDn_CITER_ELINKYES field descriptions (continued) Field Description If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. -
Page 423: Tcd Last Destination Address Adjustment/Scatter Gather Address (Dma_Tcdn_Dlastsga)
Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_CITER_ELINKNO field descriptions Field Description Enable channel-to-channel linking on minor-loop complete ELINK As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. -
Page 424: Tcd Control And Status (Dma_Tcdn_Csr)
Memory map/register definition DMA_TCDn_DLASTSGA field descriptions (continued) Field Description else • This address points to the beginning of a 0-modulo-32-byte region containing the next transfer control descriptor to be loaded into this channel. This channel reload is performed as the major iteration count completes. -
Page 425: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_CSR field descriptions (continued) Field Description • After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the channel defined by these six bits by setting that channel’s TCDn_CSR[START] bit. Channel Done DONE This flag indicates the eDMA has completed the major loop. -
Page 426: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled Dma_Tcdn_Biter_Elinkyes)
Memory map/register definition DMA_TCDn_CSR field descriptions (continued) Field Description Enable an interrupt when major iteration count completes INTMAJOR If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero. The end-of-major loop interrupt is disabled The end-of-major loop interrupt is enabled Channel Start... -
Page 427: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled Dma_Tcdn_Biter_Elinkno)
Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_BITER_ELINKYES field descriptions (continued) Field Description The channel-to-channel linking is disabled The channel-to-channel linking is enabled 14–13 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 12–9 Link Channel Number LINKCH... -
Page 428: Edma Basic Data Flow
Functional description DMA_TCDn_BITER_ELINKNO field descriptions (continued) Field Description As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. -
Page 429: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Chapter 21 Direct Memory Access Controller (eDMA) eDMA Write Address Write Data Transfer Control Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 21-289. eDMA operation, part 1 This example uses the assertion of the eDMA peripheral request signal to request service for channel n. -
Page 430: Freescale Semiconductor, Inc
Functional description eDMA Write Address Write Data Transfer Control Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 21-290. eDMA operation, part 2 The modules associated with the data transfer (address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement. -
Page 431: Error Reporting And Handling
Chapter 21 Direct Memory Access Controller (eDMA) eDMA Write Address Write Data Transfer Control Descriptor (TCD) eDMA En g in e Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 21-291. -
Page 432: Freescale Semiconductor, Inc
Functional description • All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. • In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal. All channel priority levels must be unique when fixed arbitration mode is enabled. -
Page 433: Channel Preemption
Chapter 21 Direct Memory Access Controller (eDMA) The occurrence of any error causes the eDMA engine to stop normal processing of the active channel immediately (it goes to its error processing states and the transaction to the system bus still has peipeline effect), and the appropriate channel bit in the eDMA error register is asserted. -
Page 434: Freescale Semiconductor, Inc
Functional description • In the traditional data movement context, performance is best expressed as the peak data transfer rates achieved using the eDMA. In most implementations, this transfer rate is limited by the speed of the source and destination address spaces. •... -
Page 435: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) 21.4.4.2 Peak request rates The second performance metric is a measure of the number of DMA requests that can be serviced in a given amount of time. For this metric, assume that the peripheral request causes the channel to move a single internal peripheral bus-mapped operand to/from internal SRAM. -
Page 436: Freescale Semiconductor, Inc
Functional description Table 21-293. Hardware service request process (continued) Cycle Description With internal peripheral With SRAM read and bus read and internal internal peripheral bus SRAM write write The fields in the second part of the TCDn are written back into the local memory. -
Page 437: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) 21.4.4.3 eDMA performance example Consider a system with the following characteristics: • Internal SRAM can be accessed with one wait-state when viewed from the system bus data phase • All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states viewed from the system bus data phase •... -
Page 438: Initialization/Application Information
Initialization/application information 21.5 Initialization/application information The following sections discuss initialization of the eDMA and programming considerations. 21.5.1 eDMA initialization To initialize the eDMA: 1. Write to the CR if a configuration other than the default is desired. 2. Write the channel priority levels to the DCHPRIn registers if a configuration other than the default is desired. -
Page 439: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) Table 21-296. TCD Control and Status fields TCDn_CSR field Description name START Control bit to start channel explicitly when using a software initiated DMA service (Automatically cleared by hardware) ACTIVE Status bit indicating the channel is currently in execution DONE Status bit indicating major loop completion (cleared by software when using a software initiated DMA service) -
Page 440: Programming Errors
Initialization/application information xADDR: (Starting address) xSIZE: (size of one Minor loop data transfer) (NBYTES in minor loop, Offset (xOFF): number of bytes added to often the same current address after each transfer value as xSIZE) (often the same value as xSIZE) Each DMA source (S) and destination (D) has its own: Address (xADDR) -
Page 441: Performing Dma Transfers (Examples)
Chapter 21 Direct Memory Access Controller (eDMA) 21.5.3.2 Round-robin channel arbitration Channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels. 21.5.4 Performing DMA transfers (examples) 21.5.4.1 Single request To perform a simple transfer of n bytes of data with one activation, set the major loop to one (TCDn_CITER = TCDn_BITER = 1). -
Page 442: Freescale Semiconductor, Inc
Initialization/application information 4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source-to-destination transfers are executed as follows: a. Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b. -
Page 443: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. 4. eDMA engine reads: channel TCDn data from local memory to internal register file. 5. -
Page 444: Freescale Semiconductor, Inc
Initialization/application information b. Write 32-bits to location 0x2010 → first iteration of the minor loop. c. Read byte from location 0x1014, read byte from location 0x1015, read byte from 0x1016, read byte from 0x1017. d. Write 32-bits to location 0x2014 → second iteration of the minor loop. e. -
Page 445: Monitoring Transfer Descriptor Status
Chapter 21 Direct Memory Access Controller (eDMA) Table 21-297. Modulo example (continued) Transfer Number Address 0x12345674 0x12345678 0x1234567C 0x12345670 0x12345674 21.5.5 Monitoring transfer descriptor status 21.5.5.1 Testing for minor loop completion There are two methods to test for minor loop completion when using software initiated service requests. -
Page 446: Freescale Semiconductor, Inc
Initialization/application information TCDn_CSR bits Stage State START ACTIVE DONE Channel service request via hardware (peripheral request asserted) Channel is executing Channel has completed the minor loop and is idle Channel has completed the major loop and is idle For both activation types, the major-loop-complete status is explicitly indicated via the TCDn_CSR[DONE] bit. -
Page 447: Channel Linking
Chapter 21 Direct Memory Access Controller (eDMA) 21.5.6 Channel Linking Channel linking (or chaining) is a mechanism where one channel sets the TCDn_CSR[START] bit of another channel (or itself), therefore initiating a service request for that channel. When properly enabled, the EDMA engine automatically performs this operation at the major or minor loop completion. -
Page 448: Dynamic Programming
Initialization/application information Table 21-298. Channel Linking Parameters Desired Link TCD Control Field Name Description Behavior Enable channel-to-channel linking on minor loop completion (current CITER[E_LINK] Link at end of iteration) Minor Loop CITER[LINKCH] Link channel number when linking at end of minor loop (current iteration) CSR[MAJOR_E_LINK] Enable channel-to-channel linking on major loop completion Link at end of... -
Page 449: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) Step Action Write 1b to the TCD.major.e_link bit. Read back the TCD.major.e_link bit. Test the TCD.major.e_link request status: • If TCD.major.e_link = 1b, the dynamic link attempt was successful. • If TCD.major.e_link = 0b, the attempted dynamic link did not succeed (the channel was already retiring). -
Page 450: Freescale Semiconductor, Inc
Initialization/application information cleared automatically by the eDMA engine after a channel begins execution. 21.5.7.3.1 Method 1 (channel not using major loop channel linking) For a channel not using major loop channel linking, the coherency model described here may be used for a dynamic scatter/gather request. When the TCD.major.e_link bit is zero, the TCD.major.linkch field is not used by the eDMA. -
Page 451: Freescale Semiconductor, Inc
Chapter 21 Direct Memory Access Controller (eDMA) For a channel using major loop channel linking, the coherency model described here may be used for a dynamic scatter/gather request. This method uses the TCD.dlast_sga field as a TCD indentification (ID). 1. Write 1b to the TCD.d_req bit. Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future hardware activation of this channel. -
Page 452: Freescale Semiconductor, Inc
Initialization/application information K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 453: External Watchdog Monitor (Ewm)
Chapter 22 External Watchdog Monitor (EWM) 22.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The watchdog is generally used to monitor the flow and execution of embedded software within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an internal reset (asynchronous) to all on-chip peripherals and optionally assert the RESET pin to reset external devices/circuits. -
Page 454: Modes Of Operation
Introduction • Windowed refresh option • Provides robust check that program flow is faster than expected. • Programmable window. • Refresh outside window leads to assertion of EWM_out. • Robust refresh mechanism • Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 (EWM_service_time) peripheral bus clock cycles. -
Page 455: Block Diagram
Chapter 22 External Watchdog Monitor (EWM) 22.1.2.2 Wait Mode The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes. 22.1.2.3 Debug Mode Entry to debug mode has no effect on the EWM. •... -
Page 456: Ewm Signal Descriptions
EWM Signal Descriptions 22.2 EWM Signal Descriptions The EWM has two external signals, as shown in the following table. Table 22-1. EWM Signal Descriptions Signal Description EWM_in EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. -
Page 457: Service Register (Ewm_Serv)
Chapter 22 External Watchdog Monitor (EWM) EWM_CTRL field descriptions Field Description 7–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Interrupt Enable. INTEN This bit when set and EWM_out is asserted, an interrupt request is generated. To de-assert interrupt request, user should clear this bit by writing 0. -
Page 458: Compare High Register (Ewm_Cmph)
Memory Map/Register Definition NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. Address: 4006_1000h base + 2h offset = 4006_1002h Read COMPAREL Write Reset EWM_CMPL field descriptions Field Description 7–0... -
Page 459: Functional Description
Chapter 22 External Watchdog Monitor (EWM) 22.4 Functional Description The following sections describe functional details of the EWM module. 22.4.1 The EWM_out Signal The EWM_out is a digital output signal used to gate an external circuit (application specific) that controls critical safety functions. For example, the EWM_out could be connected to the high voltage transistors circuits that control an AC motor in a large appliance. -
Page 460: Ewm Counter
Functional Description 22.4.2 The EWM_in Signal The EWM_in is a digital input signal that allows an external circuit to control the EWM_out signal. For example, in the application, an external circuit monitors a critical safety function, and if there is fault with this circuit's behavior, it can then actively initiate the EWM_out signal that controls the gating circuit. -
Page 461: Ewm Refresh Mechanism
Chapter 22 External Watchdog Monitor (EWM) • If the CPU services the EWM when the counter value lies between CMPL value and CMPH value, the counter is reset to zero. This is a legal service operation. • If the CPU executes a EWM service/refresh action outside the legal service window, EWM_out is asserted. -
Page 462: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Functional Description K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 463: Watchdog Timer (Wdog)
Chapter 23 Watchdog Timer (WDOG) 23.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. Reasons for failure include run-away software code and the stoppage of the system clock that in a safety critical system can lead to serious consequences. -
Page 464: Freescale Semiconductor, Inc
Features • You need to always update these bits after unlocking within 256 bus clock cycles. Failure to update these bits resets the system. • Programmable time-out period specified in terms of number of WDOG clock cycles. • Ability to test WDOG timer and reset with a flag indicating watchdog test. •... -
Page 465: Functional Overview
Chapter 23 Watchdog Timer (WDOG) 23.3 Functional overview WDOG Disable Control/Configuration Unlock Sequence bit changes N bus clk cycles after 2 Writes of data within K bus clock unlocking cycles of each other Refresh Sequence 2 writes of data within K 0xC520 bus clock cycles of each N bus clk cycles... -
Page 466: Unlocking And Updating The Watchdog
Functional overview to be serviced periodically, failing which it resets the system. This ensures that the software is executing correctly and has not run away in an unintended direction. Software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application. -
Page 467: Watchdog Configuration Time (Wct)
Chapter 23 Watchdog Timer (WDOG) The update feature is useful for applications that have an initial, non-safety critical part, where the watchdog is kept disabled or with a conveniently long time-out period. This means the application coder does not have to frequently service the watchdog. After the critical part of the application begins, the watchdog can be reconfigured as needed. -
Page 468: Refreshing The Watchdog
Functional overview Updates in the write-once registers take effect only after the WCT window closes with the following exceptions for which changes take effect immediately: • Stop, Wait, and Debug mode enable • IRQ_RST_EN The operations of refreshing the watchdog goes undetected during the WCT. 23.3.3 Refreshing the watchdog A robust refreshing mechanism has been chosen for the watchdog. -
Page 469: Low-Power Modes Of Operation
Chapter 23 Watchdog Timer (WDOG) time-out exception. See Generated Resets and Interrupts. You need to unlock the watchdog before enabling it. A system reset brings the watchdog out of the disabled mode. 23.3.6 Low-power modes of operation The low-power modes of operation of the watchdog are described in the following table: Table 23-1. -
Page 470: Testing The Watchdog
Testing the watchdog 23.4 Testing the watchdog For IEC 60730 and other safety standards, the expectation is that anything that monitors a safety function must be tested, and this test is required to be fault tolerant. To test the watchdog, its main timer and its associated compare and reset logic must be tested. To this end, two tests are implemented for the watchdog, as described in Quick Test Byte... -
Page 471: Byte Test
Chapter 23 Watchdog Timer (WDOG) 23.4.1 Quick test In this test, the time-out value of watchdog timer is programmed to a very low value to achieve quick time-out. The only difference between the quick test and the normal mode of the watchdog is that TESTWDOG is set for the quick test. This allows for a faster test of the watchdog reset mechanism. -
Page 472: Backup Reset Generator
Backup reset generator other stages, N – 2, N – 3... and N + 1, N + 2... are enabled for the test on byte N. These disabled stages, except the most significant stage of the counter, are loaded with a value of 0xFF. -
Page 473: Memory Map And Register Definition
Chapter 23 Watchdog Timer (WDOG) The watchdog can also generate an interrupt. If IRQ_RST_EN is set, then on the above mentioned events WDOG_ST_CTRL_L[INT_FLG] is set, generating an interrupt. A watchdog reset is also generated WCT time later to ensure the watchdog is fault tolerant. The interrupt can be cleared by writing 1 to INT_FLG. -
Page 474: Watchdog Status And Control Register High (Wdog_Stctrlh)
Memory map and register definition 23.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH) Address: 4005_2000h base + 0h offset = 4005_2000h Read Write Reset WDOG_STCTRLH field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Allows the WDOG’s functional test mode to be disabled permanently. -
Page 475: Watchdog Status And Control Register Low (Wdog_Stctrll)
Chapter 23 Watchdog Timer (WDOG) WDOG_STCTRLH field descriptions (continued) Field Description WDOG is disabled in CPU Stop mode. WDOG is enabled in CPU Stop mode. Enables or disables WDOG in Debug mode. DBGEN WDOG is disabled in CPU Debug mode. WDOG is enabled in CPU Debug mode. -
Page 476: Watchdog Time-Out Value Register High (Wdog_Tovalh)
Memory map and register definition WDOG_STCTRLL field descriptions Field Description Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a precondition to set this flag. INTFLG INTFLG = 1 results in an interrupt being issued followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this bit. -
Page 477: Watchdog Window Register High (Wdog_Winh)
Chapter 23 Watchdog Timer (WDOG) 23.7.5 Watchdog Window Register High (WDOG_WINH) NOTE You must set the Window Register value lower than the Time- out Value Register. Address: 4005_2000h base + 8h offset = 4005_2008h Read WINHIGH Write Reset WDOG_WINH field descriptions Field Description 15–0... -
Page 478: Watchdog Refresh Register (Wdog_Refresh)
Memory map and register definition 23.7.7 Watchdog Refresh register (WDOG_REFRESH) Address: 4005_2000h base + Ch offset = 4005_200Ch Read WDOGREFRESH Write Reset WDOG_REFRESH field descriptions Field Description 15–0 Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20 bus clock cycles written WDOGREFRESH to this register refreshes the WDOG and prevents it from resetting the system. -
Page 479: Watchdog Timer Output Register Low (Wdog_Tmroutl)
Chapter 23 Watchdog Timer (WDOG) WDOG_TMROUTH field descriptions Field Description 15–0 Shows the value of the upper 16 bits of the watchdog timer. TIMEROUTHIGH 23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL) During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of the watchdog timer. -
Page 480: Watchdog Prescaler Register (Wdog_Presc)
Watchdog operation with 8-bit access 23.7.12 Watchdog Prescaler register (WDOG_PRESC) Address: 4005_2000h base + 16h offset = 4005_2016h Read PRESCVAL Write Reset WDOG_PRESC field descriptions Field Description 15–11 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 10–8 3-bit prescaler for the watchdog clock source. -
Page 481: Restrictions On Watchdog Operation
Chapter 23 Watchdog Timer (WDOG) Whereas the match for a correct value for a refresh/unlock sequence is as according to the original definition, the match for an incorrect value is done byte-wise on the refresh/ unlock rather than for the whole 16-bit value. This means that if the high byte of the refresh/unlock register contains any value other than high bytes of the two values that make up the sequence, it is treated as an exception condition, leading to a reset or interrupt-then-reset. -
Page 482: Freescale Semiconductor, Inc
Restrictions on watchdog operation • Restriction on unlock/refresh operations—In the period between the closure of the WCT window after unlock and the actual reload of the watchdog timer, unlock and refresh operations need not be attempted. • The update and reload of the watchdog timer happens two to three watchdog clocks after WCT window closes, following a successful configuration on unlock. -
Page 483: Freescale Semiconductor, Inc
Chapter 23 Watchdog Timer (WDOG) • Trying to unlock the watchdog within the WCT time after an initial unlock has no effect. • The refresh and unlock operations and interrupt are not automatically disabled in the watchdog functional test mode. •... -
Page 484: Freescale Semiconductor, Inc
Restrictions on watchdog operation K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 485: Multipurpose Clock Generator (Mcg)
Chapter 24 Multipurpose Clock Generator (MCG) 24.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL). -
Page 486: Freescale Semiconductor, Inc
Introduction • Internal or external reference clock can be used as the FLL source. • Can be used as a clock source for other on-chip peripherals. • Phase-locked loop (PLL): • Voltage-controlled oscillator (VCO) • External reference clock is used as the PLL source. •... -
Page 487: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) • Internal Reference Clocks Auto Trim Machine (ATM) capability using an external clock as a reference • Reference dividers for both the FLL and PLL are provided • Reference dividers for the Fast Internal Reference Clock are provided •... -
Page 488: Freescale Semiconductor, Inc
Introduction Crystal Oscillator Oscillator External Reference Clock CLKS OSCINIT0 PLLCLKEN0 MCG Crystal Oscillator Enable Detect EREFS0 IREFS HGO0 PLLS ATMS RANGE0 OSCSEL STOP IREFSTEN Auto Trim Machine IRCLKEN MCGIRCLK SCTRIM IRCS Internal CLKS CLKS Reference SCFTRIM Slow Clock Clock IRCSCLK Generator Fast Clock FCTRIM... -
Page 489: Modes Of Operation
Chapter 24 Multipurpose Clock Generator (MCG) 24.1.2 Modes of Operation There are nine modes of operation for the MCG: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, BLPE, and Stop. For details, see MCG modes of operation. 24.2 External Signal Description There are no MCG signals that connect off chip. -
Page 490: Mcg Control 1 Register (Mcg_C1)
Memory Map/Register Definition 24.3.1 MCG Control 1 Register (MCG_C1) Address: 4006_4000h base + 0h offset = 4006_4000h Read CLKS FRDIV IREFS IRCLKEN IREFSTEN Write Reset MCG_C1 field descriptions Field Description 7–6 Clock Source Select CLKS Selects the clock source for MCGOUTCLK . Encoding 0 —... -
Page 491: Mcg Control 2 Register (Mcg_C2)
Chapter 24 Multipurpose Clock Generator (MCG) MCG_C1 field descriptions (continued) Field Description MCGIRCLK inactive. MCGIRCLK active. Internal Reference Stop Enable IREFSTEN Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. Internal reference clock is disabled in Stop mode. Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. -
Page 492: Mcg Control 3 Register (Mcg_C3)
Memory Map/Register Definition MCG_C2 field descriptions (continued) Field Description External reference clock requested. Oscillator requested. Low Power Select Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. -
Page 493: Mcg Control 4 Register (Mcg_C4)
Chapter 24 Multipurpose Clock Generator (MCG) 24.3.4 MCG Control 4 Register (MCG_C4) NOTE Reset values for DRST and DMX32 bits are 0. Address: 4006_4000h base + 3h offset = 4006_4003h Read DMX32 DRST_DRS FCTRIM SCFTRIM Write Reset * Notes: • x = Undefined at reset. -
Page 494: Mcg Control 5 Register (Mcg_C5)
Memory Map/Register Definition MCG_C4 field descriptions (continued) Field Description Encoding 1 — Mid range. Encoding 2 — Mid-high range. Encoding 3 — High range. 4–1 Fast Internal Reference Clock Trim Setting FCTRIM FCTRIM controls the fast internal reference clock frequency by controlling the fast internal reference clock period. -
Page 495: Mcg Control 6 Register (Mcg_C6)
Chapter 24 Multipurpose Clock Generator (MCG) MCG_C5 field descriptions (continued) Field Description Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit has no affect and does not enable the PLL Clock to run if it is written to 1. -
Page 496: Freescale Semiconductor, Inc
Memory Map/Register Definition MCG_C6 field descriptions (continued) Field Description Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect when LOLS 0 is set. No interrupt request is generated on loss of lock. Generate an interrupt request on loss of lock. -
Page 497: Mcg Status Register (Mcg_S)
Chapter 24 Multipurpose Clock Generator (MCG) 24.3.7 MCG Status Register (MCG_S) Address: 4006_4000h base + 6h offset = 4006_4006h Read LOLS0 LOCK0 PLLST IREFST CLKST OSCINIT0 IRCST Write Reset MCG_S field descriptions Field Description Loss of Lock Status LOLS0 This bit is a sticky bit indicating the lock status for the PLL. LOLS 0 is set if after acquiring lock, the PLL output frequency has fallen outside the lock exit frequency tolerance, D . -
Page 498: Mcg Status And Control Register (Mcg_Sc)
Memory Map/Register Definition MCG_S field descriptions (continued) Field Description 3–2 Clock Mode Status CLKST These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the CLKS bits due to internal synchronization between clock domains. Encoding 0 —... -
Page 499: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) MCG_SC field descriptions (continued) Field Description Automatic Trim Machine Select ATMS Selects the IRCS clock for Auto Trim Test. 32 kHz Internal Reference Clock selected. 4 MHz Internal Reference Clock selected. Automatic Trim Machine Fail Flag ATMF Fail flag for the Automatic Trim Machine (ATM). -
Page 500: Mcg Auto Trim Compare Value High Register (Mcg_Atcvh)
Memory Map/Register Definition 24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH) Address: 4006_4000h base + Ah offset = 4006_400Ah Read ATCVH Write Reset MCG_ATCVH field descriptions Field Description 7–0 ATM Compare Value High ATCVH Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. -
Page 501: Mcg Control 8 Register (Mcg_C8)
Chapter 24 Multipurpose Clock Generator (MCG) MCG_C7 field descriptions Field Description 7–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. MCG OSC Clock Select OSCSEL Selects the MCG FLL external reference clock Selects System Oscillator (OSCCLK). -
Page 502: Functional Description
Functional description MCG_C8 field descriptions (continued) Field Description Loss of RTC has not occur. Loss of RTC has occur 24.4 Functional description 24.4.1 MCG mode state diagram The nine states of the MCG are shown in the following figure and are described in Table 24-16. -
Page 503: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) NOTE • During exits from LLS or VLPS when the MCG is in PEE mode, the MCG will reset to PBE clock mode and the C1[CLKS] and S[CLKST] will automatically be set to 2’b10. •... -
Page 504: Freescale Semiconductor, Inc
Functional description Table 24-16. MCG modes of operation (continued) Mode Description FLL Engaged External FLL engaged external (FEE) mode is entered when all the following conditions occur: (FEE) • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 0 •... -
Page 505: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) Table 24-16. MCG modes of operation (continued) Mode Description PLL Engaged External PLL Engaged External (PEE) mode is entered when all the following conditions occur: (PEE) • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 0 •... -
Page 506: Freescale Semiconductor, Inc
Functional description Table 24-16. MCG modes of operation (continued) Mode Description Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power mode assignments, see the chapter that describes how modules are configured and MCG behavior during Stop recovery. -
Page 507: Low Power Bit Usage
Chapter 24 Multipurpose Clock Generator (MCG) the FLL remains unlocked for several reference cycles. DCO startup time is equal to the FLL acquisition time. After the selected DCO startup time is over, the FLL is locked. The completion of the switch is shown by the C4[DRST_DRS] read bits. 24.4.2 Low Power Bit Usage The C2[LP] bit is provided to allow the FLL or PLL to be disabled and thus conserve power when these systems are not being used. -
Page 508: Mcg Fixed Frequency Clock
Functional description 24.4.4 External Reference Clock The MCG module can support an external reference clock in all modes. See the device datasheet for external reference frequency range. When C1[IREFS] is set, the external reference clock will not be used by the FLL or PLL. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support. -
Page 509: Mcg Auto Trim (Atm)
Chapter 24 Multipurpose Clock Generator (MCG) 24.4.7 MCG Auto TRIM (ATM) The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG hardware to automatically trim the MCG Internal Reference Clocks using an external clock as a reference. The selection between which MCG IRC clock gets tested and enabled is controlled by the ATC[ATMS] control bit (ATC[ATMS]=0 selects the 32 kHz IRC and ATC[ATMS]=1 selects the 4 MHz IRC). -
Page 510: Initialization / Application Information
Initialization / Application information If the auto trim is being performed on the 4 MHz IRC, the calculated expected count value must be multiplied by 128 before storing it in the ATCV register. Therefore, the ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the following formula. -
Page 511: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) appropriately here according to the external reference frequency to keep the FLL reference clock in the range of 31.25 kHz to 39.0625 kHz. Although the FLL is bypassed, it is still on in FBE mode. •... -
Page 512: Using A 32.768 Khz Reference
Initialization / Application information • When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48 MHz. -
Page 513: Mcg Mode Switching
Chapter 24 Multipurpose Clock Generator (MCG) resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bits are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output frequency is 83.89 MHz at high-range. In FBI and FEI modes, setting C4[DMX32] bit is not recommended. -
Page 514: Freescale Semiconductor, Inc
Initialization / Application information Table 24-17. MCGOUTCLK Frequency Calculation Options (continued) Clock Mode Note MCGOUTCLK PBE (PLL bypassed external) / PLL_R must be in the range specified for f in the appropriate pll_ref device Data Sheet BLPI (Bypassed low power internal) BLPE (Bypassed low power external) 1. -
Page 515: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by C2[EREFS0] has been initialized. d. Loop until S[IREFST] is 0, indicating the external reference is the current source for the reference clock. e. Loop until S[CLKST] is 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK. -
Page 516: Freescale Semiconductor, Inc
Initialization / Application information • C1[CLKS] set to 2'b00 to select the output of the PLL as the system clock source. b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode. •... -
Page 517: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) Figure 24-15. Flowchart of FEI to PEE mode transition using an 4 MHz crystal K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 518: Freescale Semiconductor, Inc
Initialization / Application information 24.5.3.2 Example 2: Moving from PEE to BLPI mode: MCGOUTCLK frequency =32 kHz In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency. -
Page 519: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) • C1[IREFS] set to 1 to select the internal reference clock as the reference clock source. • C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference. b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source. -
Page 520: Freescale Semiconductor, Inc
Initialization / Application information START IN PEE MODE C1 = 0x90 CHECK S[PLLST] = 0? CHECK S[CLKST] = %10 ? C1 = 0x54 ENTER CHECK BLPE MODE ? S[IREFST] = 0? C2 = 0x1E (C2[LP] = 1) CHECK S[CLKST] = %01? C6 = 0x00 C2 = 0x02 BLPE MODE ? -
Page 521: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) 24.5.3.3 Example 3: Moving from BLPI to FEE mode In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency. -
Page 522: Freescale Semiconductor, Inc
Initialization / Application information multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. START IN BLPI MODE CHECK S[IREFST] = 0? C2 = 0x00 C2 = 0x1C CHECK... -
Page 523: Oscillator (Osc)
Chapter 25 Oscillator (OSC) 25.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 25.2 Features and Modes Key features of the module are: •... -
Page 524: Block Diagram
Block Diagram 25.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals. Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode. -
Page 525: External Crystal / Resonator Connections
Chapter 25 Oscillator (OSC) Table 25-1. OSC Signal Descriptions Signal Description EXTAL External clock/Oscillator input XTAL Oscillator output 25.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the following figures. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself. -
Page 526: External Clock Connections
External Clock Connections XTAL EXTAL Crystal or Resonator Figure 25-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. XTAL EXTAL Crystal or Resonator Figure 25-4. -
Page 527: Memory Map/Register Definitions
Chapter 25 Oscillator (OSC) XTAL EXTAL Clock Input Figure 25-5. External Clock Connections 25.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. 25.7.1 OSC Memory Map/Register Definition OSC memory map Absolute Width Section/... -
Page 528: Functional Description
Functional Description OSC_CR field descriptions Field Description External Reference Enable ERCLKEN Enables external reference clock (OSCERCLK). External reference clock is inactive. External reference clock is enabled. This field is reserved. Reserved This read-only field is reserved and always has the value 0. External Reference Stop Enable EREFSTEN Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters... -
Page 529: Osc Module States
Chapter 25 Oscillator (OSC) 25.8.1 OSC Module States The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. Oscillator OFF OSCCLK OSC_CLK_OUT = Static not requested OSCCLK requested OSCCLK requested &&... -
Page 530: Osc Module Modes
Functional Description 25.8.1.2 Oscillator Start-Up The OSC enters start-up state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized. -
Page 531: Freescale Semiconductor, Inc
Chapter 25 Oscillator (OSC) Table 25-5. Oscillator Modes Mode Frequency Range Low-frequency, high-gain (1 kHz) up to f (32.768 kHz) osc_lo osc_lo Low-frequency, low-power (VLP) High-frequency mode1, high-gain (3 MHz) up to f (8 MHz) osc_hi_1 osc_hi_1 High-frequency mode1, low-power High-frequency mode2, high-gain (8 MHz) up to f (32 MHz) -
Page 532: Counter
Reset 25.8.2.3 High-Frequency, High-Gain Mode In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. -
Page 533: Low Power Modes Operation
Chapter 25 Oscillator (OSC) 25.10 Low Power Modes Operation When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and EREFSETN bit settings. If both these bits are set, the OSC is in operation. In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If ERCLKEN and EREFSTEN bits are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes. -
Page 534: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Interrupts K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 535: Rtc Oscillator
Chapter 26 RTC Oscillator 26.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The RTC oscillator module provides the clock source for the RTC. The RTC oscillator module, in conjunction with an external crystal, generates a reference clock for the RTC. 26.1.1 Features and Modes The key features of the RTC oscillator are as follows: •... -
Page 536: Rtc Signal Descriptions
RTC Signal Descriptions control Amplitude clk out for RTC EXTAL32 detector XTAL32 Figure 26-1. RTC Oscillator Block Diagram 26.2 RTC Signal Descriptions The following table shows the user-accessible signals available for the RTC oscillator. See the chip-level specification to find out which signals are actually connected to the external pins. -
Page 537: External Crystal Connections
Chapter 26 RTC Oscillator 26.3 External Crystal Connections The connections with a crystal is shown in the following figure. External load capacitors and feedback resistor are not required. RTC Oscillator Module XTAL32 EXTAL32 Crystal or Resonator Figure 26-2. Crystal Connections 26.4 Memory Map/Register Descriptions RTC oscillator control bits are part of the RTC registers. -
Page 538: Reset Overview
Reset Overview 26.6 Reset Overview There is no reset state associated with the RTC oscillator. 26.7 Interrupts The RTC oscillator does not generate any interrupts. K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 539: Flash Memory Controller (Fmc)
Chapter 27 Flash Memory Controller (FMC) 27.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Flash Memory Controller (FMC) is a memory acceleration unit that provides: • an interface between the device and the dual-bank nonvolatile memory. Bank 0 consists of program flash memory, and bank 1 consists of FlexNVM. -
Page 540: Features
Modes of operation 27.1.2 Features The FMC's features include: • Interface between the device and the dual-bank flash memory and FlexMemory: • 8-bit, 16-bit, and 32-bit read operations to program flash memory and FlexNVM used as data flash memory. • 8-bit, 16-bit, and 32-bit read and write operations to FlexNVM and FlexRAM used as EEPROM. -
Page 541: Memory Map And Register Descriptions
Chapter 27 Flash Memory Controller (FMC) 27.4 Memory map and register descriptions The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM). -
Page 542: Freescale Semiconductor, Inc
Memory map and register descriptions Table 27-3. Program visible cache registers Cache Based at Contents of 32-bit read Nomenclature Nomenclature example storage offset 100h 13'h0, tag[18:6], 5'h0, valid In TAGVDWxSy, x denotes the way TAGVDW2S0 is the 13-bit tag and y denotes the set. and 1-bit valid for cache entry way 2, set 0. -
Page 543: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Controller (FMC) FMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4001_F160 Cache Tag Storage (FMC_TAGVDW3S0) 0000_0000h 27.4.7/555 4001_F164 Cache Tag Storage (FMC_TAGVDW3S1) 0000_0000h 27.4.7/555 4001_F168 Cache Tag Storage (FMC_TAGVDW3S2) 0000_0000h 27.4.7/555 4001_F16C Cache Tag Storage (FMC_TAGVDW3S3) -
Page 544: Freescale Semiconductor, Inc
Memory map and register descriptions FMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 27.4.10/ 4001_F260 Cache Data Storage (upper word) (FMC_DATAW1S4U) 0000_0000h 27.4.11/ 4001_F264 Cache Data Storage (lower word) (FMC_DATAW1S4L) 0000_0000h 27.4.10/ 4001_F268 Cache Data Storage (upper word) (FMC_DATAW1S5U) -
Page 545: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Controller (FMC) FMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 27.4.12/ 4001_F2B8 Cache Data Storage (upper word) (FMC_DATAW2S7U) 0000_0000h 27.4.13/ 4001_F2BC Cache Data Storage (lower word) (FMC_DATAW2S7L) 0000_0000h 27.4.14/ 4001_F2C0 Cache Data Storage (upper word) (FMC_DATAW3S0U) -
Page 546: Flash Access Protection Register (Fmc_Pfapr)
Memory map and register descriptions 27.4.1 Flash Access Protection Register (FMC_PFAPR) Address: 4001_F000h base + 0h offset = 4001_F000h Reset M7AP[1:0] M6AP[1:0] M5AP[1:0] M4AP[1:0] M3AP[1:0] M2AP[1:0] M1AP[1:0] M0AP[1:0] Reset FMC_PFAPR field descriptions Field Description 31–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. -
Page 547: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Controller (FMC) FMC_PFAPR field descriptions (continued) Field Description Master 3 Prefetch Disable M3PFD These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. Prefetching for this master is enabled. -
Page 548: Freescale Semiconductor, Inc
Memory map and register descriptions FMC_PFAPR field descriptions (continued) Field Description Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master 9–8 Master 4 Access Protection M4AP[1:0]... -
Page 549: Flash Bank 0 Control Register (Fmc_Pfb0Cr)
Chapter 27 Flash Memory Controller (FMC) 27.4.2 Flash Bank 0 Control Register (FMC_PFB0CR) Address: 4001_F000h base + 4h offset = 4001_F004h B0RWSC[3:0] B0MW[1:0] CLCK_WAY[3:0] S_B_ CINV_WAY[3:0] Reset CRC[2:0] Reset FMC_PFB0CR field descriptions Field Description 31–28 Bank 0 Read Wait State Control B0RWSC[3:0] This read-only field defines the number of wait states required to access the bank 0 flash memory. -
Page 550: Freescale Semiconductor, Inc
Memory map and register descriptions FMC_PFB0CR field descriptions (continued) Field Description These bits determine if the given cache way is to be invalidated (cleared). When a bit within this field is written, the corresponding cache way is immediately invalidated: the way's tag, data, and valid contents are cleared. -
Page 551: Flash Bank 1 Control Register (Fmc_Pfb1Cr)
Chapter 27 Flash Memory Controller (FMC) FMC_PFB0CR field descriptions (continued) Field Description Do not cache instruction fetches. Cache instruction fetches. Bank 0 Data Prefetch Enable B0DPE This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. Do not prefetch in response to data references. -
Page 552: Cache Tag Storage (Fmc_Tagvdw0Sn)
Memory map and register descriptions FMC_PFB1CR field descriptions Field Description 31–28 Bank 1 Read Wait State Control B1RWSC[3:0] This read-only field defines the number of wait states required to access the bank 1 flash memory. The relationship between the read access time of the flash array (expressed in system clock cycles) and RWSC is defined as: Access time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates this value based on the ratio of the system clock speed to the flash... -
Page 553: Cache Tag Storage (Fmc_Tagvdw1Sn)
Chapter 27 Flash Memory Controller (FMC) FMC_TAGVDW0Sn field descriptions Field Description 31–19 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 18–6 13-bit tag for cache entry tag[18:6] 5–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. -
Page 554: Cache Tag Storage (Fmc_Tagvdw2Sn)
Memory map and register descriptions 27.4.6 Cache Tag Storage (FMC_TAGVDW2Sn) The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. -
Page 555: Cache Tag Storage (Fmc_Tagvdw3Sn)
Chapter 27 Flash Memory Controller (FMC) 27.4.7 Cache Tag Storage (FMC_TAGVDW3Sn) The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. -
Page 556: Cache Data Storage (Lower Word) (Fmc_Dataw0Snl)
Memory map and register descriptions FMC_DATAW0SnU field descriptions Field Description 31–0 Bits [63:32] of data entry data[63:32] 27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. -
Page 557: Cache Data Storage (Lower Word) (Fmc_Dataw1Snl)
Chapter 27 Flash Memory Controller (FMC) FMC_DATAW1SnU field descriptions Field Description 31–0 Bits [63:32] of data entry data[63:32] 27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. -
Page 558: Cache Data Storage (Lower Word) (Fmc_Dataw2Snl)
Memory map and register descriptions FMC_DATAW2SnU field descriptions Field Description 31–0 Bits [63:32] of data entry data[63:32] 27.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. -
Page 559: Cache Data Storage (Lower Word) (Fmc_Dataw3Snl)
Chapter 27 Flash Memory Controller (FMC) FMC_DATAW3SnU field descriptions Field Description 31–0 Bits [63:32] of data entry data[63:32] 27.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. -
Page 560: Configuration Options
Functional description • These masters have write access to a portion of bank 1 when FlexNVM is used with FlexRAM as EEPROM. • For bank 0: • Prefetch support for data and instructions is enabled for crossbar masters 0, 1, 2. •... -
Page 561: Speculative Reads
Chapter 27 Flash Memory Controller (FMC) 2. the phase relationship of the core clock and flash clock at the time the read is requested. The ratio of the core clock to the flash clock is equal to the value of PFB0CR[B0RWSC] + 1 for bank 0 and to the value of PFB1CR[B1RWSC] + 1 for bank 1. -
Page 562: Initialization And Application Information
Initialization and application information • The core requests four sequential longwords in back-to-back requests, meaning there are no core cycle delays except for stalls waiting for flash memory data to be returned. • None of the data is already stored in the cache or speculation buffer. In this scenario, the sequence of events for accessing the four longwords is as follows: 1. -
Page 563: Flash Memory Module (Ftfl)
Chapter 28 Flash Memory Module (FTFL) 28.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The flash memory module includes the following accessible memory regions: • Program flash memory for vector space and code store •... -
Page 564: Features
Introduction states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. 28.1.1 Features The flash memory module includes the following features. NOTE See the device's Chip Configuration details for the exact amount of flash memory available on your device. -
Page 565: Block Diagram
Chapter 28 Flash Memory Module (FTFL) 28.1.1.3 FlexRAM Features • Memory that can be used as traditional RAM or as high-endurance EEPROM storage • Up to 2 Kbytes of FlexRAM configured for EEPROM or traditional RAM operations • When configured for EEPROM: •... -
Page 566: Glossary
Introduction Interrupt Program flash Status Register access registers Memory controller Control registers To MCU's flash controller FlexNVM Data flash FlexRAM EEPROM backup Figure 28-1. Flash Block Diagram 28.1.3 Glossary Command write sequence — A series of MCU writes to the flash FCCOB register group that initiates and controls the execution of flash algorithms that are built into the flash memory module. -
Page 567: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) EEPROM backup data record — The EEPROM backup data record is comprised of a 2-bit status field, a 14-bit address field, and a 16-bit data field found in EEPROM backup data memory which is used by the EEPROM filing system. If the status field indicates a record is valid, the data field is mirrored in the FlexRAM at a location determined by the address field. -
Page 568: External Signal Description
External Signal Description NVM Special Mode — An NVM mode enabling external, off-chip access to the memory resources in the flash memory module. A reduced flash command set is available when the MCU is secured. See the Chip Configuration details for information on when this mode is used. -
Page 569: Flash Configuration Field Description
Chapter 28 Flash Memory Module (FTFL) 28.3.1 Flash Configuration Field Description The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the flash memory module. Flash Configuration Field Byte Size (Bytes) Field Description... -
Page 570: Data Flash Ifr Map
Memory Map and Registers 28.3.2.1 Program Once Field The Program Once Field in the program flash IFR provides 64 bytes of user data storage separate from the program flash main array. The user can program the Program Once Field one time only as there is no program flash IFR erase mechanism available to the user. -
Page 571: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) Table 28-2. EEPROM Data Set Size Field Description Field Description This read-only bitfield is reserved and must always be written as one. Reserved EEPROM Size — Encoding of the total available FlexRAM for EEPROM use. EEESIZE NOTE: EEESIZE must be 0 bytes (1111b) when the FlexNVM partition code (FlexNVM Partition... -
Page 572: Register Descriptions
Memory Map and Registers Table 28-4. FlexNVM Partition Code Field Description Field Description This read-only bitfield is reserved and must always be written as one. Reserved FlexNVM Partition Code — Encoding of the data flash / EEPROM backup split within the FlexNVM memory block. -
Page 573: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) FTFL memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 28.34.1/ 4002_0000 Flash Status Register (FTFL_FSTAT) 28.34.2/ 4002_0001 Flash Configuration Register (FTFL_FCNFG) 28.34.3/ 4002_0002 Flash Security Register (FTFL_FSEC) Undefined 28.34.4/ 4002_0003... -
Page 574: Freescale Semiconductor, Inc
Memory Map and Registers 28.34.1 Flash Status Register (FTFL_FSTAT) The FSTAT register reports the operational status of the flash memory module. The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. NOTE When set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this register prevent the launch of... -
Page 575: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) FTFL_FSTAT field descriptions (continued) Field Description CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the ACCERR bit has no effect. No access error detected Access error detected Flash Protection Violation Flag... -
Page 576: Freescale Semiconductor, Inc
Memory Map and Registers FTFL_FCNFG field descriptions Field Description Command Complete Interrupt Enable CCIE The CCIE bit controls interrupt generation when a flash command completes. Command complete interrupt disabled Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. -
Page 577: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) FTFL_FCNFG field descriptions (continued) Field Description FlexRAM is not available for traditional RAM access. FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations. This flag indicates if the EEPROM backup data has been copied to the FlexRAM and is therefore available EEERDY for read access. -
Page 578: Freescale Semiconductor, Inc
Memory Map and Registers FTFL_FSEC field descriptions (continued) Field Description 5–4 Mass Erase Enable Bits MEEN Enables and disables mass erase capability of the flash memory module. The state of the MEEN bits is only relevant when the SEC bits are set to secure outside of NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does not matter. -
Page 579: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) Address: 4002_0000h base + 3h offset = 4002_0003h Read Write Reset * Notes: • x = Undefined at reset. FTFL_FOPT field descriptions Field Description 7–0 Nonvolatile Option These bits are loaded from flash to this register at reset. Refer to the device's Chip Configuration details for the definition and use of these bits. -
Page 580: Freescale Semiconductor, Inc
Memory Map and Registers FTFL_FCCOBn field descriptions (continued) Field Description NOTE: The command parameter table is written in terms of FCCOB Number (which is equivalent to the byte number). This number is a reference to the FCCOB register name and is not the register address. -
Page 581: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) During the reset sequence, the FPROT registers are loaded with the contents of the program flash protection bytes in the Flash Configuration Field as indicated in the following table. Program flash protection register Flash Configuration Field offset address FPROT0 0x0008 FPROT1... -
Page 582: Freescale Semiconductor, Inc
Memory Map and Registers 28.34.7 EEPROM Protection Register (FTFL_FEPROT) The FEPROT register defines which EEPROM regions of the FlexRAM are protected against program and erase operations. Protected EEPROM regions cannot have their content changed by writing to it. Unprotected regions can be changed by writing to the FlexRAM. -
Page 583: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) 28.34.8 Data Flash Protection Register (FTFL_FDPROT) The FDPROT register defines which data flash regions are protected against program and erase operations. Protected Flash regions cannot have their content changed; that is, these regions cannot be programmed and cannot be erased by any flash command. Unprotected regions can be changed by both program and erase operations. -
Page 584: Functional Description
Functional Description 28.4 Functional Description The following sections describe functional details of the flash memory module. 28.4.1 Flash Protection Individual regions within the flash memory can be protected from program and erase operations. Protection is controlled by the following registers: •... -
Page 585: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) FlexNVM 0x0_0000 Data flash size / 8 DPROT0 Data flash size / 8 DPROT1 Data flash size / 8 DPROT2 Data flash size / 8 DPROT3 Data flash size / 8 DPROT4 Data flash size / 8 DPROT5 Data flash size / 8 DPROT6... -
Page 586: Flexnvm Description
Functional Description 28.4.2 FlexNVM Description This section describes the FlexNVM memory. 28.4.2.1 FlexNVM Block Partitioning for FlexRAM The user can configure the FlexNVM block as either: • Basic data flash, • EEPROM flash records to support the built-in EEPROM feature, or •... -
Page 587: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) configured for EEPROM (see Set FlexRAM Function Command). The EEPROM partition grows upward from the bottom of the FlexRAM address space. 2. Data flash partition (DEPART) — The amount of FlexNVM memory used for data flash can be programmed from 0 bytes (all of the FlexNVM block is available for EEPROM backup) to the maximum size of the FlexNVM block (see Table... -
Page 588: Freescale Semiconductor, Inc
Functional Description and copies the newest data to FlexRAM. The FSTAT[CCIF] and FCNFG[EEERDY] bits are set after data from all valid EEPROM data records is copied to the FlexRAM. After the CCIF bit is set, the FlexRAM is available for read or write access. When configured for EEPROM use, writes to an unprotected location in FlexRAM invokes the EEPROM file system to program a new EEPROM data record in the EEPROM backup memory in a round-robin fashion. -
Page 589: Interrupts
Chapter 28 Flash Memory Module (FTFL) • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • n — data flash cycling endurance nvmcycd Figure 28-31. EEPROM backup writes to FlexRAM 28.4.3 Interrupts The flash memory module can generate interrupt requests to the MCU upon the occurrence of various flash events. -
Page 590: Flash Operation In Low-Power Modes
Functional Description Note Vector addresses and their relative interrupt priority are determined at the MCU level. 28.4.4 Flash Operation in Low-Power Modes 28.4.4.1 Wait Mode When the MCU enters wait mode, the flash memory module is not affected. The flash memory module can recover the MCU from wait via the command complete interrupt (see Interrupts). -
Page 591: Read While Write (Rww)
Chapter 28 Flash Memory Module (FTFL) The MCU must not read from the flash memory while commands are running (as evidenced by CCIF=0) on that block. Read data cannot be guaranteed from a flash block while any command is processing within that block. The block arbitration logic detects any simultaneous access and reports this as a read collision error (see the FSTAT[RDCOLERR] bit). -
Page 592: Freescale Semiconductor, Inc
Functional Description • The command write sequence used to set flash command parameters and launch execution • A description of all flash commands available 28.4.9.1 Command Write Sequence Flash commands are specified using a command write sequence illustrated in Figure 28-32. -
Page 593: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) If the parameter check fails, the FSTAT[ACCERR] (access error) flag is set. ACCERR reports invalid instruction codes and out-of bounds addresses. Usually, access errors suggest that the command was not set-up with valid parameters in the FCCOB register group. -
Page 594: Freescale Semiconductor, Inc
Functional Description START Read: FSTAT register FCCOB Availability Check CCIF Previous command complete? = ‘1’? Results from previous command Access Error and ACCERR/ Protection Violation Clear the old errors FPVIOL Check Write 0x30 to FSTAT register Set? Write to the FCCOB registers to load the required command parameter. -
Page 595: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) FCMD Command Program flash Data flash FlexRAM Function 0x01 Read 1s Section × × Verify that a given number of program flash or data flash locations from a starting address are erased. 0x02 Program Check ×... -
Page 596: Freescale Semiconductor, Inc
Functional Description FCMD Command Program flash Data flash FlexRAM Function 0x43 Program Once One-time program of 4 bytes of a dedicated 64-byte field in the program flash IFR. 0x44 Erase All Blocks × × × Erase all program flash blocks, data flash blocks, FlexRAM, EEPROM backup... -
Page 597: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) 28.4.9.3 Flash Commands by Mode The following table shows the flash commands that can be executed in each flash operating mode. Table 28-31. Flash Commands by Mode NVM Normal NVM Special FCMD Command Unsecure Secure MEEN=10 Unsecure... -
Page 598: Margin Read Commands
Functional Description Table 28-32. Allowed Simultaneous Memory Operations Program Flash Data Flash FlexRAM Sector Sector Read Program Read Program Read E-Write R-Write Erase Erase Read — Program Program — flash Sector — Erase Read — Data Program — flash Sector —... -
Page 599: Flash Command Description
Chapter 28 Flash Memory Module (FTFL) The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss. The 'user' margin is a small delta to the normal read reference level. -
Page 600: Freescale Semiconductor, Inc
Functional Description • program flash (=0) block • data flash (=1) block CAUTION Flash data must be in the erased state before being programmed. Cumulative programming of bits (adding more zeros) is not allowed. 28.4.11.1 Read 1s Block Command The Read 1s Block command checks to see if an entire program flash or data flash block has been erased to the specified margin level. -
Page 601: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) Table 28-35. Read 1s Block Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin choice is specified FSTAT[ACCERR] Program flash is selected and the address is out of program flash range FSTAT[ACCERR] Data flash is selected and the address is out of data flash range FSTAT[ACCERR]... -
Page 602: Freescale Semiconductor, Inc
Functional Description Upon clearing CCIF to launch the Read 1s Section command, the flash memory module sets the read margin for 1s according to Table 28-38 and then reads all locations within the specified section of flash memory. If the flash memory module fails to read all 1s (i.e. the flash section is not erased), the FSTAT(MGSTAT0) bit is set. -
Page 603: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) Upon clearing CCIF to launch the Program Check command, the flash memory module sets the read margin for 1s according to Table 28-41, reads the specified longword, and compares the actual read data to the expected data provided by the FCCOB. If the comparison at margin-1 fails, the MGSTAT0 bit is set. -
Page 604: Freescale Semiconductor, Inc
Functional Description Table 28-43. Read Resource Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x03 (RDRSRC) Flash address [23:16] Flash address [15:8] Flash address [7:0] Returned Values Read Data [31:24] Read Data [23:16] Read Data [15:8] Read Data [7:0] User-provided values Resource Select Code (see Table 28-44) -
Page 605: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) CAUTION A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-to- back program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device. -
Page 606: Freescale Semiconductor, Inc
Functional Description Table 28-47. Program Longword Command Error Handling (continued) Error Condition Error Bit Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 28.4.11.6 Erase Flash Block Command The Erase Flash Block operation erases all addresses in a single program flash or data flash block. -
Page 607: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) 28.4.11.7 Erase Flash Sector Command The Erase Flash Sector operation erases all addresses in a flash sector. Table 28-50. Erase Flash Sector Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x09 (ERSSCR) Flash address [23:16] in the flash sector to be erased Flash address [15:8] in the flash sector to be erased Flash address [7:0] in the flash sector to be erased... -
Page 608: Freescale Semiconductor, Inc
Functional Description If an Erase Flash Sector operation effectively completes before the flash memory module detects that a suspend request has been made, the flash memory module clears the ERSSUSP bit prior to setting CCIF. When an Erase Flash Sector operation has been successfully suspended, the flash memory module sets CCIF and leaves the ERSSUSP bit set. -
Page 609: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) Enter with CCIF = 1 Command Initiation ERSSCR Command (Write FCCOB) Memory Controller Command Processing Launch/Resume Command (Clear CCIF) Resume ERSSCR SUSPACK=1 Next Command CCIF = 1? (Write FCCOB) Restore Erase Algo Start Clear SUSPACK = 0 Interrupt? Execute DONE? -
Page 610: Freescale Semiconductor, Inc
Functional Description 28.4.11.8 Program Section Command The Program Section operation programs the data found in the section program buffer to previously erased locations in the flash memory using an embedded algorithm. Data is preloaded into the section program buffer by writing to the FlexRAM while it is set to function as traditional RAM (see Flash Sector Programming). -
Page 611: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) The starting address must be unprotected (see the description of the FPROT and FDPROT registers) to permit execution of the Program Section operation. Programming, which is not allowed to cross a flash sector boundary, continues until all requested phrases or longwords have been programmed. -
Page 612: Freescale Semiconductor, Inc
Functional Description 5. If a flash sector is larger than half the FlexRAM, repeat steps until the sector is completely programmed. 6. To program additional flash sectors, repeat steps through 4. 7. To restore EEPROM functionality, execute the Set FlexRAM Function command to make the FlexRAM available as EEPROM. -
Page 613: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) Table 28-57. Read 1s All Blocks Command Error Handling Error Condition Error Bit An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] 28.4.11.10 Read Once Command The Read Once command provides read access to a reserved 64-byte field located in the program flash IFR (see Program Flash IFR Map Program Once... -
Page 614: Freescale Semiconductor, Inc
Functional Description 28.4.11.11 Program Once Command The Program Once command enables programming to a reserved 64-byte field in the program flash IFR (see Program Flash IFR Map Program Once Field). Access to the Program Once field is via 16 records, each 4 bytes long. The Program Once field can be read using the Read Once command (see Read Once Command) or using the Read... -
Page 615: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) 28.4.11.12 Erase All Blocks Command The Erase All Blocks operation erases all flash memory, initializes the FlexRAM, verifies all memory contents, and releases MCU security. Table 28-62. Erase All Blocks Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x44 (ERSALL) After clearing CCIF to launch the Erase All Blocks command, the flash memory module... -
Page 616: Freescale Semiconductor, Inc
Functional Description erase-all request is reflected in the FCNFG[ERSAREQ] bit. The FCNFG[ERSAREQ] bit is cleared once the operation completes and the normal FSTAT error reporting is available as described in Erase All Blocks Command. 28.4.11.13 Verify Backdoor Access Key Command The Verify Backdoor Access Key command only executes if the mode and security conditions are satisfied (see Flash Commands by... -
Page 617: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) Table 28-65. Verify Backdoor Access Key Command Error Handling Error Condition Error Bit The supplied key is all-0s or all-Fs FSTAT[ACCERR] An incorrect backdoor key is supplied FSTAT[ACCERR] Backdoor key access has not been enabled (see the description of the FSEC register) FSTAT[ACCERR] This command is launched and the backdoor key has mismatched since the last power down FSTAT[ACCERR]... -
Page 618: Freescale Semiconductor, Inc
Functional Description Table 28-67. Valid EEPROM Data Set Size Codes (continued) EEPROM Data Size Code (FCCOB4) EEPROM Data Set Size (Bytes) FCCOB4[5:4] FCCOB4[EEESIZE] 1024 2048 1. FCCOB4[7:6] = 00 2. EEPROM Data Set Size must be set to 0 bytes when the FlexNVM Partition Code is set for no EEPROM. Table 28-68. -
Page 619: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) Table 28-69. Program Partition Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] The EEPROM data size and FlexNVM partition code bytes are not initially 0xFFFF FSTAT[ACCERR] Invalid EEPROM Data Size Code is entered (see Table 28-67 for valid codes) FSTAT[ACCERR]... -
Page 620: Security
Functional Description After clearing CCIF to launch the Set FlexRAM Function command, the flash memory module sets the function of the FlexRAM based on the FlexRAM Function Control Code. When making the FlexRAM available as traditional RAM, the flash memory module clears the FCNFG[EEERDY] and FCNFG[RAMRDY] flags, overwrites the contents of the entire FlexRAM with a background pattern of all ones, and sets the FCNFG[RAMRDY] flag. -
Page 621: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) Table 28-73. FSEC register fields FSEC field Description KEYEN Backdoor Key Access MEEN Mass Erase Capability FSLACC Freescale Factory Access MCU security 28.4.12.1 Flash Memory Access by Mode and Security The following table summarizes how access to the flash memory module is affected by security and operating mode. -
Page 622: Reset Sequence
Functional Description Backdoor Access Key command as valid comparison values. While the Verify Backdoor Access Key command is active, program flash memory is not available for read access and returns invalid data. The user code stored in the program flash memory must have a method of receiving the backdoor keys from an external stimulus. -
Page 623: Freescale Semiconductor, Inc
Chapter 28 Flash Memory Module (FTFL) CCIF is cleared throughout the reset sequence. The flash memory module holds off CPU access during the reset sequence. Flash reads are possible when the hold is removed. Completion of the reset sequence is marked by setting CCIF which enables flash user commands. -
Page 624: Freescale Semiconductor, Inc
Functional Description K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 625: Overview
Chapter 29 EzPort 29.1 Overview NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The EzPort module is a serial flash programming interface that allows In-System Programming (ISP) of flash memory contents on a 32 bit general-purpose microcontroller. -
Page 626: Features
Overview EzPort Enabled EZP_CS EZP_CK Flash EzPort Controller EZP_D EZP_Q Reset Flash Memory Reset Out Reset Controller Microcontroller Core Figure 29-1. EzPort block diagram 29.1.2 Features EzPort includes the following features: • Serial interface that is compatible with a subset of the SPI format. •... -
Page 627: External Signal Description
Chapter 29 EzPort The EzPort provides a simple interface to connect an external device to the flash memory on board a 32 bit microcontroller. The interface itself is compatible with the SPI interface, with the EzPort operating as a slave, running in either of the two following modes. -
Page 628: Ezport Serial Data In (Ezp_D)
Command definition 29.2.2 EzPort Chip Select (EZP_CS) EZP_CS is the chip select for signaling the start and end of serial transfers. If, while EZP_CS is asserted, the microcontroller's reset out signal is negated, EzPort is enabled out of reset; otherwise it is disabled. After EzPort is enabled, asserting EZP_CS commences a serial data transfer, which continues until EZP_CS is negated again. -
Page 629: Command Descriptions
Chapter 29 EzPort Table 29-2. EzPort commands (continued) Address Accepted when Command Description Code Data Bytes Bytes secure? Read FCCOB registers at high FAST_RDFCCOB 0xBB 1 - 12 speed WRFLEXRAM Write FlexRAM 0xBC RDFLEXRAM Read FlexRAM 0xBD FAST_RDFLEXRAM Read FlexRAM at high speed 0xBE 1. -
Page 630: Freescale Semiconductor, Inc
Command definition Table 29-3. EzPort status register FLEXRAM BEDIS Reset: 1. Reset value reflects the status of flash security out of reset. 2. Reset value reflects FlexNVM flash partitioning. If FlexNVM flash has been paritioned for EEPROM, this field is set immediately after reset. -
Page 631: Freescale Semiconductor, Inc
Chapter 29 EzPort Table 29-4. EzPort status register field description (continued) Field Description Write error flag Indicates whether there has been an error while executing a write command (SP, SE, BE, WRFCCOB, or WRFLEXRAM). The WEF flag will set if Flash Access Error Flag (ACCERR), Flash Protection Violation (FPVIOL), or Memory Controller Command Completion Status (MGSTAT0) inside the flash memory is set at the completion of the write command. -
Page 632: Freescale Semiconductor, Inc
Command definition 29.3.1.6 Section Program The Section Program (SP) command programs up to one section of flash memory that has previously been erased. Please see the Flash Memory chapter for a definition of section size. The starting address of the memory to program is sent after the command word and must be a 64-bit aligned address with the three LSBs being zero). -
Page 633: Freescale Semiconductor, Inc
Chapter 29 EzPort 29.3.1.8 Bulk Erase The Bulk Erase (BE) command erases the entire contents of flash memory, ignoring any protected sectors or flash security. Flash security is disabled upon successful completion of the BE command. Attempts to issue a BE command while the BEDIS and FS fields are set results in the WEF flag being set in the EzPort status register. -
Page 634: Freescale Semiconductor, Inc
Command definition 29.3.1.11 Read FCCOB Registers at High Speed The Read FCCOB Registers at High Speed (FAST_RDFCCOB) command allows the user to read the contents of the flash common command object registers. After receiving the command, EzPort waits for one dummy byte of data before returning FCCOB register data starting at FCCOB 0 and ending with FCCOB B. -
Page 635: Flash Memory Map For Ezport Access
Chapter 29 EzPort Data continues being returned for as long as the EzPort chip select (EZP_CS) is asserted, with the address automatically incrementing. In this way, the entire contents of FlexRAM can be returned by one command. The initial address must be 32-bit aligned (the two LSBs must be zero). Attempts to read from an address which does not fall within the valid address range for the FlexRAM returns unknown data. -
Page 636: Freescale Semiconductor, Inc
Flash memory map for EzPort access K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 637: Cyclic Redundancy Check (Crc)
Chapter 30 Cyclic Redundancy Check (CRC) 30.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The cyclic redundancy check (CRC) module generates 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. -
Page 638: Block Diagram
Memory map and register descriptions 30.1.2 Block diagram The following is a block diagram of the CRC. FXOR TOTR CRC Data Register [31:24] CRC Data Register Seed Reverse [23:16] [31:24] Logic [15:8] Reverse [23:16] CRC Data [7:0] Logic Logic [15:8] [7:0] Checksum CRC Polynomial... -
Page 639: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Chapter 30 Cyclic Redundancy Check (CRC) 30.2.1 CRC Data register (CRC_CRC) The CRC Data register contains the value of the seed, data, and checksum. When CTRL[WAS] is set, any write to the data register is regarded as the seed value. When CTRL[WAS] is cleared, any write to the data register is regarded as data for general CRC computation. -
Page 640: Crc Polynomial Register (Crc_Gpoly)
Memory map and register descriptions 30.2.2 CRC Polynomial register (CRC_GPOLY) This register contains the value of the polynomial for the CRC calculation. The HIGH field contains the upper 16 bits of the CRC polynomial, which are used only in 32-bit CRC mode. -
Page 641: Functional Description
Chapter 30 Cyclic Redundancy Check (CRC) CRC_CTRL field descriptions Field Description 31–30 Type Of Transpose For Writes Define the transpose configuration of the data written to the CRC data register. See the description of the transpose feature for the available transpose options. No transposition. -
Page 642: Crc Initialization/Reinitialization
Functional description 30.3.1 CRC initialization/reinitialization To enable the CRC calculation, the user must program the WAS, POLYNOMIAL, and necessary parameters for transpose and CRC result inversion in the applicable registers. Asserting CTRL[WAS] enables the programming of the seed value into the CRC data register. -
Page 643: Transpose Feature
Chapter 30 Cyclic Redundancy Check (CRC) 1. Set CTRL[TCRC] to enable 32-bit CRC mode. 2. Program the transpose and complement options in the CTRL register as required for the CRC calculation. See Transpose feature CRC result complement for details. 3. Write a 32-bit polynomial to GPOLY[HIGH:LOW]. 4. -
Page 644: Freescale Semiconductor, Inc
Functional description Bits in a byte are transposed, while bytes are not transposed. reg[31:0] becomes {reg[24:31], reg[16:23], reg[8:15], reg[0:7]} Figure 30-5. Transpose type 01 3. CTRL[TOT] or CTRL[TOTR] is 10 Both bits in bytes and bytes are transposed. reg[31:0] becomes = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 30-6. -
Page 645: Crc Result Complement
Chapter 30 Cyclic Redundancy Check (CRC) NOTE For 8-bit and 16-bit write accesses to the CRC data register, the data is transposed with zeros on the unused byte or bytes (taking 32 bits as a whole), but the CRC is calculated on the valid byte(s) only. -
Page 646: Freescale Semiconductor, Inc
Functional description K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 647: Introduction
Chapter 31 Analog-to-Digital Converter (ADC) 31.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The 16-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE For the chip specific modes of operation, see the power management information of the device. -
Page 648: Block Diagram
Introduction • Configurable sample time and conversion speed/power • Conversion complete/hardware average complete flag and interrupt • Input clock selectable from up to four sources • Operation in Low-Power modes for lower noise • Asynchronous clock source for lower noise operation with option to output the clock •... -
Page 649: Adc Signal Descriptions
Chapter 31 Analog-to-Digital Converter (ADC) ADHWTSA SC1A Conversion trigger SC1n ADHWTSn control A D T R G ADHWT (SC2, CFG1, CFG2) C o m p a re tru e Control Registers A D A C K E N Async Clock Gen Interrupt ADACK Clock... -
Page 650: Voltage Reference Select
ADC Signal Descriptions Table 31-1. ADC Signal Descriptions (continued) Signal Description DADM3–DADM0 Differential Analog Channel Inputs AD23–AD4 Single-Ended Analog Channel Inputs Voltage Reference Select High REFSH Voltage Reference Select Low REFSL Analog Power Supply Analog Ground 31.2.1 Analog Power (V The ADC analog portion uses V as its power connection. -
Page 651: Analog Channel Inputs (Adx)
Chapter 31 Analog-to-Digital Converter (ADC) In some packages, V is connected in the package to V and V to V . If REFH REFL externally available, the positive reference(s) may be connected to the same potential as or may be driven by an external source to a level between the minimum Ref Voltage High and the V potential. -
Page 652: Freescale Semiconductor, Inc
Register definition ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_B020 Status and Control Register 2 (ADC0_SC2) 0000_0000h 31.3.6/661 4003_B024 Status and Control Register 3 (ADC0_SC3) 0000_0000h 31.3.7/663 4003_B028 ADC Offset Correction Register (ADC0_OFS) 0000_0004h 31.3.8/665 4003_B02C ADC Plus-Side Gain Register (ADC0_PG) -
Page 653: Adc Status And Control Registers 1 (Adcx_Sc1N)
Chapter 31 Analog-to-Digital Converter (ADC) ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 400B_B01C Compare Value Registers (ADC1_CV2) 0000_0000h 31.3.5/660 400B_B020 Status and Control Register 2 (ADC1_SC2) 0000_0000h 31.3.6/661 400B_B024 Status and Control Register 3 (ADC1_SC3) 0000_0000h 31.3.7/663 400B_B028 ADC Offset Correction Register (ADC1_OFS) -
Page 654: Freescale Semiconductor, Inc
Register definition To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more then one status and control register: one for each conversion. The SC1B–SC1n registers indicate potentially multiple SC1 registers for use only in hardware trigger mode. -
Page 655: Freescale Semiconductor, Inc
Chapter 31 Analog-to-Digital Converter (ADC) ADCx_SC1n field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Conversion Complete Flag COCO This is a read-only field that is set each time a conversion is completed when the compare function is disabled, or SC2[ACFE]=0 and the hardware average function is disabled, or SC3[AVGE]=0. -
Page 656: Adc Configuration Register 1 (Adcx_Cfg1)
Register definition ADCx_SC1n field descriptions (continued) Field Description 01100 When DIFF=0, AD12 is selected as input ; when DIFF=1, it is reserved . 01101 When DIFF=0, AD13 is selected as input ; when DIFF=1, it is reserved . 01110 When DIFF=0, AD14 is selected as input ; when DIFF=1, it is reserved . 01111 When DIFF=0, AD15 is selected as input ;... -
Page 657: Freescale Semiconductor, Inc
Chapter 31 Analog-to-Digital Converter (ADC) ADCx_CFG1 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Low-Power Configuration ADLPC Controls the power configuration of the successive approximation converter. This optimizes power consumption when higher sample rates are not required. -
Page 658: Adc Configuration Register 2 (Adcx_Cfg2)
Register definition 31.3.3 ADC Configuration Register 2 (ADCx_CFG2) Configuration Register 2 (CFG2) selects the special high-speed configuration for very high speed conversions and selects the long sample time duration during long sample mode. Address: Base address + Ch offset Reset ADLSTS Reset ADCx_CFG2 field descriptions... -
Page 659: Adc Data Result Register (Adcx_Rn)
Chapter 31 Analog-to-Digital Converter (ADC) ADCx_CFG2 field descriptions (continued) Field Description Normal conversion sequence selected. High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. 1–0 Long Sample Time Select ADLSTS Selects between the extended sample times when long sample time is selected, that is, when CFG1[ADLSMP]=1. -
Page 660: Compare Value Registers (Adcx_Cvn)
Register definition Table 31-44. Data result register description (continued) Conversion D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Format mode 9-bit differential Sign-extended 2's complement 8-bit single- Unsigned right- ended justified NOTE S: Sign bit or sign bit extension;... -
Page 661: Status And Control Register 2 (Adcx_Sc2)
Chapter 31 Analog-to-Digital Converter (ADC) ADCx_CVn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Compare Value. 31.3.6 Status and Control Register 2 (ADCx_SC2) The status and control register 2 (SC2) contains the conversion active, hardware/software trigger select, compare function, and voltage reference select of the ADC module. -
Page 662: Freescale Semiconductor, Inc
Register definition ADCx_SC2 field descriptions (continued) Field Description Indicates that a conversion or hardware averaging is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted. Conversion not in progress. Conversion in progress. Conversion Trigger Select ADTRG Selects the type of trigger used for initiating a conversion. -
Page 663: Status And Control Register 3 (Adcx_Sc3)
Chapter 31 Analog-to-Digital Converter (ADC) ADCx_SC2 field descriptions (continued) Field Description Reserved Reserved 31.3.7 Status and Control Register 3 (ADCx_SC3) The Status and Control Register 3 (SC3) controls the calibration, continuous convert, and hardware averaging functions of the ADC module. Address: Base address + 24h offset Reset AVGS... -
Page 664: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Register definition ADCx_SC3 field descriptions (continued) Field Description calibration sequence. Once started, the calibration routine cannot be interrupted by writes to the ADC registers or the results will be invalid and CALF will set. Setting CAL will abort any current conversion. Calibration Failed Flag CALF Displays the result of the calibration sequence. -
Page 665: Adc Offset Correction Register (Adcx_Ofs)
Chapter 31 Analog-to-Digital Converter (ADC) 31.3.8 ADC Offset Correction Register (ADCx_OFS) The ADC Offset Correction Register (OFS) contains the user-selected or calibration- generated offset error correction value. This register is a 2’s complement, left-justified, 16-bit value . The value in OFS is subtracted from the conversion and the result is transferred into the result registers, Rn. -
Page 666: Adc Minus-Side Gain Register (Adcx_Mg)
Register definition ADCx_PG field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Plus-Side Gain 31.3.10 ADC Minus-Side Gain Register (ADCx_MG) The Minus-Side Gain Register (MG) contains the gain error correction for the minus-side input in differential mode. -
Page 667: Adc Plus-Side General Calibration Value Register (Adcx_Clps)
Chapter 31 Analog-to-Digital Converter (ADC) Address: Base address + 34h offset CLPD Reset ADCx_CLPD field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLPD 31.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS) For more information, see CLPD register description. -
Page 668: Adc Plus-Side General Calibration Value Register (Adcx_Clp3)
Register definition ADCx_CLP4 field descriptions Field Description 31–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 9–0 Calibration Value CLP4 31.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3) For more information, see CLPD register description. Address: Base address + 40h offset CLP3 Reset... -
Page 669: Adc Plus-Side General Calibration Value Register (Adcx_Clp1)
Chapter 31 Analog-to-Digital Converter (ADC) 31.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1) For more information, see CLPD register description. Address: Base address + 48h offset CLP1 Reset ADCx_CLP1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–0 Calibration Value CLP1... -
Page 670: Adc Pga Register (Adcx_Pga)
Register definition 31.3.18 ADC PGA Register (ADCx_PGA) Address: Base address + 50h offset PGAG Reset Reset ADCx_PGA field descriptions Field Description 31–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. PGA Enable PGAEN PGA disabled. -
Page 671: Adc Minus-Side General Calibration Value Register (Adcx_Clmd)
Chapter 31 Analog-to-Digital Converter (ADC) ADCx_PGA field descriptions (continued) Field Description 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved 15–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 31.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMD) The Minus-Side General Calibration Value (CLMx) registers contain calibration... -
Page 672: Adc Minus-Side General Calibration Value Register (Adcx_Clms)
Register definition 31.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLMS) For more information, see CLMD register description. Address: Base address + 58h offset CLMS Reset ADCx_CLMS field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLMS... -
Page 673: Adc Minus-Side General Calibration Value Register (Adcx_Clm3)
Chapter 31 Analog-to-Digital Converter (ADC) 31.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM3) For more information, see CLMD register description. Address: Base address + 60h offset CLM3 Reset ADCx_CLM3 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 8–0 Calibration Value CLM3... -
Page 674: Adc Minus-Side General Calibration Value Register (Adcx_Clm1)
Functional description 31.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM1) For more information, see CLMD register description. Address: Base address + 68h offset CLM1 Reset ADCx_CLM1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–0 Calibration Value CLM1... -
Page 675: Pga Functional Description
Chapter 31 Analog-to-Digital Converter (ADC) initiated. When it is idle and the asynchronous clock output enable is disabled, or CFG2[ADACKEN]= 0, the module is in its lowest power state. The ADC can perform an analog-to-digital conversion on any of the software selectable channels. All modes perform conversion by a successive approximation algorithm. -
Page 676: Clock Select And Divide Control
Functional description 31.4.2 Clock select and divide control One of four clock sources can be selected as the clock source for the ADC module. This clock source is then divided by a configurable value to generate the input clock ADCK, to the module. -
Page 677: Hardware Trigger And Channel Selects
Chapter 31 Analog-to-Digital Converter (ADC) selected using SC2[REFSEL]. The alternate (V and V ) voltage reference pair ALTH ALTL may select additional external pins or internal sources depending on MCU configuration. See the chip configuration information on the voltage references specific to this MCU. 31.4.4 Hardware trigger and channel selects The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled when SC2[ADTRG] is set and a hardware trigger select event,... -
Page 678: Conversion Control
Functional description The conversion complete flag associated with the ADHWTSn received, that is, SC1n[COCO], is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled, that is, SC1[AIEN]=1. 31.4.5 Conversion control Conversions can be performed as determined by CFG1[MODE] and SC1n[DIFF] as shown in the description of CFG1[MODE]. -
Page 679: Freescale Semiconductor, Inc
Chapter 31 Analog-to-Digital Converter (ADC) If continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion, by:. In software triggered operation, that is, when ADTRG=0, continuous conversions begin after SC1A is written and continue until aborted. -
Page 680: Freescale Semiconductor, Inc
Functional description • The MCU is reset or enters Low-Power Stop modes. • The MCU enters Normal Stop mode with ADACK not enabled. When a conversion is aborted, the contents of the data registers, Rn, are not altered. The data registers continue to be the values transferred after the completion of the last successful conversion. -
Page 681: Freescale Semiconductor, Inc
Chapter 31 Analog-to-Digital Converter (ADC) The total conversion time depends upon: • The sample time as determined by CFG1[ADLSMP] and CFG2[ADLSTS] • The MCU bus frequency • The conversion mode, as determined by CFG1[MODE] and SC1n[DIFF] • The high speed configuration, that is, CFG2[ADHSC] •... -
Page 682: Freescale Semiconductor, Inc
Functional description Table 31-107. Single or first continuous time adder (SFCAdder) (continued) CFG1[AD CFG2[AD CFG1[ADICLK] Single or first continuous time adder (SFCAdder) LSMP] ACKEN] 5 μs + 5 ADCK cycles + 5 bus clock cycles 1. To achieve this time, CFG2[ADACKEN] must be 1 for at least 5 μs prior to the conversion is initiated. Table 31-108. -
Page 683: Freescale Semiconductor, Inc
Chapter 31 Analog-to-Digital Converter (ADC) Note The ADCK frequency must be between f minimum and ADCK maximum to meet ADC specifications. ADCK 31.4.5.6 Conversion time examples The following examples use Figure 31-95 and the information provided in Table 31-107 through Table 31-111. -
Page 684: Freescale Semiconductor, Inc
Functional description • Configured for longest adder • High-speed conversion disabled • Average enabled for 32 conversions The conversion time for this conversion is calculated by using Figure 31-95 and the information provided in Table 31-107 through Table 31-111. The following table lists the variables of the Figure 31-95. -
Page 685: Automatic Compare Function
Chapter 31 Analog-to-Digital Converter (ADC) The resulting conversion time is generated using the parameters listed in in the preceding table. Therefore, for bus clock and ADCK frequency equal to 20 MHz, the resulting conversion time is 1.45 µs. 31.4.5.7 Hardware average function The hardware average function can be enabled by setting SC3[AVGE]=1 to perform a hardware average of multiple conversions. -
Page 686: Freescale Semiconductor, Inc
Functional description Table 31-115. Compare modes ADCCV1 SC2[AC SC2[AC relative to Function Compare mode description FGT] REN] ADCCV2 — Less than threshold Compare true if the result is less than the CV1 registers. — Greater than or equal to threshold Compare true if the result is greater than or equal to CV1 registers. -
Page 687: Calibration Function
Chapter 31 Analog-to-Digital Converter (ADC) 31.4.7 Calibration function The ADC contains a self-calibration function that is required to achieve the specified accuracy. Calibration must be run, or valid calibration values written, after any reset and before a conversion is initiated. The calibration function sets the offset calibration value, the minus-side calibration values, and the plus-side calibration values. -
Page 688: User-Defined Offset Function
Functional description 2. Add the plus-side calibration results CLP0, CLP1, CLP2, CLP3, CLP4, and CLPS to the variable. 3. Divide the variable by two. 4. Set the MSB of the variable. 5. The previous two steps can be achieved by setting the carry bit, rotating to the right through the carry bit on the high byte and again on the low byte. -
Page 689: Temperature Sensor
Chapter 31 Analog-to-Digital Converter (ADC) OFS is automatically set according to calibration requirements once the self-calibration sequence is done, that is, SC3[CAL] is cleared. The user may write to OFS to override the calibration result if desired. If the OFS is written by the user to a value that is different from the calibration value, the ADC error specifications may not be met. -
Page 690: Mcu Wait Mode Operation
Functional description For temperature calculations, use the V and temperature sensor slope values from TEMP25 the ADC Electricals table. In application code, the user reads the temperature sensor channel, calculates V , and TEMP compares to V . If V is greater than V the cold slope value is applied in TEMP25... -
Page 691: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Chapter 31 Analog-to-Digital Converter (ADC) 31.4.11.1 Normal Stop mode with ADACK disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the ADC in its Idle state. The contents of the ADC registers, including Rn, are unaffected by Normal Stop mode. -
Page 692: Initialization Information
Initialization information 31.5 Initialization information This section gives an example that provides some basic direction on how to initialize and configure the ADC module. The user can configure the module for 16-bit, 12-bit, 10-bit, or 8-bit single-ended resolution or 16-bit, 13-bit, 11-bit, or 9-bit differential resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. -
Page 693: Freescale Semiconductor, Inc
Chapter 31 Analog-to-Digital Converter (ADC) 6. Update the PGA register to enable or disable PGA and configure appropriate gain. This register is also used to select Power Mode and to check whether the module is chopper-stabilized. 31.5.1.2 Pseudo-code example In this example, the ADC module is set up with interrupts enabled to perform a single 10- bit conversion at low-power with a long sample time on input channel 1, where ADCK is derived from the bus clock divided by 1. -
Page 694: Application Information
Application information Reset Initialize ADC CFG1 = 0x98 SC2 = 0x00 SC1n = 0x41 Check SC1n[COCO]=1? Read Rn to clear SC1n[COCO] Continue Figure 31-97. Initialization flowchart example 31.6 Application information The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an ADC. -
Page 695: Freescale Semiconductor, Inc
Chapter 31 Analog-to-Digital Converter (ADC) • V is shared on the same pin as the MCU digital V • V and V are shared with the MCU digital supply pins—In these cases, there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. -
Page 696: Sources Of Error
Application information 31.6.1.3 Analog input pins The external analog inputs are typically shared with digital I/O pins on MCU devices. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. Use of 0.01 μF capacitors with good high-frequency characteristics is sufficient. -
Page 697: Freescale Semiconductor, Inc
Chapter 31 Analog-to-Digital Converter (ADC) LSBERR = value of acceptable sampling error in LSBs N = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode or 16 in 16-bit mode Higher source resistances or higher-accuracy sampling is possible by setting CFG1[ADLSMP] and changing CFG2[ADLSTS] to increase the sample window, or decreasing ADCK frequency to increase sample time. -
Page 698: Freescale Semiconductor, Inc
Application information There are some situations where external system activity causes radiated or conducted noise emissions or excessive V noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in Wait or Normal Stop mode, or I/O activity cannot be halted, the following actions may reduce the effect of noise on the accuracy: •... -
Page 699: Freescale Semiconductor, Inc
Chapter 31 Analog-to-Digital Converter (ADC) 31.6.2.5 Linearity errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors, but the system designers must be aware of these errors because they affect overall accuracy: •... -
Page 700: Freescale Semiconductor, Inc
Application information • Non-monotonicity: Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. • Missing codes: Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. -
Page 701: Introduction
Chapter 32 Comparator (CMP) 32.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The comparator (CMP) module provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage, known as rail-to-rail operation. -
Page 702: Bit Dac Key Features
6-bit DAC key features • Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output • Selectable inversion on comparator output • Capability to produce a wide range of outputs such as: • Sampled • Windowed, which is ideal for certain PWM zero-crossing-detection applications •... -
Page 703: Anmux Key Features
Chapter 32 Comparator (CMP) 32.4 ANMUX key features • Two 8-to-1 channel mux • Operational over the entire supply range 32.5 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. K30 Sub-Family Reference Manual, Rev. -
Page 704: Cmp Block Diagram
CMP block diagram VRSEL VOSEL[5:0] DACEN DAC output PSEL[2:0] Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Sample input Reference Input 5 Reference Input 6 Window ANMUX and filter control CMPO MSEL[2:0] Figure 32-1. CMP, DAC and ANMUX block diagram 32.6 CMP block diagram The following figure shows the block diagram for the CMP module. -
Page 705: Freescale Semiconductor, Inc
Chapter 32 Comparator (CMP) Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN,PMODE,HYSCTRL[1:0] Window Interrupt Polarity Filter control select control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided prescaler FILT_PER CGMUX clock Figure 32-2. Comparator module block diagram In the CMP block diagram: •... -
Page 706: Memory Map/Register Definitions
Memory map/register definitions • If enabled, the Filter block will incur up to one bus clock additional latency penalty on COUT due to the fact that COUT, which is crossing clock domain boundaries, must be resynchronized to the bus clock. •... -
Page 707: Cmp Control Register 1 (Cmpx_Cr1)
Chapter 32 Comparator (CMP) CMPx_CR0 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–4 Filter Sample Count FILTER_CNT Represents the number of consecutive samples that must agree prior to the comparator ouput filter accepting a new output state. -
Page 708: Freescale Semiconductor, Inc
Memory map/register definitions CMPx_CR1 field descriptions (continued) Field Description Sampling mode is not selected. Sampling mode is selected. Windowing Enable At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is set and WE is cleared. -
Page 709: Cmp Filter Period Register (Cmpx_Fpr)
Chapter 32 Comparator (CMP) 32.7.3 CMP Filter Period Register (CMPx_FPR) Address: Base address + 2h offset Read FILT_PER Write Reset CMPx_FPR field descriptions Field Description 7–0 Filter Sample Period FILT_PER Specifies the sampling period, in bus clock cycles, of the comparator output filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. -
Page 710: Dac Control Register (Cmpx_Daccr)
Memory map/register definitions CMPx_SCR field descriptions (continued) Field Description Interrupt is disabled. Interrupt is enabled. Comparator Interrupt Enable Falling Enables the CFF interrupt from the CMP. When this field is set, an interrupt will be asserted when CFF is set. Interrupt is disabled. -
Page 711: Mux Control Register (Cmpx_Muxcr)
Chapter 32 Comparator (CMP) CMPx_DACCR field descriptions (continued) Field Description V is selected as resistor ladder network supply reference V. in1in V is selected as resistor ladder network supply reference V. in2in 5–0 DAC Output Voltage Select VOSEL Selects an output voltage from one of 64 distinct levels. /64) * (VOSEL[5:0] + 1) , so the DACO range is from V /64 to V DACO = (V... -
Page 712: Cmp Functional Description
CMP functional description CMPx_MUXCR field descriptions (continued) Field Description NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator. 32.8 CMP functional description The CMP module can be used to compare two analog input voltages applied to INP and INM. -
Page 713: Freescale Semiconductor, Inc
Chapter 32 Comparator (CMP) The "windowing mode" is enabled by setting CR1[WE]. When set, the comparator output is sampled only when WINDOW=1. This feature can be used to ignore the comparator output during time periods in which the input voltages are not valid. This is especially useful when implementing zero-crossing-detection for certain PWM applications. -
Page 714: Freescale Semiconductor, Inc
CMP functional description For cases where a comparator is used to drive a fault input, for example, for a motor- control module such as FTM, it must be configured to operate in Continuous mode so that an external fault can immediately pass through the comparator to the target fault circuitry. -
Page 715: Freescale Semiconductor, Inc
Chapter 32 Comparator (CMP) NOTE See the chip configuration section for the source of sample/ window input. The analog comparator block is powered and active. CMPO may be optionally inverted, but is not subject to external sampling or filtering. Both window control and filter blocks are completely bypassed. -
Page 716: Freescale Semiconductor, Inc
CMP functional description The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Non-Filtered (# 3B) is in how the clock to the filter block is derived. In #3A, the clock to filter block is externally derived while in #3B, the clock to filter block is internally derived. -
Page 717: Freescale Semiconductor, Inc
Chapter 32 Comparator (CMP) Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE, HYSTCTR[1:0] > 0x01 Polarity Interrupt Window Filter select control control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1... -
Page 718: Freescale Semiconductor, Inc
CMP functional description Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE,HYSTCTR[1:0 > 0x01 Polarity Filter Window Interrupt block select control control CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=0 Figure 32-31. -
Page 719: Freescale Semiconductor, Inc
Chapter 32 Comparator (CMP) WI NDOW Plus input Minus input CMPO COUTA Figure 32-32. Windowed mode operation Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE,HYSCTR[1:0] 0x01 Interrupt Polarity Window Filter select control control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock... -
Page 720: Freescale Semiconductor, Inc
CMP functional description When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. 32.8.1.6 Windowed/Resampled mode (# 6) The following figure uses the same input stimulus shown in Figure 32-32, and adds resampling of COUTA to generate COUT. -
Page 721: Power Modes
Chapter 32 Comparator (CMP) 32.8.1.7 Windowed/Filtered mode (#7) This is the most complex mode of operation for the comparator block, as it uses both windowing and filtering features. It also has the highest latency of any of the modes. This can be approximated: up to 1 bus clock synchronization in the window function + ((CR0[FILTER_CNT] * FPR[FILT_PER]) + 1) * bus clock for the filter function. -
Page 722: Startup And Operation
CMP functional description 32.8.2.2 Stop mode operation Subject to platform-specific clock restrictions, the MCU is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin. -
Page 723: Low-Pass Filter
Chapter 32 Comparator (CMP) During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] to reflect an input change or a configuration change to one of the components involved in the data path. -
Page 724: Freescale Semiconductor, Inc
CMP functional description Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process. Note Always switch to this setting prior to making any changes in filter parameters. This resets the filter to a known state. Switching CR0[FILTER_CNT] on the fly without this intermediate step can result in unexpected behavior. -
Page 725: Cmp Interrupts
Chapter 32 Comparator (CMP) Table 32-30. Comparator sample/filter maximum latencies (continued) CR1[ CR1[ CR1[ CR0[FILTER FPR[FILT_P Mode # Operation Maximum latency _CNT] > 0x01 Sampled, Filtered mode + (CR0[FILTER_CNT] * ) + T SAMPLE > 0x01 > 0x00 + (CR0[FILTER_CNT] * FPR[FILT_PER] x T ) + T 0x00... -
Page 726: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Digital-to-analog converter block diagram 32.11 Digital-to-analog converter block diagram The following figure shows the block diagram of the DAC module. It contains a 64-tap resistor ladder network and a 64-to-1 multiplexer, which selects an output voltage from one of 64 distinct levels that outputs from DACO. It is controlled through the DAC Control Register (DACCR). -
Page 727: Dac Resets
Chapter 32 Comparator (CMP) 32.13 DAC resets This module has a single reset input, corresponding to the chip-wide peripheral reset. 32.14 DAC clocks This module has a single clock input, the bus clock. 32.15 DAC interrupts This module has no interrupts. K30 Sub-Family Reference Manual, Rev. -
Page 728: Freescale Semiconductor, Inc
DAC interrupts K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 729: Introduction
Chapter 33 12-bit Digital-to-Analog Converter (DAC) 33.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The 12-bit digital-to-analog converter (DAC) is a low-power general-purpose DAC. The output of this DAC can be placed on an external pin or set as one of the inputs to the analog comparator, operational amplifiers (OPAMPs), analog-to-digital converter (ADC), or other peripherals. -
Page 730: Memory Map/Register Definition
Memory map/register definition DACREF_2 DACREF_1 DACRFS DACRFS AMP buffer DACEN LPEN DACDAT[11:0] Hardware trigger DACBFWMF & DACBWIEN DACSWTRG Data Buffer DACBFWM DACBFRPTF dac_interrupt & DACBFEN DACBTIEN DACBFUP DACBFRPBF DACBFRP & DACBBIEN DACBFMD DACTRGSE Figure 33-1. DAC block diagram 33.4 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions. -
Page 731: Dac Data Low Register (Dacx_Datnl)
Chapter 33 12-bit Digital-to-Analog Converter (DAC) NOTE The below memory map describes 2 DACs (DAC0 and DAC1) map. The address of a register is the sum of a base address and an address offset. The base address is defined at the chip level. The address offset is defined at the module level. DAC memory map Absolute Width... -
Page 732: Dac Status Register (Dacx_Sr)
Memory map/register definition DACx_DATnL field descriptions Field Description 7–0 When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following DATA[7:0] formula: V * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA is mapped to the 16-word buffer. 33.4.2 DAC Data High Register (DACx_DATH) Address: 400C_C000h base + 1h offset = 400C_C001h Read... -
Page 733: Dac Control Register (Dacx_C0)
Chapter 33 12-bit Digital-to-Analog Converter (DAC) DACx_SR field descriptions (continued) Field Description The DAC buffer read pointer has not reached the watermark level. The DAC buffer read pointer has reached the watermark level. DAC Buffer Read Pointer Top Position Flag DACBFRPTF The DAC buffer read pointer is not zero. -
Page 734: Dac Control Register 1 (Dacx_C1)
Memory map/register definition DACx_C0 field descriptions (continued) Field Description NOTE: See the 12-bit DAC electrical characteristics of the device data sheet for details on the impact of the modes below. High-Power mode Low-Power mode DAC Buffer Watermark Interrupt Enable DACBWIEN The DAC buffer watermark interrupt is disabled. -
Page 735: Dac Control Register 2 (Dacx_C2)
Chapter 33 12-bit Digital-to-Analog Converter (DAC) DACx_C1 field descriptions (continued) Field Description 2–1 DAC Buffer Work Mode Select DACBFMD Normal mode Swing mode Reserved One-Time Scan mode Reserved DAC Buffer Enable DACBFEN Buffer read pointer is disabled. The converted data is always the first word of the buffer. Buffer read pointer is enabled. -
Page 736: Dac Data Buffer Operation
Functional description 33.5.1 DAC data buffer operation When the DAC is enabled and the buffer is not enabled, the DAC module always converts the data in DAT0 to analog output voltage. When both the DAC and the buffer are enabled, the DAC converts the data in the data buffer to analog output voltage. -
Page 737: Dma Operation
Chapter 33 12-bit Digital-to-Analog Converter (DAC) Table 33-47. Modes of DAC data buffer operation (continued) Modes Description The read pointer increases by 1 every time the trigger occurs. When it reaches the upper limit, it stops there. If read pointer is reset to the address other than the upper limit, it will Buffer One-time Scan mode increase to the upper address and stop there again. -
Page 738: Freescale Semiconductor, Inc
Functional description K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 739: Introduction
Chapter 34 Voltage Reference (VREFV1) 34.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Voltage Reference(VREF) is intended to supply an accurate voltage output that can be trimmed in 0.5 mV steps. The VREF can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC, DAC, or CMP. -
Page 740: Overview
Introduction Figure 34-1. Voltage reference block diagram 34.1.1 Overview The Voltage Reference provides a buffered reference voltage for use as an external reference. In addition, the buffered reference is available internally for use with on chip peripherals such as ADCs and DACs. Refer to the chip configuration chapter for a description of these options. -
Page 741: Modes Of Operation
Chapter 34 Voltage Reference (VREFV1) • Bandgap enabled/standby (output buffer disabled) • Low power buffer mode (output buffer enabled) • High power buffer mode (output buffer enabled) • 1.2 V output at room temperature • Dedicated output pin, VREF_OUT 34.1.3 Modes of Operation The Voltage Reference continues normal operation in Run, Wait, and Stop modes. -
Page 742: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Memory Map and Register Definition 34.2 Memory Map and Register Definition VREF memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_4000 VREF Trim Register (VREF_TRM) See section 34.2.1/742 4007_4001 VREF Status and Control Register (VREF_SC) 34.2.2/743 34.2.1 VREF Trim Register (VREF_TRM) This register contains bits that contain the trim data for the Voltage Reference. -
Page 743: Vref Status And Control Register (Vref_Sc)
Chapter 34 Voltage Reference (VREFV1) 34.2.2 VREF Status and Control Register (VREF_SC) This register contains the control bits used to enable the internal voltage reference and to select the buffer mode to be used. Address: 4007_4000h base + 1h offset = 4007_4001h Read VREFST VREFEN... -
Page 744: Functional Description
Functional Description VREF_SC field descriptions (continued) Field Description This bit indicates that the bandgap reference within the Voltage Reference module has completed its startup and stabilization. The module is disabled or not stable. The module is stable. 1–0 Buffer Mode selection MODE_LV These bits select the buffer modes for the Voltage Reference module. -
Page 745: Voltage Reference Enabled, Sc[Vrefen] = 1
Chapter 34 Voltage Reference (VREFV1) 34.3.2 Voltage Reference Enabled, SC[VREFEN] = 1 When SC[VREFEN] = 1, the Voltage Reference is enabled, and different modes should be set by the SC[MODE_LV] bits. 34.3.2.1 SC[MODE_LV]=00 The internal VREF bandgap is enabled to generate an accurate 1.2 V output that can be trimmed with the TRM register's TRIM[5:0] bitfield. -
Page 746: Initialization/Application Information
Initialization/Application Information If this mode is entered from the standby mode (SC[MODE_LV] = 00, SC[VREFEN] = 1) there will be a delay before the buffer output is settled at the final value. This is the buffer start up delay (Tstup) and the value is specified in the appropriate device data sheet. If this mode is entered when the VREF module is enabled then you must wait the longer of Tstup or until SC[VREFST] = 1. -
Page 747: Introduction
Chapter 35 Programmable Delay Block (PDB) 35.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Programmable Delay Block (PDB) provides controllable delays from either an internal or an external trigger, or a programmable interval tick, to the hardware trigger inputs of ADCs and/or generates the interval triggers to DACs, so that the precise timing between ADC conversions and/or DAC updates can be achieved. -
Page 748: Implementation
Introduction • Optional back-to-back mode operation, which enables the ADC conversions complete to trigger the next PDB channel • One programmable delay interrupt • One sequence error interrupt • One channel flag and one sequence error flag per pre-trigger • DMA support •... -
Page 749: Back-To-Back Acknowledgment Connections
Chapter 35 Programmable Delay Block (PDB) • Y — Total number of Pulse-Out's. • y — Pulse-Out number, valid value is from 0 to Y-1. NOTE The number of module output triggers to core is chip-specific. For module to core output triggers implementation, see the chip configuration information. -
Page 750: Freescale Semiconductor, Inc
Introduction Ack 0 PDBCHnDLY0 Pre-trigger 0 BB[0], TOS[0] EN[0] Ch n pre-trigger 0 Ack m PDBCHnDLYm Pre-trigger m BB[m], TOS[m] EN[m] Ch n pre-trigger m Sequence Error Detection ERR[M - 1:0] Ch n trigger PDBMOD Control DACINTx Logic DAC interval trigger x PDBCNT DAC Interval Counter x... -
Page 751: Modes Of Operation
Chapter 35 Programmable Delay Block (PDB) 35.1.6 Modes of operation PDB ADC trigger operates in the following modes. Disabled: Counter is off, all pre-trigger and trigger outputs are low if PDB is not in back- to-back operation of Bypass mode. Debug: Counter is paused when processor is in Debug mode, and the counter for dac trigger is also paused in Debug mode. -
Page 752: Freescale Semiconductor, Inc
Memory map and register definition PDB memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_6000 Status and Control Register (PDB0_SC) 0000_0000h 35.3.1/753 4003_6004 Modulus Register (PDB0_MOD) 0000_FFFFh 35.3.2/755 4003_6008 Counter Register (PDB0_CNT) 0000_0000h 35.3.3/756 4003_600C Interrupt Delay Register (PDB0_IDLY) 0000_FFFFh... -
Page 753: Status And Control Register (Pdbx_Sc)
Chapter 35 Programmable Delay Block (PDB) 35.3.1 Status and Control Register (PDBx_SC) Address: 4003_6000h base + 0h offset = 4003_6000h LDMOD Reset PRESCALER TRGSEL MULT Reset PDBx_SC field descriptions Field Description 31–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 19–18 Load Mode Select LDMOD... -
Page 754: Freescale Semiconductor, Inc
Memory map and register definition PDBx_SC field descriptions (continued) Field Description PDB sequence error interrupt disabled. PDB sequence error interrupt enabled. Software Trigger SWTRIG When PDB is enabled and the software trigger is selected as the trigger input source, writing 1 to this bit reset and restarts the counter. -
Page 755: Modulus Register (Pdbx_Mod)
Chapter 35 Programmable Delay Block (PDB) PDBx_SC field descriptions (continued) Field Description PDB Enable PDBEN PDB disabled. Counter is off. PDB enabled. PDB Interrupt Flag PDBIF This bit is set when the counter value is equal to the IDLY register. Writing zero clears this bit. PDB Interrupt Enable. -
Page 756: Counter Register (Pdbx_Cnt)
Memory map and register definition PDBx_MOD field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 PDB Modulus Specifies the period of the counter. When the counter reaches this value, it will be reset back to zero. If the PDB is in Continuous mode, the count begins anew. -
Page 757: Channel N Control Register 1 (Pdbx_Chnc1)
Chapter 35 Programmable Delay Block (PDB) PDBx_IDLY field descriptions (continued) Field Description equal to the IDLY. Reading these bits returns the value of internal register that is effective for the current cycle of the PDB. 35.3.5 Channel n Control Register 1 (PDBx_CHnC1) Each PDB channel has one Control Register, CHnC1. -
Page 758: Channel N Status Register (Pdbx_Chns)
Memory map and register definition 35.3.6 Channel n Status Register (PDBx_CHnS) Address: 4003_6000h base + 14h offset + (40d × i), where i=0d to 1d Reset PDBx_CHnS field descriptions Field Description 31–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 23–16 PDB Channel Flags The CF[m] bit is set when the PDB counter matches the CHnDLYm. -
Page 759: Channel N Delay 1 Register (Pdbx_Chndly1)
Chapter 35 Programmable Delay Block (PDB) 35.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1) Address: 4003_6000h base + 1Ch offset + (40d × i), where i=0d to 1d Reset PDBx_CHnDLY1 field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 PDB Channel Delay These bits specify the delay value for the channel's corresponding pre-trigger. -
Page 760: Dac Interval N Register (Pdbx_Dacintn)
Memory map and register definition PDBx_DACINTCn field descriptions (continued) Field Description DAC Interval Trigger Enable This bit enables the DAC interval trigger. DAC interval trigger disabled. DAC interval trigger enabled. 35.3.10 DAC Interval n Register (PDBx_DACINTn) Address: 4003_6000h base + 154h offset + (8d × i), where i=0d to 0d Reset PDBx_DACINTn field descriptions Field... -
Page 761: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Chapter 35 Programmable Delay Block (PDB) PDBx_POEN field descriptions (continued) Field Description PDB Pulse-Out disabled PDB Pulse-Out enabled 35.3.12 Pulse-Out n Delay Register (PDBx_POnDLY) Address: 4003_6000h base + 194h offset + (4d × i), where i=0d to 2d DLY1 DLY2 Reset PDBx_POnDLY field descriptions Field... -
Page 762: Freescale Semiconductor, Inc
Functional description • Trigger input event to pre-trigger m = (prescaler X multiplication factor X delay m) + 2 peripheral clock cycles • Add one additional peripheral clock cycle to determine the time at which the channel trigger output change. Each channel is associated with one ADC block. -
Page 763: Pdb Trigger Input Source Selection
Chapter 35 Programmable Delay Block (PDB) When an ADC conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress and ADCnSC1[COCO] is not set, a new trigger from PDB channel n pre-trigger m cannot be accepted by ADCn. Therefore every time when one PDB channel n pre-trigger and trigger output starts an ADC conversion, an internal lock associated with the corresponding pre-trigger is activated. -
Page 764: Pulse-Out's
Functional description DAC interval counters are also reset when the PDB counter reaches the MOD register value; therefore, when the PDB counter rolls over to zero, the DAC interval counters starts anew. Together, the DAC interval trigger pulse and the ADC pre-trigger/trigger pulses allow precise timing of DAC updates and ADC measurements. -
Page 765: Updating The Delay Registers
Chapter 35 Programmable Delay Block (PDB) The pulse-out connections implemented in this MCU are described in the device's chip configuration details. 35.4.5 Updating the delay registers The following registers control the timing of the PDB operation; and in some of the applications, they may need to become effective at the same time. -
Page 766: Interrupts
Functional description CHnDLY1 CHnDLY0 PDB Counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 35-54. Registers Update with SC[LDMOD] = 00 CHnDLY1 CHnDLY0 PDB Counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 35-55. Registers update with SC[LDMOD] = x1 35.4.6 Interrupts PDB can generate two interrupts: PDB interrupt and PDB sequence error interrupt. -
Page 767: Application Information
Chapter 35 Programmable Delay Block (PDB) 35.5 Application information 35.5.1 Impact of using the prescaler and multiplication factor on timing resolution Use of prescaler and multiplication factor greater than 1 limits the count/delay accuracy in terms of peripheral clock cycles (to the modulus of the prescaler X multiplication factor). -
Page 768: Freescale Semiconductor, Inc
Application information K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 769: Introduction
Chapter 36 FlexTimer Module (FTM) 36.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The FlexTimer module (FTM) is a two-to-eight channel timer that supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. -
Page 770: Features
Introduction Motor control and power conversion features have been added through a dedicated set of registers and defaults turn off all new features. The new features, such as hardware deadtime insertion, polarity, fault control, and output forcing and masking, greatly reduce loading on the execution software and are usually each controlled by a group of registers. -
Page 771: Modes Of Operation
Chapter 36 FlexTimer Module (FTM) • The capture can occur on rising edges, falling edges or both edges • An input filter can be selected for some channels • In Output Compare mode the output signal can be set, cleared, or toggled on match •... -
Page 772: Block Diagram
Introduction real time reference or provide the interrupt sources needed to wake the MCU from Wait mode, the power can then be saved by disabling FTM functions before entering Wait mode. 36.1.4 Block diagram The FTM uses one input/output (I/O) pin per channel, CHn (FTM channel (n)) where n is the channel number (0–7). -
Page 773: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) CLKS FTMEN QUADEN no clock selected (FTM counter disable) system clock fixed frequency clock prescaler external clock synchronizer (1, 2, 4, 8, 16, 32, 64 or 128) phase A Quadrature decoder phase B QUADEN CPWMS CAPTEST INITTRIGEN initialization... -
Page 774: Ftm Signal Descriptions
FTM signal descriptions 36.2 FTM signal descriptions Table 36-1 shows the user-accessible signals for the FTM. Table 36-1. FTM signal descriptions Signal Description Function EXTCLK External clock. FTM external The external clock input signal is used as the FTM counter clock can be selected to drive clock if selected by CLKS[1:0] bits in the SC register. -
Page 775: Register Descriptions
Chapter 36 FlexTimer Module (FTM) The second set has the FTM specific registers. Any second set registers, or bits within these registers, that are used by an unavailable function in the FTM configuration remain in the memory map and in the reset value, so they have no active function. Note Do not write to the FTM specific registers (second set registers) when FTMEN = 0. -
Page 776: Freescale Semiconductor, Inc
Memory map and register definition FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 36.3.11/ 4003_8058 Synchronization (FTM0_SYNC) 0000_0000h 36.3.12/ 4003_805C Initial State For Channels Output (FTM0_OUTINIT) 0000_0000h 36.3.13/ 4003_8060 Output Mask (FTM0_OUTMASK) 0000_0000h 36.3.14/ 4003_8064... -
Page 777: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_9024 Channel (n) Status And Control (FTM1_C3SC) 0000_0000h 36.3.6/783 4003_9028 Channel (n) Value (FTM1_C3V) 0000_0000h 36.3.7/785 4003_902C Channel (n) Status And Control (FTM1_C4SC) 0000_0000h 36.3.6/783 4003_9030... -
Page 778: Freescale Semiconductor, Inc
Memory map and register definition FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 36.3.25/ 4003_9090 FTM Inverting Control (FTM1_INVCTRL) 0000_0000h 36.3.26/ 4003_9094 FTM Software Output Control (FTM1_SWOCTRL) 0000_0000h 36.3.27/ 4003_9098 FTM PWM Load (FTM1_PWMLOAD) 0000_0000h 400B_8000 Status And Control (FTM2_SC) -
Page 779: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 36.3.17/ 400B_8070 Channels Polarity (FTM2_POL) 0000_0000h 36.3.18/ 400B_8074 Fault Mode Status (FTM2_FMS) 0000_0000h 36.3.19/ 400B_8078 Input Capture Filter Control (FTM2_FILTER) 0000_0000h 36.3.20/ 400B_807C Fault Control (FTM2_FLTCTRL) -
Page 780: Status And Control (Ftmx_Sc)
Memory map and register definition 36.3.3 Status And Control (FTMx_SC) SC contains the overflow status flag and control bits used to configure the interrupt enable, FTM configuration, clock source, and prescaler factor. These controls relate to all channels within this module. Address: Base address + 0h offset Reset TOIE... -
Page 781: Counter (Ftmx_Cnt)
Chapter 36 FlexTimer Module (FTM) FTMx_SC field descriptions (continued) Field Description Timer Overflow Interrupt Enable TOIE Enables FTM overflow interrupts. Disable TOF interrupts. Use software polling. Enable TOF interrupts. An interrupt is generated when TOF equals one. Center-Aligned PWM Select CPWMS Selects CPWM mode. -
Page 782: Modulo (Ftmx_Mod)
Memory map and register definition Address: Base address + 4h offset COUNT Reset FTMx_CNT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Counter Value COUNT 36.3.5 Modulo (FTMx_MOD) The Modulo register contains the modulo value for the FTM counter. -
Page 783: Channel (N) Status And Control (Ftmx_Cnsc)
Chapter 36 FlexTimer Module (FTM) 36.3.6 Channel (n) Status And Control (FTMx_CnSC) CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. Table 36-67. Mode, edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA... -
Page 784: Freescale Semiconductor, Inc
Memory map and register definition Table 36-67. Mode, edge, and level selection (continued) DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration See the Dual Edge One-Shot following table Capture Capture mode (Table 36-8). Continuous Capture mode Table 36-68. Dual Edge Capture mode — edge polarity selection ELSnB ELSnA Channel Port Enable... -
Page 785: Channel (N) Value (Ftmx_Cnv)
Chapter 36 FlexTimer Module (FTM) FTMx_CnSC field descriptions (continued) Field Description Disable channel interrupts. Use software polling. Enable channel interrupts. Channel Mode Select Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See Table 36-7. -
Page 786: Counter Initial Value (Ftmx_Cntin)
Memory map and register definition Address: Base address + 10h offset + (8d × i), where i=0d to 7d Reset FTMx_CnV field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Channel Value Captured FTM counter value of the input modes or the match value for the output modes... -
Page 787: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Chapter 36 FlexTimer Module (FTM) Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be checked using only one read of STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to STATUS. Hardware sets the individual channel flags when an event occurs on the channel. -
Page 788: Features Mode Selection (Ftmx_Mode)
Memory map and register definition FTMx_STATUS field descriptions (continued) Field Description No channel event has occurred. A channel event has occurred. Channel 6 Flag CH6F See the register description. No channel event has occurred. A channel event has occurred. Channel 5 Flag CH5F See the register description. -
Page 789: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) • Fault control mode and interrupt • Capture Test mode • PWM synchronization • Write protection • Channel output initialization These controls relate to all channels within this module. Address: Base address + 54h offset Reset FAULTM INIT... -
Page 790: Synchronization (Ftmx_Sync)
Memory map and register definition FTMx_MODE field descriptions (continued) Field Description Capture test mode is disabled. Capture test mode is enabled. PWM Synchronization Mode PWMSYNC Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. See synchronization. -
Page 791: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) NOTE The software trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a potential conflict if used together when SYNCMODE = 0. Use only hardware or software triggers but not both at the same time, otherwise unpredictable behavior is likely to happen. -
Page 792: Freescale Semiconductor, Inc
Memory map and register definition FTMx_SYNC field descriptions (continued) Field Description Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2 happens when a rising edge is detected at the trigger 2 input signal. Trigger is disabled. Trigger is enabled. PWM Synchronization Hardware Trigger 1 TRIG1 Enables hardware trigger 1 to the PWM synchronization. -
Page 793: Initial State For Channels Output (Ftmx_Outinit)
Chapter 36 FlexTimer Module (FTM) 36.3.12 Initial State For Channels Output (FTMx_OUTINIT) Address: Base address + 5Ch offset Reset Reset FTMx_OUTINIT field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel 7 Output Initialization Value CH7OI Selects the value that is forced into the channel output when the initialization occurs. -
Page 794: Output Mask (Ftmx_Outmask)
Memory map and register definition FTMx_OUTINIT field descriptions (continued) Field Description The initialization value is 0. The initialization value is 1. Channel 2 Output Initialization Value CH2OI Selects the value that is forced into the channel output when the initialization occurs. The initialization value is 0. -
Page 795: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTMx_OUTMASK field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel 7 Output Mask CH7OM Defines if the channel output is masked or unmasked. Channel output is not masked. -
Page 796: Function For Linked Channels (Ftmx_Combine)
Memory map and register definition 36.3.14 Function For Linked Channels (FTMx_COMBINE) This register contains the control bits used to configure the fault control, synchronization, deadtime insertion, Dual Edge Capture mode, Complementary, and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2, 4, and 6. Address: Base address + 64h offset Reset Reset... -
Page 797: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field Description Dual Edge Capture Mode Captures For n = 6 DECAP3 Enables the capture of the FTM counter value according to the channel (n) input event and the configuration of the dual edge capture bits. This field applies only when FTMEN = 1 and DECAPEN = 1. -
Page 798: Freescale Semiconductor, Inc
Memory map and register definition FTMx_COMBINE field descriptions (continued) Field Description Deadtime Enable For n = 4 DTEN2 Enables the deadtime insertion in the channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. The deadtime insertion in this pair of channels is disabled. -
Page 799: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field Description The fault control in this pair of channels is disabled. The fault control in this pair of channels is enabled. Synchronization Enable For n = 2 SYNCEN1 Enables PWM synchronization of registers C(n)V and C(n+1)V. The PWM synchronization in this pair of channels is disabled. -
Page 800: Freescale Semiconductor, Inc
Memory map and register definition FTMx_COMBINE field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Fault Control Enable For n = 0 FAULTEN0 Enables the fault control in channels (n) and (n+1). This field is write protected. -
Page 801: Deadtime Insertion Control (Ftmx_Deadtime)
Chapter 36 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field Description Combine Channels For n = 0 COMBINE0 Enables the combine feature for channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. Channels (n) and (n+1) are independent. -
Page 802: Ftm External Trigger (Ftmx_Exttrig)
Memory map and register definition 36.3.16 FTM External Trigger (FTMx_EXTTRIG) This register: • Indicates when a channel trigger was generated • Enables the generation of a trigger when the FTM counter is equal to its initial • Selects which channels are used in the generation of the channel triggers Several channels can be selected to generate multiple triggers in one PWM period. -
Page 803: Channels Polarity (Ftmx_Pol)
Chapter 36 FlexTimer Module (FTM) FTMx_EXTTRIG field descriptions (continued) Field Description Channel 1 Trigger Enable CH1TRIG Enable the generation of the channel trigger when the FTM counter is equal to the CnV register. The generation of the channel trigger is disabled. The generation of the channel trigger is enabled. -
Page 804: Freescale Semiconductor, Inc
Memory map and register definition Address: Base address + 70h offset Reserved Reset Reserved POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 Reset FTMx_POL field descriptions Field Description 31–8 This field is reserved. Reserved Channel 7 Polarity POL7 Defines the polarity of the channel output. This field is write protected. -
Page 805: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTMx_POL field descriptions (continued) Field Description This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel polarity is active high. The channel polarity is active low. Channel 1 Polarity POL1 Defines the polarity of the channel output. -
Page 806: Fault Mode Status (Ftmx_Fms)
Memory map and register definition 36.3.18 Fault Mode Status (FTMx_FMS) This register contains the fault detection flags, write protection enable bit, and the logic OR of the enabled fault inputs. Address: Base address + 74h offset Reset Reset FTMx_FMS field descriptions Field Description 31–8... -
Page 807: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTMx_FMS field descriptions (continued) Field Description Write Protection Enable WPEN The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPEN has no effect. Write protection is disabled. -
Page 808: Input Capture Filter Control (Ftmx_Filter)
Memory map and register definition FTMx_FMS field descriptions (continued) Field Description If another fault condition is detected at the corresponding fault input before the clearing sequence is completed, the sequence is reset so FAULTF1 remains set after the clearing sequence is completed for the earlier fault condition. -
Page 809: Fault Control (Ftmx_Fltctrl)
Chapter 36 FlexTimer Module (FTM) FTMx_FILTER field descriptions (continued) Field Description 11–8 Channel 2 Input Filter CH2FVAL Selects the filter value for the channel input. The filter is disabled when the value is zero. 7–4 Channel 1 Input Filter CH1FVAL Selects the filter value for the channel input. -
Page 810: Freescale Semiconductor, Inc
Memory map and register definition FTMx_FLTCTRL field descriptions (continued) Field Description NOTE: Writing to this field has immediate effect and must be done only when the fault control or all fault inputs are disabled. Failure to do this could result in a missing fault detection. Fault Input 3 Filter Enable FFLTR3EN Enables the filter for the fault input. -
Page 811: Quadrature Decoder Control And Status (Ftmx_Qdctrl)
Chapter 36 FlexTimer Module (FTM) FTMx_FLTCTRL field descriptions (continued) Field Description Fault input is disabled. Fault input is enabled. Fault Input 0 Enable FAULT0EN Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input is disabled. -
Page 812: Freescale Semiconductor, Inc
Memory map and register definition FTMx_QDCTRL field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Phase A Input Filter Enable PHAFLTREN Enables the filter for the quadrature decoder phase A input. The filter value for the phase A input is defined by the CH0FVAL field of FILTER. -
Page 813: Configuration (Ftmx_Conf)
Chapter 36 FlexTimer Module (FTM) FTMx_QDCTRL field descriptions (continued) Field Description Quadrature Decoder Mode Enable QUADEN Enables the Quadrature Decoder mode. In this mode, the phase A and B input signals control the FTM counter direction. The Quadrature Decoder mode has precedence over the other modes. See Table 36-7. -
Page 814: Ftm Fault Input Polarity (Ftmx_Fltpol)
Memory map and register definition FTMx_CONF field descriptions (continued) Field Description Use of an external global time base is disabled. Use of an external global time base is enabled. This field is reserved. Reserved This read-only field is reserved and always has the value 0. 7–6 BDM Mode BDMMODE... -
Page 815: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTMx_FLTPOL field descriptions (continued) Field Description Fault Input 3 Polarity FLT3POL Defines the polarity of the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. The fault input polarity is active high. A one at the fault input indicates a fault. The fault input polarity is active low. -
Page 816: Synchronization Configuration (Ftmx_Synconf)
Memory map and register definition 36.3.24 Synchronization Configuration (FTMx_SYNCONF) This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j = 0, 1, 2, when the hardware trigger j is detected. Address: Base address + 8Ch offset Reset INVC... -
Page 817: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTMx_SYNCONF field descriptions (continued) Field Description 15–13 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Software output control synchronization is activated by the software trigger. SWSOC The software trigger does not activate the SWOCTRL register synchronization. The software trigger activates the SWOCTRL register synchronization. -
Page 818: Ftm Inverting Control (Ftmx_Invctrl)
Memory map and register definition FTMx_SYNCONF field descriptions (continued) Field Description FTM clears the TRIGj bit when the hardware trigger j is detected. FTM does not clear the TRIGj bit when the hardware trigger j is detected. 36.3.25 FTM Inverting Control (FTMx_INVCTRL) This register controls when the channel (n) output becomes the channel (n+1) output, and channel (n+1) output becomes the channel (n) output. -
Page 819: Ftm Software Output Control (Ftmx_Swoctrl)
Chapter 36 FlexTimer Module (FTM) FTMx_INVCTRL field descriptions (continued) Field Description Pair Channels 0 Inverting Enable INV0EN Inverting is disabled. Inverting is enabled. 36.3.26 FTM Software Output Control (FTMx_SWOCTRL) This register enables software control of channel (n) output and defines the value forced to the channel (n) output: •... -
Page 820: Freescale Semiconductor, Inc
Memory map and register definition FTMx_SWOCTRL field descriptions (continued) Field Description The software output control forces 0 to the channel output. The software output control forces 1 to the channel output. Channel 5 Software Output Control Value CH5OCV The software output control forces 0 to the channel output. The software output control forces 1 to the channel output. -
Page 821: Ftm Pwm Load (Ftmx_Pwmload)
Chapter 36 FlexTimer Module (FTM) FTMx_SWOCTRL field descriptions (continued) Field Description The channel output is not affected by software output control. The channel output is affected by software output control. Channel 1 Software Output Control Enable CH1OC The channel output is not affected by software output control. The channel output is affected by software output control. -
Page 822: Functional Description
Functional description FTMx_PWMLOAD field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel 7 Select CH7SEL Do not include the channel in the matching process. Include the channel in the matching process. Channel 6 Select CH6SEL Do not include the channel in the matching process. -
Page 823: Clock Source
Chapter 36 FlexTimer Module (FTM) FTM counting is up. Channel (n) is in high-true EPWM mode. PS[2:0] = 001 CNTIN = 0x0000 MOD = 0x0004 CnV = 0x0002 prescaler counter FTM counter channel (n) output counter channel (n) channel (n) counter counter channel (n) -
Page 824: Prescaler
Functional description The external clock passes through a synchronizer clocked by the system clock to assure that counter transitions are properly aligned to system clock transitions.Therefore, to meet Nyquist criteria considering also jitter, the frequency of the external clock source must not exceed 1/4 of the system clock frequency. -
Page 825: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) The FTM period when using up counting is (MOD – CNTIN + 0x0001) × period of the FTM counter clock. The TOF bit is set when the FTM counter changes from MOD to CNTIN. FTM counting is up. CNTIN = 0xFFFC (in two's complement is equal to -4) MOD = 0x0004 -4 -3 -2 -1... -
Page 826: Freescale Semiconductor, Inc
Functional description FTM counting is up CNTIN = 0x0000 MOD = 0x0004 FTM counter TOF bit set TOF bit set TOF bit set TOF bit period of FTM counter clock period of counting = (MOD - CNTIN + 0x0001) x period of FTM counter clock = (MOD + 0x0001) x period of FTM counter clock Figure 36-169. -
Page 827: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTM counting is up MOD = 0x0005 CNTIN = 0x0015 load of CNTIN load of CNTIN FTM counter 0x0005 0x0015 0x0016 0xFFFE 0xFFFF 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0015 0x0016 TOF bit set TOF bit set TOF bit Figure 36-170. -
Page 828: Freescale Semiconductor, Inc
Functional description FTM counting is up-down CNTIN = 0x0000 MOD = 0x0004 FTM counter TOF bit set TOF bit set TOF bit period of FTM counter clock period of counting = 2 x (MOD - CNTIN) x period of FTM counter clock = 2 x MOD x period of FTM counter clock Figure 36-171. -
Page 829: Input Capture Mode
Chapter 36 FlexTimer Module (FTM) 36.4.3.4 Counter reset Any write to CNT resets the FTM counter to the value in the CNTIN register and the channels output to its initial value, except for channels in Output Compare mode. FTM counter synchronization can also be used to force the value of CNTIN into the FTM counter and the channels output to its initial value, except for channels in Output Compare mode. -
Page 830: Freescale Semiconductor, Inc
Functional description • DECAPEN = 0 • COMBINE = 0 • CPWMS = 0 • MSnB:MSnA = 0:0 • ELSnB:ELSnA ≠ 0:0 When a selected edge occurs on the channel input, the current value of the FTM counter is captured into the CnV register, at the same time the CHnF bit is set and the channel interrupt is generated if enabled by CHnIE = 1. -
Page 831: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) Note The Input Capture mode must be used only with CNTIN = 0x0000. 36.4.4.1 Filter for Input Capture mode The filter function is only available on channels 0, 1, 2, and 3. First, the input signal is synchronized by the system clock. Following synchronization, the input signal enters the filter block. -
Page 832: Output Compare Mode
Functional description system clock divided by 4 channel (n) input after the synchronizer 5-bit counter CHnFVAL[3:0] = 0010 (binary value) Time filter output Figure 36-177. Channel input filter example 36.4.5 Output Compare mode The Output Compare mode is selected when: •... -
Page 833: Edge-Aligned Pwm (Epwm) Mode
Chapter 36 FlexTimer Module (FTM) MOD = 0x0005 CnV = 0x0003 channel (n) counter channel (n) counter counter overflow overflow match match overflow channel (n) output previous value CHnF bit previous value TOF bit Figure 36-179. Example of the Output Compare mode when the match clears the channel output MOD = 0x0005 CnV = 0x0003... -
Page 834: Freescale Semiconductor, Inc
Functional description The EPWM period is determined by (MOD − CNTIN + 0x0001) and the pulse width (duty cycle) is determined by (CnV − CNTIN). The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel (n) match (FTM counter = CnV), that is, at the end of the pulse width. -
Page 835: Center-Aligned Pwm (Cpwm) Mode
Chapter 36 FlexTimer Module (FTM) MOD = 0x0008 CnV = 0x0005 counter channel (n) counter overflow match overflow channel (n) output previous value CHnF bit TOF bit Figure 36-183. EPWM signal with ELSnB:ELSnA = X:1 If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal and CHnF bit is not set even when there is the channel (n) match. -
Page 836: Freescale Semiconductor, Inc
Functional description The other channel modes are not compatible with the up-down counter (CPWMS = 1). Therefore, all FTM channels must be used in CPWM mode when (CPWMS = 1). FTM counter = CNTIN counter overflow counter overflow channel (n) match channel (n) match (FTM counting (FTM counting... -
Page 837: Combine Mode
Chapter 36 FlexTimer Module (FTM) counter counter MOD = 0x0008 overflow overflow CnV = 0x0005 channel (n) match in channel (n) match in channel (n) match in down counting up counting down counting channel (n) output CHnF bit previous value TOF bit Figure 36-186. -
Page 838: Freescale Semiconductor, Inc
Functional description The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (FTM counter = C(n)V). The CH(n+1)F bit is set and the channel (n +1) interrupt is generated, if CH(n+1)IE = 1, at the channel (n+1) match (FTM counter = C(n+1)V). -
Page 839: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTM counter C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 36-188. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V <... -
Page 840: Freescale Semiconductor, Inc
Functional description FTM counter MOD = C(n+1)V C(n)V CNTIN not fully 100% duty cycle channel (n) output with ELSnB:ELSnA = 1:0 not fully 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 Figure 36-191. Channel (n) output if (CNTIN < C(n)V < MOD) and (C(n)V is Almost Equal to CNTIN) and (C(n+1)V = MOD) FTM counter C(n+1)V... -
Page 841: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTM counter C(n+1)V CNTIN C(n)V channel (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 36-193. Channel (n) output if C(n)V and C(n+1)V are not between CNTIN and MOD FTM counter C(n+1)V = C(n)V CNTIN... -
Page 842: Freescale Semiconductor, Inc
Functional description FTM counter C(n)V = C(n+1)V = CNTIN channel (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 36-195. Channel (n) output if (C(n)V = C(n+1)V = CNTIN) FTM counter MOD = C(n+1)V =... -
Page 843: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTM counter C(n+1)V CNTIN C(n)V channel (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 36-198. Channel (n) output if (C(n)V < CNTIN) and (CNTIN < C(n+1)V < MOD) FTM counter C(n)V CNTIN... -
Page 844: Freescale Semiconductor, Inc
Functional description FTM counter C(n)V C(n+1)V CNTIN channel (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 36-200. Channel (n) output if (C(n)V > MOD) and (CNTIN < C(n+1)V < MOD) FTM counter C(n+1)V C(n)V... -
Page 845: Complementary Mode
Chapter 36 FlexTimer Module (FTM) FTM counter C(n+1)V MOD = C(n)V CNTIN channel (n) output not fully 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output not fully 100% duty cycle with ELSnB:ELSnA = X:1 Figure 36-202. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V = MOD) 36.4.8.1 Asymmetrical PWM In Combine mode, the control of the PWM signal first edge, when the channel (n) match occurs, that is, FTM counter = C(n)V, is independent of the control of the PWM signal... -
Page 846: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Functional description channel (n+1) match FTM counter channel (n) match channel (n) output with ELSnB:ELSnA = 1:0 channel (n+1) output with COMP = 0 channel (n+1) output with COMP = 1 Figure 36-203. Channel (n+1) output in Complementary mode with (ELSnB:ELSnA = 1:0) channel (n+1) match FTM counter channel (n) match... -
Page 847: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) 36.4.10.2 MOD register update The following table describes when MOD register is updated: Table 36-244. MOD register update When Then MOD register is updated CLKS[1:0] = 0:0 When MOD register is written, independent of FTMEN bit. •... -
Page 848: Pwm Synchronization
Functional description 36.4.11 PWM synchronization The PWM synchronization provides an opportunity to update the MOD, CNTIN, CnV, OUTMASK, INVCTRL and SWOCTRL registers with their buffered value and force the FTM counter to the CNTIN register value. Note • The PWM synchronization must be used only in Combine mode. -
Page 849: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) system clock write 1 to TRIG0 bit TRIG0 bit trigger_0 input synchronized trigger_0 by system clock trigger 0 event Note All hardware trigger inputs have the same behavior. Figure 36-205. Hardware trigger event with HWTRIGMODE = 0 If HWTRIGMODE = 1, then the TRIGn bit is only cleared when 0 is written to it. -
Page 850: Freescale Semiconductor, Inc
Functional description system clock system clock write 1 to SWSYNC bit write 1 to SWSYNC bit SWSYNC bit SWSYNC bit software trigger event software trigger event PWM synchronization PWM synchronization selected loading point Figure 36-206. Software trigger event 36.4.11.3 Boundary cycle and loading points The boundary cycle definition is important for the loading points for the registers MOD, CNTIN, and C(n)V. -
Page 851: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) loading points if CNTMAX = 1 or CNTMIN = 1 CNT = MOD -> CNTIN up counting mode loading points if CNTMAX = 1 CNT = (MOD - 0x0001) -> MOD up-down counting mode CNT = (CNTIN + 0x0001) -> CNTIN loading points if CNTMIN = 1 Figure 36-207. -
Page 852: Freescale Semiconductor, Inc
Functional description Figure 36-208. MOD register synchronization flowchart In the case of legacy PWM synchronization, the MOD register synchronization depends on PWMSYNC and REINIT bits according to the following description. If (SYNCMODE = 0), (PWMSYNC = 0), and (REINIT = 0), then this synchronization is made on the next selected loading point after an enabled trigger event takes place. -
Page 853: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) loading point. If the trigger event was a hardware trigger, then the trigger enable bit (TRIGn) is cleared according to Hardware trigger. Examples with software and hardware triggers follow. system clock write 1 to SWSYNC bit SWSYNC bit software trigger event selected loading point... -
Page 854: Freescale Semiconductor, Inc
Functional description system clock write 1 to SWSYNC bit SWSYNC bit software trigger event MOD register is updated Figure 36-211. MOD synchronization with (SYNCMODE = 0), (PWMSYNC = 0), (REINIT = 1), and software trigger was used system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event MOD register is updated... -
Page 855: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) 36.4.11.5 CNTIN register synchronization The CNTIN register synchronization updates the CNTIN register with its buffer value. This synchronization is enabled if (FTMEN = 1), (SYNCMODE = 1), and (CNTINC = 1). The CNTIN register synchronization can be done only by the enhanced PWM synchronization (SYNCMODE = 1). -
Page 856: Freescale Semiconductor, Inc
Functional description update OUTMASK register at update OUTMASK register by each rising edge of system clock PWM synchronization rising edge no = of system clock ? legacy = yes PWM synchronization enhanced PWM synchronization OUTMASK is updated OUTMASK is updated by hardware trigger by software trigger hardware... -
Page 857: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 0), then this synchronization is done on the next enabled trigger event. If the trigger event was a software trigger, then the SWSYNC bit is cleared on the next selected loading point. If the trigger event was a hardware trigger, then the TRIGn bit is cleared according to Hardware trigger. -
Page 858: Freescale Semiconductor, Inc
Functional description system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event OUTMASK register is updated and TRIG0 bit is cleared Figure 36-217. OUTMASK synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0), (SYNCHOM = 1), (PWMSYNC = 1), and a hardware trigger was used 36.4.11.8 INVCTRL register synchronization The INVCTRL register synchronization updates the INVCTRL register with its buffer value. -
Page 859: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) begin update INVCTRL register at update INVCTRL register by each rising edge of system clock PWM synchronization INVC bit ? SYNCMODE bit ? rising edge no = of system clock ? = yes update INVCTRL with its buffer value enhanced PWM synchronization INVCTRL is updated... -
Page 860: Freescale Semiconductor, Inc
Functional description The SWOCTRL register can be updated at each rising edge of system clock (SWOC = 0) or by the enhanced PWM synchronization (SWOC = 1 and SYNCMODE = 1) according to the following flowchart. In the case of enhanced PWM synchronization, the SWOCTRL register synchronization depends on SWSOC and HWSOC bits. -
Page 861: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) 36.4.11.10 FTM counter synchronization The FTM counter synchronization is a mechanism that allows the FTM to restart the PWM generation at a certain point in the PWM period. The channels outputs are forced to their initial value, except for channels in Output Compare mode, and the FTM counter is forced to its initial counting value defined by CNTIN register. -
Page 862: Freescale Semiconductor, Inc
Functional description Figure 36-221. FTM counter synchronization flowchart In the case of legacy PWM synchronization, the FTM counter synchronization depends on REINIT and PWMSYNC bits according to the following description. If (SYNCMODE = 0), (REINIT = 1), and (PWMSYNC = 0) then this synchronization is made on the next enabled trigger event. -
Page 863: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) system clock write 1 to SWSYNC bit SWSYNC bit software trigger event FTM counter is updated with the CNTIN register value and channel outputs are forced to their initial value Figure 36-222. FTM counter synchronization with (SYNCMODE = 0), (REINIT = 1), (PWMSYNC = 0), and software trigger was used system clock write 1 to TRIG0 bit... -
Page 864: Inverting
Functional description 36.4.12 Inverting The invert functionality swaps the signals between channel (n) and channel (n+1) outputs. The inverting operation is selected when (FTMEN = 1), (QUADEN = 0), (DECAPEN = 0), (COMBINE = 1), (COMP = 1), (CPWMS = 0), and (INVm = 1), where m represents a channel pair. -
Page 865: Software Output Control
Chapter 36 FlexTimer Module (FTM) channel (n+1) match FTM counter channel (n) match channel (n) output before the inverting channel (n+1) output before the inverting write 1 to INV(m) bit INV(m) bit buffer INVCTRL register synchronization INV(m) bit channel (n) output after the inverting channel (n+1) output after the inverting... -
Page 866: Freescale Semiconductor, Inc
Functional description channel (n+1) match FTM counter channel (n) match channel (n) output after the software output control channel (n+1) output after the software output control CH(n)OC buffer CH(n+1)OC buffer write to SWOCTRL register write to SWOCTRL register CH(n)OC bit CH(n+1)OC bit SWOCTRL register synchronization SWOCTRL register synchronization... -
Page 867: Deadtime Insertion
Chapter 36 FlexTimer Module (FTM) Note • The software output control feature must be used only in Combine mode. • The CH(n)OC and CH(n+1)OC bits should be equal. • The COMP bit must not be modified when software output control is enabled, that is, CH(n)OC = 1 and/or CH(n +1)OC = 1. -
Page 868: Freescale Semiconductor, Inc
Functional description channel (n+1) match FTM counter channel (n) match channel (n) output (before deadtime insertion) channel (n+1) output (before deadtime insertion) channel (n) output (after deadtime insertion) channel (n+1) output (after deadtime insertion) Figure 36-228. Deadtime insertion with ELSnB:ELSnA = 1:0, POL(n) = 0, and POL(n+1) = channel (n+1) match FTM counter channel (n) match... -
Page 869: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) • and the deadtime delay is greater than or equal to the channel (n) duty cycle ((C(n +1)V – C(n)V) × system clock), then the channel (n) output is always the inactive value (POL(n) bit value). •... -
Page 870: Output Mask
Functional description 36.4.15 Output mask The output mask can be used to force channels output to their inactive state through software. For example: to control a BLDC motor. Any write to the OUTMASK register updates its write buffer. The OUTMASK register is updated with its buffer value by PWM synchronization;... -
Page 871: Fault Control
Chapter 36 FlexTimer Module (FTM) Note The output mask feature must be used only in Combine mode. 36.4.16 Fault control The fault control is enabled if (FTMEN = 1) and (FAULTM[1:0] ≠ 0:0). FTM can have up to four fault inputs. FAULTnEN bit (where n = 0, 1, 2, 3) enables the fault input n and FFLTRnEN bit enables the fault input n filter. -
Page 872: Freescale Semiconductor, Inc
Functional description (FFVAL[3:0] 0000) and (FFLTRnEN*) FLTnPOL fault input n* value synchronizer fault input fault input n* polarity rising edge FAULTFn* control detector Fault filter (5-bit counter) system clock * where n = 3, 2, 1, 0 Figure 36-233. Fault input n control block diagram If the fault control and fault input n are enabled and a rising edge at the fault input n signal is detected, a fault condition has occurred and the FAULTFn bit is set. -
Page 873: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) 36.4.16.1 Automatic fault clearing If the automatic fault clearing is selected (FAULTM[1:0] = 1:1), then the channels output disabled by fault control is again enabled when the fault input signal (FAULTIN) returns to zero and a new PWM cycle begins. See the following figure. the beginning of new PWM cycles FTM counter channel (n) output... -
Page 874: Polarity Control
Functional description the beginning of new PWM cycles FTM counter channel (n) output (before fault control) FAULTIN bit channel (n) output (after fault control with manual fault clearing and POLn=0) FAULTF bit FAULTF bit is cleared NOTE The channel (n) output is after the fault control with manual fault clearing and POLn = 0. Figure 36-236. -
Page 875: Initialization
Chapter 36 FlexTimer Module (FTM) Note The polarity control must be used only in Combine mode. 36.4.18 Initialization The initialization forces the CHnOI bit value to the channel (n) output when a one is written to the INIT bit. The initialization depends on COMP and DTEN bits. The following table shows the values that channels (n) and (n+1) are forced by initialization when the COMP and DTEN bits are zero. -
Page 876: Channel Trigger Output
Functional description pair channels (m) - channels (n) and (n+1) FTM counter QUADEN DECAPEN COMBINE(m) CPWMS C(n)V MS(n)B CH(n)OC MS(n)A CH(n)OCV POL(n) POL(n+1) ELS(n)B CH(n+1)OC CH(n)OI CH(n)OM ELS(n)A CH(n+1)OCV DTEN(m) CH(n+1)OI INV(m)EN COMP(m) CH(n+1)OM FAULTEN(m) channel generation of channel (n) output output signal signal... -
Page 877: Initialization Trigger
Chapter 36 FlexTimer Module (FTM) The FTM is able to generate multiple triggers in one PWM period. Because each trigger is generated for a specific channel, several channels are required to implement this functionality. This behavior is described in the following figure. the beginning of new PWM cycles FTM counter = C5V FTM counter = C4V... -
Page 878: Freescale Semiconductor, Inc
Functional description • When there is the FTM counter synchronization • If (CNT = CNTIN), (CLKS[1:0] = 0:0), and a value different from zero is written to CLKS[1:0] bits The following figures show these cases. CNTIN = 0x0000 MOD = 0x000F CPWMS = 0 system clock 0x0C 0x0D 0x0E 0x0F 0x00 0x01 0x02 0x03 0x04 0x05... -
Page 879: Capture Test Mode
Chapter 36 FlexTimer Module (FTM) CNTIN = 0x0000 MOD = 0x000F CPWMS = 0 system clock 0x00 0x01 0x02 0x03 0x04 0x05 FTM counter CLKS[1:0] bits initialization trigger Figure 36-242. Initialization trigger is generated if (CNT = CNTIN), (CLKS[1:0] = 0:0), and a value different from zero is written to CLKS[1:0] bits The initialization trigger output provides a trigger signal that is used for on-chip modules. -
Page 880: Freescale Semiconductor, Inc
Functional description FTM counter clock set CAPTEST clear CAPTEST write to MODE CAPTEST bit FTM counter 0x1053 0x1054 0x1055 0x1056 0x78AD 0x78AE0x78AF 0x78B0 0x78AC write 0x78AC write to CNT CHnF bit 0x0300 0x78AC NOTE - FTM counter configuration: (FTMEN = 1), (QUADEN = 0), (CAPTEST = 1), (CPWMS = 0), (CNTIN = 0x0000), and (MOD = 0xFFFF) - FTM channel n configuration: input capture mode - (DECAPEN = 0), (COMBINE = 0), and (MSnB:MSnA = 0:0) Figure 36-243. -
Page 881: Dual Edge Capture Mode
Chapter 36 FlexTimer Module (FTM) Table 36-252. Clear CHnF bit when DMA = 1 CHnIE How CHnF Bit Can Be Cleared CHnF bit is cleared either when the channel DMA transfer is done or by reading CnSC while CHnF is set and then writing a 0 to CHnF bit. -
Page 882: Freescale Semiconductor, Inc
Functional description The C(n)V register stores the value of FTM counter when the selected edge by channel (n) is detected at channel (n) input. The C(n+1)V register stores the value of FTM counter when the selected edge by channel (n+1) is detected at channel (n) input. In this mode, a coherency mechanism ensures coherent data when the C(n)V and C(n +1)V registers are read. -
Page 883: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) 36.4.24.2 Continuous Capture mode The Continuous Capture mode is selected when (FTMEN = 1), (DECAPEN = 1), and (MS(n)A = 1). In this capture mode, the edges at the channel (n) input are captured continuously. The ELS(n)B:ELS(n)A bits select the initial edge to be captured, and ELS(n+1)B:ELS(n+1)A bits select the final edge to be captured. -
Page 884: Freescale Semiconductor, Inc
Functional description FTM counter channel (n) input (after the filter channel input) DECAPEN bit set DECAPEN DECAP bit set DECAP C(n)V CH(n)F bit clear CH(n)F C(n+1)V CH(n+1)F bit clear CH(n+1)F problem 1 problem 2 Note - The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user. - Problem 1: channel (n) input = 1, set DECAP, not clear CH(n)F, and clear CH(n+1)F. -
Page 885: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) FTM counter channel (n) input (after the filter channel input) DECAPEN bit set DECAPEN DECAP bit set DECAP C(n)V CH(n)F bit clear CH(n)F C(n+1)V CH(n+1)F bit clear CH(n+1)F Note - The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user. Figure 36-246. -
Page 886: Freescale Semiconductor, Inc
Functional description The following figure shows an example of the Dual Edge Capture – One-Shot mode used to measure the period between two consecutive rising edges. The DECAPEN bit selects the Dual Edge Capture mode, so it remains set. The DECAP bit is set to enable the measurement of next period. -
Page 887: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) when the second rising edge is detected, that is, the edge selected by ELS(n+1)B:ELS(n +1)A bits. The CH(n+1)F bit indicates when two edges of the period were captured and the C(n)V and C(n+1)V registers are ready for reading. FTM counter channel (n) input (after the filter... -
Page 888: Quadrature Decoder Mode
Functional description When a rising edge occurs in the channel (n) input signal, the FTM counter value is captured into channel (n) capture buffer. The channel (n) capture buffer value is transferred to C(n)V register when a falling edge occurs in the channel (n) input signal. C(n)V register has the FTM counter value when the previous rising edge occurred, and the channel (n) capture buffer has the FTM counter value when the last rising edge occurred. -
Page 889: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) PHAFLTREN CH0FVAL[3:0] synchronizer CNTIN phase A input filtered phase A signal PHAPOL PHBPOL Filter FTM counter system clock enable FTM counter up/down direction PHBFLTREN CH1FVAL[3:0] TOFDIR QUADIR synchronizer phase B input filtered phase B signal Filter Filter Figure 36-250. -
Page 890: Freescale Semiconductor, Inc
Functional description phase B (counting direction) phase A (counting rate) FTM counter +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 increment/decrement FTM counter CNTIN 0x0000 Time Figure 36-251. Quadrature Decoder – Count and Direction Encoding mode If QUADMODE = 0, then the Phase A and Phase B Encoding mode is enabled;... -
Page 891: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) phase A phase B FTM counter +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 increment/decrement FTM counter CNTIN... -
Page 892: Freescale Semiconductor, Inc
Functional description phase A phase B FTM counter increment/decrement FTM counter CNTIN 0x0000 Time set TOF set TOF clear TOFDIR clear TOFDIR Figure 36-254. FTM counter overflow in down counting for Quadrature Decoder mode 36.4.25.1 Quadrature Decoder boundary conditions The following figures show the FTM counter responding to motor jittering typical in motor position control applications. -
Page 893: Bdm Mode
Chapter 36 FlexTimer Module (FTM) phase A phase B FTM counter CNTIN 0x0000 Time Figure 36-256. Motor position jittering near maximum and minimum count value The first highlighted transition causes a jitter on the FTM counter value near the maximum count value (MOD). The second indicated transition occurs on phase A and causes the FTM counter transition between the maximum and minimum count values which are defined by MOD and CNTIN registers. -
Page 894: Intermediate Load
Functional description Table 36-253. FTM behavior when the chip Is in BDM mode (continued) BDMMODE CH(n)F Bit FTM Channels Output Writes to MOD, CNTIN, and C(n)V Registers Counter Functional can be set Functional mode Functional mode mode Note that if BDMMODE[1:0] = 2’b00 then the channels outputs remain at the value when the chip enters in BDM mode, because the FTM counter is stopped. -
Page 895: Freescale Semiconductor, Inc
Chapter 36 FlexTimer Module (FTM) The following figure shows some examples of enabled loading points. FTM counter = MOD FTM counter = C7V FTM counter = C6V FTM counter = C5V FTM counter = C4V FTM counter = C3V FTM counter = C2V FTM counter = C1V FTM counter = C0V NOTE... -
Page 896: Global Time Base (Gtb)
Functional description NOTE • If ELSjB and ELSjA bits are different from zero, then the channel (j) output signal is generated according to the configured output mode. If ELSjB and ELSjA bits are zero, then the generated signal is not available on channel (j) output. -
Page 897: Reset Overview
Chapter 36 FlexTimer Module (FTM) In the configuration described in the preceding figure, FTM modules A and B have their FTM counters enabled if at least one of the gtb_out signals from one of the FTM modules is 1. There are several possible configurations for the interconnection of the gtb_in and gtb_out signals, represented by the example glue logic shown in the figure. -
Page 898: Freescale Semiconductor, Inc
Reset overview When the FTM exits from reset: • the FTM counter and the prescaler counter are zero and are stopped (CLKS[1:0] = 00b); • the timer overflow interrupt is zero, see Timer Overflow Interrupt; • the channels interrupts are zero, see Channel (n) Interrupt;... -
Page 899: Ftm Interrupts
Chapter 36 FlexTimer Module (FTM) The following figure shows an example when the channel (n) is in Output Compare mode and the channel (n) output is toggled when there is a match. In the Output Compare mode, the channel output is not updated to its initial value when there is a write to CNT register (item 3). -
Page 900: Freescale Semiconductor, Inc
FTM Interrupts K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 901: Introduction
Chapter 37 Periodic Interrupt Timer (PIT) 37.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels. -
Page 902: Features
Signal description Peripheral registers load_value Timer 1 I i nterrupts Triggers Timer n Peripheral bus clock Figure 37-1. Block diagram of the PIT NOTE See the chip configuration details for the number of PIT channels used in this MCU. 37.1.2 Features The main features of this block are: •... -
Page 903: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Chapter 37 Periodic Interrupt Timer (PIT) 37.3 Memory map/register description This section provides a detailed description of all registers accessible in the PIT module. NOTE • Reserved registers will read as 0, writes will have no effect. • See the chip configuration details for the number of PIT channels used in this MCU. PIT memory map Absolute Width... -
Page 904: Timer Load Value Register (Pit_Ldvaln)
Memory map/register description MDIS Reset PIT_MCR field descriptions Field Description 31–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Module Disable MDIS Disables the module clock. This field must be enabled before any other setup is done. Clock for PIT timers is enabled. -
Page 905: Current Timer Value Register (Pit_Cvaln)
Chapter 37 Periodic Interrupt Timer (PIT) 37.3.3 Current Timer Value Register (PIT_CVALn) These registers indicate the current timer position. Address: 4003_7000h base + 104h offset + (16d × i), where i=0d to 3d Reset PIT_CVALn field descriptions Field Description 31–0 Current Timer Value Represents the current timer value, if the timer is enabled. -
Page 906: Timer Flag Register (Pit_Tflgn)
Memory map/register description PIT_TCTRLn field descriptions (continued) Field Description Timer is not chained. Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. Timer Interrupt Enable When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt will immediately cause an interrupt event. -
Page 907: Functional Description
Chapter 37 Periodic Interrupt Timer (PIT) 37.4 Functional description This section provides the functional description of the module. 37.4.1 General operation This section gives detailed information on the internal operation of the module. Each timer can be used to generate trigger pulses and interrupts. Each interrupt is available on a separate interrupt line. -
Page 908: Interrupts
Functional description Timer enabled Re-enable Disable timer, Start value = p1 Set new load value timer Trigger event Figure 37-24. Modifying running timer period It is also possible to change the counter period without restarting the timer by writing LDVAL with the new load value. This value will then be loaded after the next trigger event. -
Page 909: Chained Timers
Chapter 37 Periodic Interrupt Timer (PIT) 37.4.3 Chained timers When a timer has chain mode enabled, it will only count after the previous timer has expired. So if timer n-1 has counted down to 0, counter n will decrement the value by one. -
Page 910: Example Configuration For Chained Timers
Example configuration for chained timers 37.6 Example configuration for chained timers In the example configuration: • The PIT clock has a frequency of 100 MHz. • Timers 1 and 2 are available. • An interrupt shall be raised every 1 hour. The PIT module needs to be activated by writing a 0 to MCR[MDIS]. -
Page 911: Introduction
Chapter 38 Low-Power Timer (LPTMR) 38.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. -
Page 912: Lptmr Signal Descriptions
LPTMR signal descriptions Table 38-1. Modes of operation Modes Description The LPTMR operates normally. The LPTMR continues to operate normally and Wait may be configured to exit the low-power mode by generating an interrupt request. The LPTMR continues to operate normally and Stop may be configured to exit the low-power mode by generating an interrupt request. -
Page 913: Memory Map And Register Definition
Chapter 38 Low-Power Timer (LPTMR) 38.3 Memory map and register definition NOTE The LPTMR registers are reset only on a POR or LVD event. LPTMR power and reset for more details. LPTMR memory map Absolute Width Section/ address Register name Access Reset value (in bits) -
Page 914: Freescale Semiconductor, Inc
Memory map and register definition LPTMRx_CSR field descriptions (continued) Field Description Timer interrupt disabled. Timer interrupt enabled. 5–4 Timer Pin Select Configures the input source to be used in Pulse Counter mode. TPS must be altered only when the LPTMR is disabled. The input connections vary by device. See the chip configuration details for information on the connections to these inputs. -
Page 915: Low Power Timer Prescale Register (Lptmrx_Psr)
Chapter 38 Low-Power Timer (LPTMR) 38.3.2 Low Power Timer Prescale Register (LPTMRx_PSR) Address: 4004_0000h base + 4h offset = 4004_0004h Reset PRESCALE PBYP Reset LPTMRx_PSR field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–3 Prescale Value PRESCALE... -
Page 916: Low Power Timer Compare Register (Lptmrx_Cmr)
Memory map and register definition LPTMRx_PSR field descriptions (continued) Field Description 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. -
Page 917: Low Power Timer Counter Register (Lptmrx_Cnr)
Chapter 38 Low-Power Timer (LPTMR) 38.3.4 Low Power Timer Counter Register (LPTMRx_CNR) Address: 4004_0000h base + Ch offset = 4004_000Ch COUNTER Reset LPTMRx_CNR field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Counter Value COUNTER... -
Page 918: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Functional description In Pulse Counter mode with the prescaler/glitch filter bypassed, the selected input source directly clocks the CNR and no other clock source is required. To minimize power in this case, configure the prescaler clock source for a clock that is not toggling. NOTE The clock source or pulse input source selected for the LPTMR should not exceed the frequency f... -
Page 919: Lptmr Compare
Chapter 38 Low-Power Timer (LPTMR) 38.4.3.3 Glitch filter In Pulse Counter mode, when the glitch filter is enabled, the output of the glitch filter directly clocks the CNR. When the LPTMR is first enabled, the output of the glitch filter is asserted, that is, logic 1 for active-high and logic 0 for active-low. -
Page 920: Lptmr Hardware Trigger
Functional description 38.4.5 LPTMR counter The CNR increments by one on every: • Prescaler clock in Time Counter mode with prescaler bypassed • Prescaler output in Time Counter mode with prescaler enabled • Input source assertion in Pulse Counter mode with glitch filter bypassed •... -
Page 921: Introduction
Chapter 39 Carrier Modulator Transmitter (CMT) 39.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The carrier modulator transmitter (CMT) module provides the means to generate the protocol timing and carrier signals for a wide variety of encoding schemes. The CMT incorporates hardware to off-load the critical and/or lengthy timing requirements associated with signal generation from the CPU, releasing much of its bandwidth to handle other tasks such as:... -
Page 922: Block Diagram
Block diagram • Baseband • Frequency-shift key (FSK) • Direct software control of the IRO signal • Extended space operation in Time, Baseband, and FSK modes • Selectable input clock divider • Interrupt on end-of-cycle • Ability to disable the IRO signal and use as timer interrupt 39.3 Block diagram The following figure presents the block diagram of the CMT module. -
Page 923: Modes Of Operation
Chapter 39 Carrier Modulator Transmitter (CMT) Carrier generator Modulator CMT_IRO CMT registers Interrupts divider_enable Clock divider Peripheral bus clock Peripheral bus Figure 39-1. CMT module block diagram 39.4 Modes of operation The following table describes the operation of the CMT module operates in various modes. -
Page 924: Wait Mode Operation
Modes of operation Table 39-1. Modes of operation (continued) Modes Description This mode allows the carrier generator to alternate between two sets of high and low times. When operating in FSK mode, the generator will toggle between the two sets when Frequency-shift key instructed by the modulator, allowing the user to dynamically switch between two carrier frequencies without... -
Page 925: Stop Mode Operation
Chapter 39 Carrier Modulator Transmitter (CMT) 39.4.2 Stop mode operation This section describes the CMT Stop mode operations. 39.4.2.1 Normal Stop mode operation During Normal Stop mode, clocks to the CMT module are halted. No registers are affected. The CMT module will resume upon exit from Normal Stop mode because the clocks are halted. -
Page 926: Memory Map/Register Definition
Memory map/register definition 39.5.1 CMT_IRO — Infrared Output This output signal is driven by the modulator output when MSC[MCGEN] and OC[IROPEN] are set. The IRO signal starts a valid transmission with a delay, after MSC[MCGEN] bit be asserted to high, that can be calculated based on two register bits. Table 39-5 shows how to calculate this delay. -
Page 927: Cmt Carrier Generator High Data Register 1 (Cmt_Cgh1)
Chapter 39 Carrier Modulator Transmitter (CMT) CMT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4006_2007 CMT Modulator Data Register Mark Low (CMT_CMD2) Undefined 39.6.8/933 4006_2008 CMT Modulator Data Register Space High (CMT_CMD3) Undefined 39.6.9/933 39.6.10/... -
Page 928: Cmt Carrier Generator Low Data Register 1 (Cmt_Cgl1)
Memory map/register definition 39.6.2 CMT Carrier Generator Low Data Register 1 (CMT_CGL1) This data register contains the primary low value for generating the carrier output. Address: 4006_2000h base + 1h offset = 4006_2001h Read Write Reset * Notes: • x = Undefined at reset. CMT_CGL1 field descriptions Field Description... -
Page 929: Cmt Carrier Generator Low Data Register 2 (Cmt_Cgl2)
Chapter 39 Carrier Modulator Transmitter (CMT) CMT_CGH2 field descriptions (continued) Field Description The secondary carrier high time value is undefined out of reset. This register must be written to nonzero values before the carrier generator is enabled when operating in FSK mode. 39.6.4 CMT Carrier Generator Low Data Register 2 (CMT_CGL2) This data register contains the secondary low value for generating the carrier output. -
Page 930: Cmt Modulator Status And Control Register (Cmt_Msc)
Memory map/register definition CMT_OC field descriptions Field Description IRO Latch Control IROL Reads the state of the IRO latch. Writing to IROL changes the state of the IRO signal when MSC[MCGEN] is cleared and IROPEN is set. CMT Output Polarity CMTPOL Controls the polarity of the IRO signal. -
Page 931: Freescale Semiconductor, Inc
Chapter 39 Carrier Modulator Transmitter (CMT) CMT_MSC field descriptions (continued) Field Description • The modulator is not currently active and MCGEN is set to begin the initial CMT transmission. • At the end of each modulation cycle while MCGEN is set. This is recognized when a match occurs between the contents of the space period register and the down counter. -
Page 932: Cmt Modulator Data Register Mark High (Cmt_Cmd1)
Memory map/register definition CMT_MSC field descriptions (continued) Field Description 0 CPU interrupt is disabled. CPU interrupt is enabled. Modulator and Carrier Generator Enable MCGEN Setting MCGEN will initialize the carrier generator and modulator and will enable all clocks. When enabled, the carrier generator and modulator will function continuously. When MCGEN is cleared, the current modulator cycle will be allowed to expire before all carrier and modulator clocks are disabled to save power and the modulator output is forced low. -
Page 933: Cmt Modulator Data Register Mark Low (Cmt_Cmd2)
Chapter 39 Carrier Modulator Transmitter (CMT) 39.6.8 CMT Modulator Data Register Mark Low (CMT_CMD2) The contents of this register are transferred to the modulator down counter upon the completion of a modulation period. Address: 4006_2000h base + 7h offset = 4006_2007h Read MB[7:0] Write... -
Page 934: Cmt Modulator Data Register Space Low (Cmt_Cmd4)
Memory map/register definition 39.6.10 CMT Modulator Data Register Space Low (CMT_CMD4) The contents of this register are transferred to the space period register upon the completion of a modulation period. Address: 4006_2000h base + 9h offset = 4006_2009h Read SB[7:0] Write Reset * Notes:... -
Page 935: Cmt Direct Memory Access Register (Cmt_Dma)
Chapter 39 Carrier Modulator Transmitter (CMT) CMT_PPS field descriptions (continued) Field Description 0100 Bus clock ÷ 5 0101 Bus clock ÷ 6 0110 Bus clock ÷ 7 0111 Bus clock ÷ 8 1000 Bus clock ÷ 9 1001 Bus clock ÷ 10 1010 Bus clock ÷... -
Page 936: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Functional description 39.7 Functional description The CMT module primarily consists of clock divider, carrier generator, and modulator. 39.7.1 Clock divider The CMT was originally designed to be based on an 8 MHz bus clock that could be divided by 1, 2, 4, or 8 according to the specification. To be compatible with higher bus frequency, the primary prescaler (PPS) was developed to receive a higher frequency and generate a clock enable signal called intermediate frequency (IF). -
Page 937: Freescale Semiconductor, Inc
Chapter 39 Carrier Modulator Transmitter (CMT) Table 39-19. Clock divider Min. Min. carrier generator Bus clock Carrier generator period MSC[CMTDIV] modulator period (MHz) resolution (μs) (μs) (μs) 0.125 0.25 0.25 The possible duty cycle options depend upon the number of counts required to complete the carrier period. -
Page 938: Freescale Semiconductor, Inc
Functional description Figure 39-15. Carrier generator block diagram The high/low time counter is an 8-bit up counter. After each increment, the contents of the counter are compared with the appropriate high or low count value register. When the compare value is reached, the counter is reset to a value of 0x01, and the compare is redirected to the other count value register. -
Page 939: Modulator
Chapter 39 Carrier Modulator Transmitter (CMT) The duty cycle of the carrier signal is controlled by varying the ratio of high time to low + high time. As the input clock period is fixed, the duty cycle resolution will be proportional to the number of counts required to generate the desired carrier period. -
Page 940: Freescale Semiconductor, Inc
Functional description When a match is obtained, the cycle repeats by opening the modulator gate, reloading the counter with the contents of CMD1 and CMD2, and reloading the modulation space period register with the contents of CMD3 and CMD4. The modulation space period is activated when the carrier signal is low to prohibit cutting off the high pulse of a carrier signal. -
Page 941: Freescale Semiconductor, Inc
Chapter 39 Carrier Modulator Transmitter (CMT) • The modulation mark period consists of an integer number of (CMTCLK ÷ 8) clock periods. • The modulation space period consists of 0 or an integer number of (CMTCLK ÷ 8) clock periods. With an 8 MHz IF and MSC[CMTDIV] = 00, the modulator resolution is 1 μs and has a maximum mark and space period of about 65.535 ms each . -
Page 942: Freescale Semiconductor, Inc
Functional description In this mode, the modulator output will be at a logic 1 for the duration of the mark period and at a logic 0 for the duration of a space period. See Figure 39-17 for an example of the output for both Baseband and Time modes. -
Page 943: Extended Space Operation
Chapter 39 Carrier Modulator Transmitter (CMT) • Secondary carrier high count = 0x03 • Secondary carrier low count = 0x01 Carrier out (fcg) Modulator gate Mark1 Space1 Mark2 Space2 Mark1 Mark2 Space1 IRO signal Figure 39-18. Example: CMT output in FSK mode 39.7.4 Extended space operation In either Time, Baseband, or FSK mode, the space period can be made longer than the maximum possible value of the space period register. -
Page 944: Freescale Semiconductor, Inc
Functional description Figure 39-19. Extended space operation 39.7.4.2 EXSPC operation in FSK mode In FSK mode, the modulator continues to count carrier out clocks, alternating between the primary and secondary registers at the end of each modulation period. To calculate the length of an extended space in FSK mode, it is required to know whether MSC[EXSPC] was set on a primary or secondary modulation period, and the total number of both primary and secondary modulation periods completed while MSC[EXSPC] is high. -
Page 945: Cmt Interrupts And Dma
Chapter 39 Carrier Modulator Transmitter (CMT) 39.8 CMT interrupts and DMA The CMT generates an interrupt request or a DMA transfer request according to MSC[EOCIE], MSC[EOCF], DMA[DMA] bits. Table 39-23. DMA transfer request x CMT interrupt request MSC[EOCF] DMA[DMA] MSC[EOCIE] DMA transfer request CMT interrupt request MSC[EOCF] is set:... -
Page 946: Freescale Semiconductor, Inc
CMT interrupts and DMA • Loading the down-counter with the contents of CMD1:CMD2 • Loading the space period register with the contents of CMD3:CMD4 The EOC interrupt provides a means for the user to reload new mark/space values into the modulator data registers. Modulator data register updates will take effect at the end of the current modulation cycle. -
Page 947: Introduction
Chapter 40 Real Time Clock (RTC) 40.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 40.1.1 Features The RTC module features include: • Independent power supply, POR, and 32 kHz crystal oscillator •... -
Page 948: Rtc Signal Descriptions
Register definition During chip power-down, RTC is powered from the backup power supply (VBAT) and is electrically isolated from the rest of the chip but continues to increment the time counter (if enabled) and retain the state of the RTC registers. The RTC registers are not accessible. -
Page 949: Rtc Time Seconds Register (Rtc_Tsr)
Chapter 40 Real Time Clock (RTC) Write accesses to any register by non-supervisor mode software, when the supervisor access bit in the control register is clear, will terminate with a bus error. Read accesses by non-supervisor mode software complete as normal. Writing to a register protected by the write access register or lock register does not generate a bus error, but the write will not complete. -
Page 950: Rtc Time Prescaler Register (Rtc_Tpr)
Register definition 40.2.2 RTC Time Prescaler Register (RTC_TPR) Address: 4003_D000h base + 4h offset = 4003_D004h Reset RTC_TPR field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Time Prescaler Register When the time counter is enabled, the TPR is read only and increments every 32.768 kHz clock cycle. -
Page 951: Freescale Semiconductor, Inc
Chapter 40 Real Time Clock (RTC) RTC_TCR field descriptions Field Description 31–24 Compensation Interval Counter Current value of the compensation interval counter. If the compensation interval counter equals zero then it is loaded with the contents of the CIR. If the CIC does not equal zero then it is decremented once a second. -
Page 952: Rtc Control Register (Rtc_Cr)
Register definition 40.2.5 RTC Control Register (RTC_CR) Address: 4003_D000h base + 10h offset = 4003_D010h Reset SC2P SC4P SC8P WPE SWR Reset RTC_CR field descriptions Field Description 31–15 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. -
Page 953: Freescale Semiconductor, Inc
Chapter 40 Real Time Clock (RTC) RTC_CR field descriptions (continued) Field Description Disable the load. Enable the additional load. Oscillator 16pF Load Configure SC16P Disable the load. Enable the additional load. Clock Output CLKO The 32 kHz clock is output to other peripherals. The 32 kHz clock is not output to other peripherals. -
Page 954: Rtc Status Register (Rtc_Sr)
Register definition 40.2.6 RTC Status Register (RTC_SR) Address: 4003_D000h base + 14h offset = 4003_D014h Reset Reset RTC_SR field descriptions Field Description 31–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Time Counter Enable When time counter is disabled the TSR register and TPR register are writeable, but do not increment. -
Page 955: Rtc Lock Register (Rtc_Lr)
Chapter 40 Real Time Clock (RTC) 40.2.7 RTC Lock Register (RTC_LR) Address: 4003_D000h base + 18h offset = 4003_D018h Reset Reset RTC_LR field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. -
Page 956: Rtc Interrupt Enable Register (Rtc_Ier)
Register definition 40.2.8 RTC Interrupt Enable Register (RTC_IER) Address: 4003_D000h base + 1Ch offset = 4003_D01Ch Reset Reserved TSIE TAIE TOIE TIIE Reset RTC_IER field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 7–5 This field is reserved. -
Page 957: Rtc Write Access Register (Rtc_War)
Chapter 40 Real Time Clock (RTC) 40.2.9 RTC Write Access Register (RTC_WAR) Address: 4003_D000h base + 800h offset = 4003_D800h Reset IERW LRW SRW CRW Reset RTC_WAR field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Interrupt Enable Register Write IERW After being cleared, this bit is set only by system reset. -
Page 958: Rtc Read Access Register (Rtc_Rar)
Register definition RTC_WAR field descriptions (continued) Field Description Writes to the Time Compensation Register are ignored. Writes to the Time Compensation Register complete as normal. Time Alarm Register Write TARW After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset. Writes to the Time Alarm Register are ignored. -
Page 959: Functional Description
Chapter 40 Real Time Clock (RTC) RTC_RAR field descriptions (continued) Field Description After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset. Reads to the Lock Register are ignored. Reads to the Lock Register complete as normal. -
Page 960: Power, Clocking, And Reset
Functional description 40.3.1 Power, clocking, and reset The RTC is an always powered block that remains active in all low power modes and is powered by the battery power supply (VBAT). The battery power supply ensures that the RTC registers retain their state during chip power-down and that the RTC time counter remains operational. -
Page 961: Time Counter
Chapter 40 Real Time Clock (RTC) 40.3.1.3 Supervisor access When the supervisor access control bit is clear, only supervisor mode software can write to the RTC registers, non-supervisor mode software will generate a bus error. Both supervisor and non-supervisor mode software can always read the RTC registers. 40.3.2 Time counter The time counter consists of a 32-bit seconds counter that increments once every second and a 16-bit prescaler register that increments once every 32.768 kHz clock cycle. -
Page 962: Time Alarm
Functional description Crystal compensation can be supported by using firmware and crystal characteristics to determine the compensation amount. Temperature compensation can be supported by firmware that periodically measures the external temperature via ADC and updates the compensation register based on a look-up table that specifies the change in crystal frequency over temperature. -
Page 963: K30 Sub-Family Reference Manual, Rev. 1.1, Dec
Chapter 40 Real Time Clock (RTC) time seconds and prescaler registers to be initialized whenever time is invalidated, while preventing the time seconds and prescaler registers from being changed on the fly. When LR[SRL] is set, CR[UM] has no effect on SR[TCE]. 40.3.6 Register lock The lock register can be used to block write accesses to certain registers until the next VBAT POR or software reset. -
Page 964: Freescale Semiconductor, Inc
Functional description K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc. -
Page 965: Introduction
Chapter 41 CAN (FlexCAN) 41.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The FlexCAN module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification. A general block diagram is shown in the following figure, which describes the main sub-blocks implemented in the FlexCAN module, including one associated memory for storing Message Buffers, Rx Global Mask Registers, Rx Individual Mask Registers, Rx FIFO and Rx FIFO ID Filters. -
Page 966: Overview
Introduction Peripheral Bus Interface Address, Data, Clocks, Interrupts Registers Message Buffers CAN Control Host Interface (MBs) Arbitration Matching CAN Protocol Engine CAN Rx CAN Tx Chip CAN Transceiver CAN Bus Figure 41-1. FlexCAN block diagram 41.1.1 Overview The CAN protocol was primarily designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. -
Page 967: Flexcan Module Features
Chapter 41 CAN (FlexCAN) 41.1.2 FlexCAN module features The FlexCAN module includes these distinctive legacy features: • Full implementation of the CAN protocol specification, Version 2.0B • Standard data and remote frames • Extended data and remote frames • Zero to eight bytes data length •... -
Page 968: Modes Of Operation
Introduction • Short latency time due to an arbitration scheme for high-priority messages • Low power modes, with programmable wake up on bus activity New major features are also provided: • Remote request frames may be handled automatically or by software •... -
Page 969: Freescale Semiconductor, Inc
Chapter 41 CAN (FlexCAN) • Listen-Only mode: The module enters this mode when the LOM bit in the Control 1 Register is asserted. In this mode, transmission is disabled, all error counters are frozen and the module operates in a CAN Error Passive mode. Only messages acknowledged by another CAN station will be received. -
Page 970: Flexcan Signal Descriptions
FlexCAN signal descriptions 41.2 FlexCAN signal descriptions The FlexCAN module has two I/O signals connected to the external MCU pins. These signals are summarized in the following table and described in more detail in the next sub-sections. Table 41-1. FlexCAN signal descriptions Signal Description CAN Rx... -
Page 971: Freescale Semiconductor, Inc
Chapter 41 CAN (FlexCAN) Each individual register is identified by its complete name and the corresponding mnemonic. The access type can be Supervisor (S) or Unrestricted (U). Most of the registers can be configured to have either Supervisor or Unrestricted access by programming the SUPV bit in the MCR Register. -
Page 972: Freescale Semiconductor, Inc
Memory map/register definition CAN memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4002_4000 Module Configuration Register (CAN0_MCR) D890_000Fh 41.3.2/974 4002_4004 Control 1 register (CAN0_CTRL1) 0000_0000h 41.3.3/979 4002_4008 Free Running Timer (CAN0_TIMER) 0000_0000h 41.3.4/982 4002_4010 Rx Mailboxes Global Mask Register (CAN0_RXMGMASK) FFFF_FFFFh... -
Page 973: Freescale Semiconductor, Inc
Chapter 41 CAN (FlexCAN) CAN memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 41.3.17/ 4002_48A8 Rx Individual Mask Registers (CAN0_RXIMR10) Undefined 1001 41.3.17/ 4002_48AC Rx Individual Mask Registers (CAN0_RXIMR11) Undefined 1001 41.3.17/ 4002_48B0 Rx Individual Mask Registers (CAN0_RXIMR12) Undefined... -
Page 974: Module Configuration Register (Canx_Mcr)
Memory map/register definition 41.3.2 Module Configuration Register (CANx_MCR) This register defines global system configurations, such as the module operation modes and the maximum message buffer configuration. Address: 4002_4000h base + 0h offset = 4002_4000h MDIS FRZ RFEN IRMQ Reset IDAM MAXMB Reset CANx_MCR field descriptions... -
Page 975: Freescale Semiconductor, Inc
Chapter 41 CAN (FlexCAN) CANx_MCR field descriptions (continued) Field Description Not enabled to enter Freeze mode. Enabled to enter Freeze mode. Rx FIFO Enable RFEN This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is set, MBs 0 to 5 cannot be used for normal reception and transmission because the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used as Rx FIFO ID Filter Table elements. -
Page 976: Freescale Semiconductor, Inc
Memory map/register definition CANx_MCR field descriptions (continued) Field Description Freeze Mode Acknowledge FRZACK This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler is stopped. The Freeze mode request cannot be granted until current transmission or reception processes have finished. Therefore the software can poll the FRZACK bit to know when FlexCAN has actually entered Freeze mode. -
Page 977: Freescale Semiconductor, Inc
Chapter 41 CAN (FlexCAN) CANx_MCR field descriptions (continued) Field Description NOTE: LPMACK will be asserted within 180 CAN bits from the low-power mode request by the CPU, and negated within 2 CAN bits after the low-power mode request removal (see Section "Protocol Timing"). -
Page 978: Freescale Semiconductor, Inc
Memory map/register definition CANx_MCR field descriptions (continued) Field Description NOTE: When MCR[AEN] is asserted, only the abort mechanism (see Section "Transmission Abort Mechanism") must be used for updating Mailboxes configured for transmission. CAUTION: Writing the Abort code into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is asserted. -
Page 979: Control 1 Register (Canx_Ctrl1)
Chapter 41 CAN (FlexCAN) 41.3.3 Control 1 register (CANx_CTRL1) This register is defined for specific FlexCAN control features related to the CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling (Bus-Off, Error, Warning). -
Page 980: Freescale Semiconductor, Inc
Memory map/register definition CANx_CTRL1 field descriptions (continued) Field Description This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time. The valid programmable values are 1–7. This field can be written only in Freeze mode because it is blocked by hardware in other modes. -
Page 981: Freescale Semiconductor, Inc
Chapter 41 CAN (FlexCAN) CANx_CTRL1 field descriptions (continued) Field Description This bit provides a mask for the Rx Warning Interrupt associated with the RWRNINT flag in the Error and Status Register. This bit is read as zero when MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is asserted. -
Page 982: Free Running Timer (Canx_Timer)
Memory map/register definition CANx_CTRL1 field descriptions (continued) Field Description acknowledged by another CAN station will be received. If FlexCAN detects a message that has not been acknowledged, it will flag a BIT0 error without changing the REC, as if it was trying to acknowledge the message. -
Page 983: Rx Mailboxes Global Mask Register (Canx_Rxmgmask)
Chapter 41 CAN (FlexCAN) Address: 4002_4000h base + 8h offset = 4002_4008h TIMER Reset CANx_TIMER field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Timer Value TIMER Contains the free-running counter value. -
Page 984: Rx 14 Mask Register (Canx_Rx14Mask)
Memory map/register definition CANx_RXMGMASK field descriptions (continued) Field Description SMB[RTR] CTRL2[RRS] CTRL2[EACE Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved note note MG[28:0] MG[31:29] MG[31] MG[30] MG[28:0] MG[29] MG[31:0] MG[28:0] MG[31:29] MG[31] MG[30] MG[28:0] MG[29] 1. RTR bit of the Incoming Frame. It is saved into an auxiliary MB called Rx Serial Message Buffer (Rx SMB). -
Page 985: Rx 15 Mask Register (Canx_Rx15Mask)
Chapter 41 CAN (FlexCAN) CANx_RX14MASK field descriptions (continued) Field Description The corresponding bit in the filter is "don’t care." The corresponding bit in the filter is checked. 41.3.7 Rx 15 Mask register (CANx_RX15MASK) This register is located in RAM. RX15MASK is provided for legacy application support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. -
Page 986: Freescale Semiconductor, Inc
Memory map/register definition The following are the basic rules for FlexCAN bus state transitions: • If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to 128, the FLTCONF field in the Error and Status Register is updated to reflect ‘Error Passive’... -
Page 987: Error And Status 1 Register (Canx_Esr1)
Chapter 41 CAN (FlexCAN) CANx_ECR field descriptions (continued) Field Description 7–0 Transmit Error Counter TXERRCNT 41.3.9 Error and Status 1 register (CANx_ESR1) This register reflects various error conditions, some general status of the device and it is the source of interrupts to the CPU. The CPU read action clears bits 15-10. -
Page 988: Freescale Semiconductor, Inc
Memory map/register definition FLTCONF Reset CANx_ESR1 field descriptions Field Description 31–19 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CAN Synchronization Status SYNCH This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process. -
Page 989: Freescale Semiconductor, Inc
Chapter 41 CAN (FlexCAN) CANx_ESR1 field descriptions (continued) Field Description NOTE: This bit is not set by a transmitter in case of arbitration field or ACK slot, or in case of a node sending a passive error flag that detects dominant bits. No such occurrence. -
Page 990: Freescale Semiconductor, Inc
Memory map/register definition CANx_ESR1 field descriptions (continued) Field Description No such occurrence. RXERRCNT is greater than or equal to 96. This bit indicates when CAN bus is in IDLE state. See the table in the overall CAN_ESR1 register IDLE description. No such occurrence. -
Page 991: Interrupt Masks 1 Register (Canx_Imask1)
Chapter 41 CAN (FlexCAN) CANx_ESR1 field descriptions (continued) Field Description This field applies when FlexCAN is in low-power mode: • Stop mode When a recessive-to-dominant transition is detected on the CAN bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag is masked. -
Page 992: Interrupt Flags 1 Register (Canx_Iflag1)
Memory map/register definition 41.3.11 Interrupt Flags 1 register (CANx_IFLAG1) This register defines the flags for the 32 Message Buffer interrupts for MB31 to MB0. It contains one interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding IFLAG1 bit. If the corresponding IMASK1 bit is set, an interrupt will be generated. -
Page 993: Freescale Semiconductor, Inc
Chapter 41 CAN (FlexCAN) CANx_IFLAG1 field descriptions Field Description 31–8 Buffer MB Interrupt BUF31TO8I Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to MB8. The corresponding buffer has no occurrence of successfully completed transmission or reception. The corresponding buffer has successfully completed transmission or reception. Buffer MB7 Interrupt Or "Rx FIFO Overflow"... -
Page 994: Control 2 Register (Canx_Ctrl2)
Memory map/register definition CANx_IFLAG1 field descriptions (continued) Field Description The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. 41.3.12 Control 2 register (CANx_CTRL2) This register contains control bits for CAN errors, FIFO features, and mode selection. Address: 4002_4000h base + 34h offset = 4002_4034h RFFN TASD... -
Page 995: Freescale Semiconductor, Inc
Chapter 41 CAN (FlexCAN) CANx_CTRL2 field descriptions (continued) Field Description Considering that the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should be programmed with a value correponding to a number of filters not greater than the number of available memory words which can be calculated as follows: (SETUP_MB - 6) ×... -
Page 996: Freescale Semiconductor, Inc
Memory map/register definition CANx_CTRL2 field descriptions (continued) Field Description The optimal arbitration timing is that in which the last MB is scanned right before the first bit of the Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial clock ratio is high and the CAN baud rate is low then the arbitration can be delayed and vice-versa. -
Page 997: Error And Status 2 Register (Canx_Esr2)
Chapter 41 CAN (FlexCAN) CANx_CTRL2 field descriptions (continued) Field Description This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process. This bit does not affect matching for Rx FIFO. This bit can be written only in Freeze mode because it is blocked by hardware in other modes. -
Page 998: Crc Register (Canx_Crcr)
Memory map/register definition CANx_ESR2 field descriptions (continued) Field Description This bit indicates whether IMB and LPTM contents are currently valid or not. VPS is asserted upon every complete Tx arbitration process unless the CPU writes to Control and Status word of a Mailbox that has already been scanned, that is, it is behind Tx Arbitration Pointer, during the Tx arbitration process. -
Page 999: Rx Fifo Global Mask Register (Canx_Rxfgmask)
Chapter 41 CAN (FlexCAN) CANx_CRCR field descriptions Field Description 31–23 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 22–16 CRC Mailbox MBCRC This field indicates the number of the Mailbox corresponding to the value in TXCRC field. This field is reserved. -
Page 1000: Rx Fifo Information Register (Canx_Rxfir)
Memory map/register definition CANx_RXFGMASK field descriptions (continued) Field Description Rx FIFO ID Identifier Acceptance Filter Fields Filter Table RXIDA RXIDB RXIDC Reserved Elements Format (MCR[IDAM]) FGM[31] FGM[30] FGM[29:1] FGM[0] FGM[31], FGM[30], FGM[29:16], FGM[15] FGM[14] FGM[13:0] FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0] 1. If MCR[IDAM] field is equivalent to the format B only the fourteen most significant bits of the Identifier of the incoming frame are compared with the Rx FIFO filter.
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