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states between beats (BSCY).
with BSCY=1.
CLKOUT
ADDR[3:31]
RD_WR
TSIZ[0:1]
TS
BDIP
DATA[0:31]
TA
CSx
OE
Figure 14-25. Burst 32-bit Read Cycle, One Wait State between Beats, TBDIP=0
When using TBDIP=1, the BDIP behavior changes to toggle between every beat when BSCY is a non-zero
value.
Figure 14-26
shows an example of the TBDIP=1 timing for the same 4-beat burst shown in
Figure
14-25.
Freescale Semiconductor
Figure 14-25
shows an example of the TBDIP=0 timing for a 4-beat burst
ADDR[29:31] = 000
00
Expects more data
Wait State
Wait State
MPC5644A Microcontroller Reference Manual, Rev. 6
DATA is valid
Wait State
Wait State
External Bus Interface (EBI)
315
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