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Resets
PLLREF
0
1
The Reset Status Register (SIU_RSR) gives the source, or sources, of the last reset and indicates whether
a glitch has occurred on the RESET pin. The SIU_RSR is updated for all reset sources except JTAG reset.
All reset sources initiate execution of the Boot Assist Module (BAM) program with the exception of the
Software External Reset.
The Reset Configuration Half Word (RCHW) determines the MCU configuration after reset. The RCHW
is stored in internal flash, or a default configuration is used. During reset, the RCHW is read from internal
flash memory. The BOOTCFG[0:1]
BAM program reads the value of the BOOTCFG[0:1] pins from field SIU_RSR[BOOTCFG], then reads
the RCHW from the specified location, and then uses the RCHW value to determine and execute the
specified boot procedure. Note: the reset controller latches the value on the BOOTCFG input to the SIU
four clock cycles prior to the negation of RSTOUT.
4.2
Reset vector
The reset vector for this device is 0xFFFF_FFFC. This is a fixed location in the BAM. The BAM program
executes after every internal reset. The BAM program determines where to branch after its execution
completes based on the value on the BOOTCFG[0:1] pins. See the BAM chapter's functional description
for details on the BAM program operation and branch location to application software.
4.3
Reset pins
4.3.1
RESET
The RESET pin is an active low input. The RESET pin must be asserted by an external device during a
power-on or whenever an external reset is required. The internal reset signal asserts only if the RESET pin
asserts for 10 clock cycles. Assertion of the RESET pin while the reset state machine is already processing
a reset causes the reset cycle to start over. The RESET pin has a glitch detector which detects spikes greater
than two clocks in duration that fall below the switch point of the input buffer logic of the VDDEH input
pins. The switch point lies between the maximum VIL and minimum VIH specifications for the VDDEH
input pins.
Figure 4-1
and
4.3.2
RSTOUT
The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven
to the low state by the MCU for all internal and external reset sources.
Depending on the PLL configuration, External Reference or Crystal Mode, the RSTOUT pin is asserted
after a delay defined in
Table
1. BOOTCFG[0] is not available on all packages.
94
Table 4-2. PLLREF options
Normal mode with external reference
Normal mode with crystal reference
1
pins are defined in
Figure 4-2
show logic flows of the reset state machine on assertion of RESET.
4-3, plus four cycles for sampling of the configuration pins.
MPC5644A Microcontroller Reference Manual, Rev. 6
Clock mode
Chapter 16, System Integration Unit (SIU).
The
Freescale Semiconductor
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