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When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the Priority Ceiling Protocol (PCP) for coherent accesses. By providing a modifiable priority
mask, the priority level can be raised temporarily so that no task can preempt another task that shares the
same resource.
Multiple processors can assert interrupt requests to each other through software configurable interrupt
requests, i.e., by using application software to assert an interrupt request. These same software
configurable interrupt requests also can be used to break the work involved in servicing an interrupt
request into a high priority portion and a low priority portion. The high priority portion is initiated by a
peripheral interrupt request, but the ISR can assert a software configurable interrupt request to finish the
servicing in a low priority ISR.
15.2.3
Features
Features include the following:
•
Total number of interrupt vectors is 486, of which:
— 279 are peripheral interrupt vectors
— 8 are software configurable sources
— 199 are reserved sources
•
9-bit unique vector for each interrupt request source in hardware vector mode.
•
Each interrupt source can be programmed to one of 16 priorities.
•
Preemption.
— Preemptive prioritized interrupt requests to processor.
— ISR at a higher priority preempts ISRs or tasks at lower priorities.
— Automatic pushing or popping of preempted priority to or from a LIFO.
— Ability to modify the ISR or task priority. Modifying the priority can be used to implement the
PCP for accessing shared resources.
•
Low latency–three clocks from receipt of interrupt request from peripheral to interrupt request to
processor.
15.2.4
Modes of operation
The interrupt controller has two handshaking modes with the processor: software vector mode and
hardware vector mode. The state of the hardware vector enable bit, INTC_MCR[HVEN], determines
which mode is used.
In debug mode, the interrupt controller operation is identical to its normal operation of software vector
mode or hardware vector mode.
15.2.4.1
Software vector mode
In the software vector mode, there is a common interrupt exception handler address that is calculated by
hardware as shown in
Figure
to the offset contained in the external input interrupt vector offset register (IVOR4).
Freescale Semiconductor
15-5. The upper half of the interrupt vector prefix register (IVPR) is added
MPC5644A Microcontroller Reference Manual, Rev. 6
Interrupt Controller (INTC)
345
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