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Chapter 16
System Integration Unit (SIU)
16.1
Overview
The System integration unit (SIU) controls this device's reset configuration, pad configuration, external
interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation.
The reset configuration block contains the external pin boot configuration logic. The pad configuration
block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and
discrete input/output control of the MCU I/O pins. The reset controller performs reset monitoring of
internal and external reset sources, and drives the RSTOUT pin. The SIU is accessed by the core through
the peripheral bus.
16.2
Features
•
System configuration
— MCU reset configuration via external pins
— Pad configuration control
•
System reset monitoring and generation
— Power-on reset support
— Reset Status Register provides last reset source to software
— Glitch detection on reset input
— Software controlled reset assertion
•
External interrupt
— 15 interrupt requests
— 1 Non-Maskable/Critical Interrupt request (NMI)
— Rising or falling edge event detection
— Programmable digital filter for glitch rejection
•
GPIO
— GPIO function on 163 I/O pins
— Dedicated input and output registers for each GPIO pin
•
Internal multiplexing
— Allows serial and parallel chaining of DSPIs
— Allows flexible selection of eQADC trigger inputs
— Allows selection of interrupt requests between external pins and DSPI
— Allows selection of some eTPU inputs from external eTPU pins or deserialized output from the
DSPI module
— Allows selection of serialized data source for the DSPI
Freescale Semiconductor
MPC5644A Microcontroller Reference Manual, Rev. 6
System Integration Unit (SIU)
381
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