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17.4.2.2
Synthesizer Status Register (SYNSR)
Offset 0x0004
0
1
R
0
0
W
Reset
0
0
16
17
18
R
0
0
W
Reset
0
0
1
Reset value is determined by the state of the PLLREF pin.
Field
0–21
Reserved, should be cleared.
22
Loss-of-lock flag
LOLF
This bit provides the interrupt request flag for the loss-of-lock. To clear the flag, software must write a 1 to
the bit. Writing 0 has no effect. This flag bit is sticky in the sense that if lock is reacquired, the bit will remain
set until cleared by either writing 1 or asserting reset. It will not be asserted when lock is lost due to system
reset, write to the FMPLL_SYNCR in legacy mode which modifies the PREDIV or MFD fields, or write to
FMPLL_ESYNCR1 in enhanced mode which modifies the EMODE, EPREDIV, EMFD or CLKCFG[1:0]
fields. Furthermore, it is not asserted if the loss-of-lock condition was detected while the FMPLL is in
bypass mode. Nevertheless, going from normal to bypass will not automatically clear the flag if it was
asserted while the FMPLL was in normal mode. See
0 No loss of lock detected. Interrupt service not requested.
1 Loss of lock detected. Interrupt service requested.
23
Loss-of-clock
LOC
This bit is an indication of whether a loss-of-clock condition is present. If LOC = 0, the system clocks are
operating normally. If LOC = 1, the system clocks have failed due to a reference or VCO failure. If a
loss-of-clock condition occurs which sets this bit and the clocks later return to normal, this bit will be
cleared. A loss-of-clock condition can only be detected if LOCEN = 1. Furthermore, the LOC bit is not
asserted when the FMPLL is in bypass mode (because, in bypass, the VCO clock is not monitored and a
loss-of-clock on the reference clock causes reset). See
0 No loss-of-clock detected. Clocks are operating normally.
1 Loss-of-clock detected. Clocks are not operating normally.
Freescale Semiconductor
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
19
20
21
22
LOL
0
0
0
0
F
w1c
0
0
0
0
0
Figure 17-3. Synthesizer Status Register (SYNSR)
Table 17-7. SYNSR field descriptions
MPC5644A Microcontroller Reference Manual, Rev. 6
Frequency-modulated phase locked loop (FMPLL)
7
8
9
10
0
0
0
0
0
0
0
0
23
24
25
26
27
MOD
PLL
PLL
LOCK
LOC
E
SEL
REF
1
0
0
0
–
Description
Section 17.5.3, Lock
Section 17.5.4, Loss-of-clock
Access: User read/write
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
28
29
30
31
LOC
LOC
0
0
S
K
F
w1c
0
0
0
0
0
detection.
detection.
567
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