Block Diagram - NXP Semiconductors MPC5644A Reference Manual

5.3.2

Block diagram

EXTAL
XTAL OSC
XTAL
PLLREF
RCOSC
CLKIN
/IDF
5.3.3 System clock sources
The on-chip MHz oscillator, PLL and the top level pin are the possible sources of system clock. The system
clock can be generated using any of the following options:
• PLL disabled
— MHz crystal oscillator with crystal as the reference
— MHz crystal oscillator bypassed
• PLL enabled
— MHz crystal oscillator (with crystal as the reference) output used as PLL reference frequency
— MHz crystal oscillator (bypassed) output used as PLL reference frequency
Freescale Semiconductor
1
CLKIN
0
FMPLL
IDF NDIV ODF
Control & Status Registers
loss of
VCO
Clock Quality Monitor
(CQM)
Figure 5-1. System clock diagram
Charge pump
PFD
Low Pass Filter
Controller
Figure 5-2. FMPLL
MPC5644A Microcontroller Reference Manual, Rev. 6
clkcfg[0]
0
1
PHI
PD Lock
loss of
Reference
VCO
/NDIV
FM
Operating Modes and Clocking
bypass_sysdiv
siu_system_div[1:0]
SYSDIV
/2, /4, /8, /16
system
clock
PHI
/ODF
PHI1
/6
FMPLL
107