NXP Semiconductors MPC5644A Reference Manual page 144

Enhanced Direct Memory Access Controller (eDMA)
Offset from
EDMA_BASE
EDMA_BASE + 0x15A0 EDMA_TCD45—eDMA transfer control descriptor 45
EDMA_BASE + 0x15C0 EDMA_TCD46—eDMA transfer control descriptor 46
EDMA_BASE + 0x15E0 EDMA_TCD47—eDMA transfer control descriptor 47
EDMA_BASE + 0x1600 EDMA_TCD48—eDMA transfer control descriptor 48
EDMA_BASE + 0x1620 EDMA_TCD49—eDMA transfer control descriptor 49
EDMA_BASE + 0x1640 EDMA_TCD50—eDMA transfer control descriptor 50
EDMA_BASE + 0x1660 EDMA_TCD51—eDMA transfer control descriptor 51
EDMA_BASE + 0x1680 EDMA_TCD52—eDMA transfer control descriptor 52
EDMA_BASE + 0x16A0 EDMA_TCD53—eDMA transfer control descriptor 53
EDMA_BASE + 0x16C0 EDMA_TCD54—eDMA transfer control descriptor 54
EDMA_BASE + 0x16E0 EDMA_TCD55—eDMA transfer control descriptor 55
EDMA_BASE + 0x1700 EDMA_TCD56—eDMA transfer control descriptor 56
EDMA_BASE + 0x1720 EDMA_TCD57—eDMA transfer control descriptor 57
EDMA_BASE + 0x1740 EDMA_TCD58—eDMA transfer control descriptor 58
EDMA_BASE + 0x1760 EDMA_TCD59—eDMA transfer control descriptor 59
EDMA_BASE + 0x1780 EDMA_TCD60—eDMA transfer control descriptor 60
EDMA_BASE + 0x17A0 EDMA_TCD61—eDMA transfer control descriptor 61
EDMA_BASE + 0x17C0 EDMA_TCD62—eDMA transfer control descriptor 62
EDMA_BASE + 0x17E0 EDMA_TCD63—eDMA transfer control descriptor 63
Address
0xFFF4_4000
0xFFF4_4004
0xFFF4_4008
0xFFF4_400C
0xFFF4_4010
0xFFF4_4014
0xFFF4_4018 eDMA Set Enable
(EDMA_SERQR)
144
Table 8-1. eDMA memory map (continued)
Register
Table 8-2. eDMA 32-bit memory map—graphical view
eDMA Control Register (EDMA_CR)
eDMA Error Status (EDMA_ESR)
eDMA enable request high register (EDMA_ERQRH)
eDMA Enable Request
(EDMA_ERQRL, channels 31–16)
eDMA Enable Error Interrupt High
(EDMA_EEIRH, channels 63–48)
eDMA Enable Error Interrupt Low
(EDMA_EEIRL, channels 31–16)
eDMA Clear Enable
Request Request
(EDMA_CERQR)
MPC5644A Microcontroller Reference Manual, Rev. 6
Register
eDMA Enable Request
(EDMA_ERQRL, channels 15–00)
eDMA Enable Error Interrupt High
(EDMA_EEIRH, Channels 47–32)
eDMA Enable Error Interrupt Low
(EDMA_EEIRL, Channels 15–00)
eDMA Set Enable
Error Interrupt
(EDMA_SEEIR)
Location Size
on page 8-165 256
on page 8-165 256
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eDMA Clear Enable
Error Interrupt
(EDMA_CEEIR)
Freescale Semiconductor