Engine Related Registers - NXP Semiconductors MPC5644A Reference Manual

Enhanced Time Processing Unit (eTPU2)
24.4.4

Engine related registers

This section gathers registers that are engine-related, other than ETPU_ECR (see
ETPU_ECR – eTPU Engine Configuration
24.4.4.1 ETPU_WDTR – eTPU Watchdog Timer Register
This register configures the watchdog timer for the engine.
Offset: eTPU_A: eTPU_Base + 0x060; eTPU_B: eTPU_Base + 0x070
0 1
R WDM
W
Reset 0 0
16 17
R
W
Reset 0 0
= Unimplemented or Reserved
Field
0-1 WDM—Watchdog Mode
WDM selects the Watchdog operation mode, as shown below. For more information on the Watchdog
operation, see
00: disabled
01: reserved
10: thread length
11: busy length
Note: The watchdog must be disabled first before a new mode is configured.
2-15 Reserved
16-31 WDCNT[15:0]—Watchdog Count
This field indicates the maximum number of microcyles allowed for a thread (in thread length mode) or a
sequence of threads (in busy length mode) before the current running thread is forced to end. For more
information on Watchdog operation, see
Note: The TST microcycles are also counted by the watchdog.
790
Register).
2 3 4 5 6
0 0 0 0 0
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
Figure 24-10. ETPU_WDTR Register
Table 24-21. ETPU_WDTR field description
Section 24.5.1.4, Watchdog.
Section 24.5.1.4,
MPC5644A Microcontroller Reference Manual, Rev. 6
7 8 9 10
0 0 0 0
0 0 0 0
23 24 25 26
WDCNT[15:0]
0 0 0 0
Description
Watchdog.
Section 24.4.2.5,
Access: User read/write
11 12 13 14 15
0 0 0 0 0
0 0 0 0 0
27 28 29 30 31
0 0 0 0 0
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