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System Integration Unit (SIU)
Field
28:29
System Clock Divide
SYSCLKDIV
The SYSCLKDIV bits select the divider value for the system clock (ipg_clk). Note that the
SYSCLKDIV divider is required in addition to the RFD to allow the other sources for the system clock
(16 MHz IRC and OSC) to be divided down to slowest frequencies to improve power. The output of
the clock divider is nominally a 50% duty cycle.
00 Divide by 2
01 Divide by 4
10 Divide by 8
11 Divide by 16
Note: The above four divider values can be selected only if SIU_SYSDIV[BYPASS] value = 0. If
SIU_SYSDIV[BYPASS] = 1, the system clock divider is bypassed and "divide by 1" is selected.
30:31
Reserved
16.6.32 Halt Register (SIU_HLT)
The SIU_HLT register is used to put various modules into stop mode to save power. Each bit will drive a
separate stop request signal to a different module. When the module acknowledges the stop request, the
clock to that module is halted. In order to remove the module from stop mode, the corresponding bit in the
SIU_HLT register must be cleared. In the case of the CPU, stop mode in entered when the corresponding
bit in SIU_HLT is set and a WAIT instruction is executed. The CPU exits stop mode upon reception of any
interrupt request.
SIU_BASE + 0x9A4
0
1
R
0
W
Reset
0
0
16
17
R
0
W
Reset
0
0
= Unimplemented or Reserved
546
Table 16-217. SIU_SYSDIV field description (continued)
2
3
4
5
6
0
0
0
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Figure 16-217. Halt Register (SIU_HLT)
MPC5644A Microcontroller Reference Manual, Rev. 6
Description
7
8
9
10
11
0
0
0
0
0
23
24
25
26
27
0
0
0
0
0
0
0
0
0
0
12
13
14
15
0
0
0
0
0
0
0
28
29
30
31
0
0
0
0
0
Freescale Semiconductor
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