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Enhanced Time Processing Unit (eTPU2)
•
Number of parameter RAM accesses during execution of a Function thread
•
System clock frequency.
Each time slot may require a different number of microcycles, depending on the thread of a Function to be
executed. This variation is shown in
For more details on latency evaluation, see
Microcycles
Time Slot
Fixed Priority Level
24.5.4
Parameter sharing and coherency
SPRAM can be concurrently accessed by Host and Microengines (two in a dual eTPU engine system). In
general, there is no guaranteed order by which a group of parameters is accessed, which may lead to a lack
of internal consistency if two or more related parameters are read when only part of them is updated.
eTPU provides mechanisms to guarantee parameter coherency. The most generic mechanisms for
Host-eTPU coherency, suitable for any number of parameters, are:
•
the use of Transfer Service Thread mechanism.
•
the mailbox (or "software semaphore") mechanism.
These mechanisms, described in
transfer parameters from temporary buffers in SPRAM to their definitive locations (or vice-versa). These
methods have the disadvantage of wasting processing and code memory resources.
eTPU also provides a Coherent Dual-parameter Controller (CDC) mechanism. It is used by Host to
coherently transfer pairs of parameters from/to a parameter buffer located on SPRAM to/from the
locations on SPRAM where parameters are accessed directly by the channels. Coherency is guaranteed by
SPRAM access arbitration. Although limited to two parameters only, it has lower latency and wastes no
1
microengine resources
. CDC usage is described in
(CDC).
For parameters shared by both engines, eTPU provides Hardware Semaphores. Coherency is assured
given the semaphores are used to prevent concurrent access to the changing parameters. Microengine can
request semaphores using specific microinstructions (see
Hardware Semaphores are described in detail in
Neither Host nor CDC have access to the hardware semaphores, but they can be combined with microcode
transfer mechanisms if Host must coherently access parameters which are also shared by both engines.
1. A microengine access to the SPRAM in the moment CDC is performing the transfer may suffer a maximum of two wait-states.
836
Figure
24-34.
Section 24.6.5, Estimating worst-case
1
2
H
M
Figure 24-34. Time-slot variation
Section 24.6.3, Multiple parameter coherency
Section 24.5.4.3, Coherent Dual-parameter Controller
Section 24.5.4.4, Hardware
MPC5644A Microcontroller Reference Manual, Rev. 6
3
4
5
6
H
L
H
M
methods, use microcode to
Section 24.5.9.1.7, Semaphore
Semaphores.
latency.
operations).
Freescale Semiconductor
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