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Although INTC_SSCIn is 8 bits wide, it can be accessed with a single 16-bit or 32-bit access, provided
that the access does not cross a 32-bit boundary.
Address: Base + 0x0020 + n (INTC_SSCIRn); n = 0–7
0
1
R
0
0
W
RESET:
0
0
16
17
R
0
0
W
RESET:
0
0
= Unimplemented or Reserved
Figure 15-12. INTC Software Set/Clear Interrupt Register (INTC_SSCIRn)
Field
0–5
Reserved, must be cleared.
6
Set flag bits. Writing a 1 sets the corresponding CLRn bit. Writing a 0 has no effect. Each SETn is always
SETn
read as a 0.
7
Clear flag bits. CLRn is the flag bit. Writing a 1 to CLRn clears it provided that a 1 is not written
CLRn
simultaneously to its corresponding SETn bit. Writing a 0 to CLRn has no effect.
0 Interrupt request not pending within INTC.
1 Interrupt request pending within INTC.
15.4.1.6
INTC Priority Select Registers (INTC_PSR0–485)
The INTC_PSRn allows you to select a priority for each interrupt request source (peripheral IRQs or
software configurable IRQs). Each priority select register (INTC_PSRn) is assigned to the IRQ source
vector with the same number. For example, the software configurable IRQs 0–7 are assigned vectors 0–7,
and their priorities are configured in INTC_PSR0–INTC_PSR7, respectively. The peripheral interrupt
requests are assigned vectors 8–485 and their priorities are configured in priority select registers
INTC_PSR8 through INTC_PSR485, respectively.
Although INTC_PSRn is 8-bits wide, you can use a single 16-bit or 32-bit access, provided that it does not
cross a 32-bit boundary.
Do not modify the PRI
Freescale Semiconductor
2
3
4
5
6
0
0
0
0
0
SET0
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
SET2
0
0
0
0
0
Table 15-6. INTC_SSCIRn Field Descriptions
NOTE
field in INTC_PSR
n
MPC5644A Microcontroller Reference Manual, Rev. 6
7
8
9
10
11
CLR0
0
0
0
0
0
0
0
0
0
23
24
25
26
27
CLR2
0
0
0
0
0
0
0
0
0
Description
when the IRQ is asserted.
n
Interrupt Controller (INTC)
Access: R/W
12
13
14
15
0
0
0
CLR1
SET1
0
0
0
0
28
29
30
31
0
0
0
CLR3
SET3
0
0
0
0
353
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