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TCR1
TCR2
TBSA[0]
Microengine
ER1 Bus
ucode ERWA & CMW=1
Comparator
TBSA[2]
0: >=
1: ==
ucode MRLE
Rst
Set
MRLEA
Rst
Set
ucode
MRLA
MRLA
to branch
MRLA
ucode
TCCEA
MTD
Rst
Set
TDLA
ucode TDL
to branch
TDLA
ucode IPACA
Trans.A
IPACA
to service request
Match A
SRI
Flag0
Set
Channel
Flag1
ucode
Flags
MTD
ucode FLC
= Channel 0 only
Output Buffer Enable
Freescale Semiconductor
TBSA[1]
CaptureA
ucode ERWA
& CMW=0
MatchA
UDCM
Action Logic 1
Match
Recognition
Transition
Event
Logic
to branch
PSTI
ODIS
Rst
Output
OPOL
Logic
ucode
ucode TBSA[2:0]
PSC, PSCS
Set
OBE
Output FF
FF
Output Signal
ipp_obe_etpuch
channel output
Figure 24-36. Channel Logic Block Diagram
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Time Processing Unit (eTPU2)
TBSB[1]
Capture 2
ucode PDCM
MatchB
PDCM
mode
decoding
MEF
Action Logic 2
control
Match
Recognition
Transition
Event
Logic
ucode
OPACA
OPACA
ucode
OPACB
OPACB
Rst
ETPU_TBCR[CDCF]
ETPU_ECR[FPSCK]
to branch
PSTO
Input Signal
channel input
TBSB[0]
Microengine
ER2 Bus
ucode ERWB
Comparator
0: >=
TBSB[2]
1: ==
ucode MRLE
Rst
Set
MRLEB
Set
Rst
MRLB
ucode
to branch
MRLB
Set
Rst
TDLB
to branch
TDLB
ucode IPACB
IPACB
to service request
SRI
AM
AM
EDF
TCRCLK
(Filter)
Filter
Synchr.
Synchr.
Input Signal
TCRCLK
MRLB
ucode
TDL
Trans.B
Match B
843
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