NXP Semiconductors MPC5644A Reference Manual page 662

Configurable Enhanced Modular IO Subsystem (eMIOS200)
Figure 22-13 shows both the Unified Channel Control and Datapath block diagram. The control block is
responsible for the generation of signals to control the multiplexes in the Datapath sub-block. Each mode
is implemented by a dedicated logic independent from others modes, thus allowing to optimize the logic
by disabling the mode and therefore its associated logic. The unused gates are removed during the
synthesis phase. Targeting the logic optimization, a set of registers is shared by the modes thus providing
sequential events to be stored.
The Datapath block provides the channel A and B registers, the internal time base and comparators.
Multiplexors select the input of comparators and data for the registers inputs, thus configuring the datapath
in order to implement the channel modes. The outputs of A and B comparators are connected to the control
block.
input
global counter bus
[A]
local counter bus
[B/C/D]
BSL[0]
Datapath
Figure 22-13. Unified Channel Control and Datapath block diagrams
662
input
filter
MODE
register
MODE
decoder
Control Block
BSL[1]+logic
internal counter
CNT
BSL[1]+logic
BSL[1]+logic
MPC5644A Microcontroller Reference Manual, Rev. 6
mode 0 mode 1
logic logic
A Comparator
A2
A1
B1
B2
B Comparator
mode n
logic
General
Purpose
Registers
==
==
Freescale Semiconductor