NXP Semiconductors MC9S12ZVH128 Manuals

Manuals and User Guides for NXP Semiconductors MC9S12ZVH128. We have 1 NXP Semiconductors MC9S12ZVH128 manual available for free PDF download: Reference Manual

NXP Semiconductors MC9S12ZVH128 Reference Manual

NXP Semiconductors MC9S12ZVH128 Reference Manual (878 pages)

MC9S12ZVH-Family S12 MagniV Microcontrollers

Brand: NXP Semiconductors | Category: Controller | Size: 7 MB

Table of Contents

Device Overview Mc9S12Zvh-Family

3
- Table of Contents
  3
- Introduction
  19
  - Features
    20
- Maskset 0N65E and 1N65E Device Compare
  21
- Maskset 2N65E and 1N65E/0N65E Device Compare
  22
- Module Features
  23
- Package and Pinouts
  45
  - Modes of Operation
    55
  - Debugging Modes
    56
- Security
  57
- COP Configuration
  63
- ADC0 Internal Channels
  64
- ADC Result Reference
  65
- LCD Clock Source Connectivity
  66
- Introduction
  67
- Chapter 1
  
  21
- Chapter 10
  
  36
  - Detailed Signal Descriptions
    36
  - VSENSE - Voltage Sensor Input
    43
  - Bctlc
    44
- Chapter 23
  
  68
  - Features
    68
  - External Signal Description
    69
  - Memory Map and Register Definition
    78
- Chapter 2
  
  79
  - Register Map
    79
    
    Register Descriptions
    86
    
    Functional Description
    103
  - Interrupts
    107
  - Pin Interrupts and Wakeup
    108
  - Initialization and Application Information
    109
  - Introduction
    111
- Chapter 5
  
  112
  - Glossary
    112
  - Block Diagram
    113
    
    Register Descriptions
    114
    
    Functional Description
    119
- Chapter 3
  
  121
  - Illegal Accesses
    121
  - Uncorrectable ECC Faults
    122
  - Introduction
    123
- Chapter 4
  
  124
  - Glossary
    124
    
    Modes of Operation
    125
    
    External Signal Description
    126
    
    Register Descriptions
    127
    
    Functional Description
    131
  - S12Z Exception Requests
    132
  - Priority Decoder
    133
  - Interrupt Vector Table Layout
    134
  - Wake up from Stop or Wait Mode
    135
    
    Introduction
    137
    
    S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor
    138
    
    Block Diagram
    140
    
    External Signal Description
    141
    
    Register Descriptions
    142
    
    Functional Description
    146
  - Clock Source
    147
Table of Contents

150
- Dump_Mem.sz_Ws
  154
- Non-Intrusive no (0X33+4 X Sz)/D/Ss/Rd.sz
  154
- Fill_Mem.sz
  155
- Non-Intrusive no (0X13+4 X Sz)/Wd.sz/D/Ss
  155
- Active Yes Background
  157
- Go_Until
  157
- Read_Rn
  157
- Non-Intrusive no
  158
- Non-Intrusive Yes
  158
- Read_Mem.sz
  158
- Read_Mem.sz_Ws
  158
- Non-Intrusive Yes
  159
  - BDC Access of Internal Resources
    163
  - BDC Serial Interface
    166
  - Serial Interface Hardware Handshake (ACK Pulse) Protocol
    169
  - Hardware Handshake Abort Procedure
    171
  - Hardware Handshake Disabled (ACK Pulse Disabled)
    172
  - Single Stepping
    173
  - Serial Communication Timeout
    174
  - Introduction
    175
  - Overview
    176
  - Modes of Operation
    177
  - External Signal Description
    178
  - Register Descriptions
    181
  - Functional Description
    202
  - Signal Description
    233
  - BCTL— Base Control Pin for External PNP
    234
  - TEMPSENSE — Internal Temperature Sensor Output Voltage
    235
  - Memory Map and Registers
    236
  - Register Descriptions
    238
  - Functional Description
    276
  - Startup from Reset
    278
  - Stop Mode Using PLLCLK as Source of the Bus Clock
    279
  - External Oscillator
    281
  - System Clock Configurations
    282
  - Resets
    283
  - Description of Reset Operation
    284
  - PLL Clock Monitor Reset
    285
  - Power-On Reset (POR)
    286
  - Interrupts
    287
  - Initialization/Application Information
    289
  - Introduction
    291
  - S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor
    292
  - External Signal Description
    295
  - Register Descriptions
    296
  - Functional Description
    312
- Chapter 6
  
  206
  - Read_Dbgtb
    159
  - Events
    206
  - State Sequence Control
    208
  - Trace Buffer Operation
    209
  - Code Profiling
    218
  - Breakpoints
    222
  - Application Information
    223
  - Breakpoints from Other S12Z Sources
    224
    
    Introduction
    225
    
    Features
    226
    
    Modes of Operation
    228
- Chapter 7
  
  231
  - S12CPMU_UHV_V6 Block Diagram
    231
- Chapter 8
  
  314
  - Prescaler
    314
  - Pulse Accumulator
    315
  - Event Counter Mode
    316
  - Channel [7:0] Interrupt (C[7:0]F)
    317
    
    Introduction
    319
    
    Block Diagram
    320
    
    PWM7 - PWM0 — PWM Channel 7 - 0
    321
  - Functional Description
    336
- Chapter 9
  
  339
  - PWM Channel Timers
    339
  - Resets
    347
    
    Interrupts
    348
    
    Introduction
    349
  - Key Features
    351
- Chapter 18
  
  352
  - Modes of Operation
    352
    
    Block Diagram
    355
    
    Signal Description
    356
10.4 Memory Map and Register Definition

357
- Memory Map and Register Definition
  357
- Address Name Bit
  358
- Radc_En
  360
  - Register Descriptions
    360
- Csl_Bmod Rvl_Bmod Smod_Acc Aut_Rsta
  362
- DBECC_ERR Reserved
  363
- Rvl_Sel
  363
- Cmd_Eie
  370
- Eol_Eie
  370
- Seqad_Ie Conif_Oie
  371
- Cmd_Eif
  372
- Eol_Eif
  372
- Ldok_Eif
  373
- Eol_Ie
  375
- Eol_If
  376
  - Functional Description
    392
  - Digital Sub-Block
    393
  - Resets
    406
  - ADC Error and Conversion Flow Control Issue Interrupt
    407
  - Use Cases and Application Information
    408
  - List Usage — CSL Double Buffer Mode and RVL Double Buffer Mode
    409
  - List Usage — CSL Double Buffer Mode and RVL Double Buffer Mode
    410
  - Conversion Flow Control Application Information
    412
  - Continuous Conversion
    414
  - Triggered Conversion — Single CSL
    415
  - Fully Timing Controlled Conversion
    416
  - Introduction
    417
  - Glossary
    418
  - Features
    419
  - External Signal Description
    420
  - S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor
    421
  - Register Descriptions
    423
  - Programmer's Model of Message Storage
    442
  - Functional Description
    453
  - Identifier Acceptance Filter
    456
  - Modes of Operation
    462
  - Low-Power Options
    464
  - Reset Initialization
    468
  - Initialization/Application Information
    470
  - Introduction
    471
  - Block Diagram
    472
  - External Signal Description
    473
  - SS — Slave Select Pin
    474
  - Register Descriptions
    475
  - Functional Description
    483
- Chapter 12
  
  484
  - Master Mode
    484
  - Slave Mode
    485
  - Transmission Formats
    486
  - SPI Baud Rate Generation
    491
  - Special Features
    492
  - Error Conditions
    493
  - Low Power Mode Options
    494
    
    Introduction
    497
    
    Modes of Operation
    499
    
    External Signal Description
    500
    
    Functional Description
    512
- Chapter 13 Operation in Run Mode
  
  517
  - Application Information
    518
    
    Introduction
    525
    
    Features
    526
    
    External Signal Description
    528
    
    Register Descriptions
    530
    
    Functional Description
    537
    
    Operation in Wait Mode
    539
    
    LCD Waveform Examples
    540
    
    LCD Clock Inputs & Reset Behavior
    546
  - Resets
    547
    
    Introduction
    549
    
    S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor
    550
    
    Modes of Operation
    551
    
    External Signal Description
    552
    
    Register Descriptions
    553
    
    Functional Description
    566
- Chapter 15
  
  567
  - Infrared Interface Submodule
    567
  - Data Format
    568
  - Baud Rate Generation
    569
  - Transmitter
    570
  - Receiver
    575
  - Single-Wire Operation
    583
  - Loop Operation
    584
  - Modes of Operation
    585
  - Recovery from Wait Mode
    588
  - Introduction
    589
  - Block Diagram
    591
    
    External Signal Description
    592
    
    M3C0M/M3C0P/M3C1M/M3C1P — PWM Output Pins for Motor 3
    593
    
    Register Descriptions
    595
    
    Functional Description
    601
  - PWM Duty Cycle
    613
  - Output Switching Delay
    614
- Chapter 14
  
  615
  - Operation in Wait Mode
    615
    
    Initialization/Application Information
    616
    
    Introduction
    621
    
    Block Diagram
    622
    
    External Signal Description
    623
    
    Memory Map and Register Definition
    624
    
    Functional Description
    631
- Chapter 17
  
  632
  - Return to Zero Modes
    632
  - Operation in Low Power Modes
    636
    
    Introduction
    639
    
    Block Diagram
    640
    
    External Signal Description
    641
  - Oscclk_32K
    642
  - RTC Control Register 1(RTCCTL1)
    643
  - RTC Control Register 2 (RTCCTL2)
    644
  - RTC Control Register 4 (RTCCTL4)
    645
  - RTC Status Register 1 (RTCS1)
    646
  - RTC Compensation Configure Register (RTCCCR)
    647
  - RTC Counter Register (RTCCNT)
    648
  - RTC Modulo Register (RTCMOD)
    649
  - RTC Minute Register (RTCMINR)
    650
  - Functional Description
    651
  - RTC Clock Compensation
    652
  - Calendar Register and Bit Write Protection
    653
  - Load Buffer Register
    654
  - RTC Compensation
    655
    
    Introduction
    657
    
    External Signal Description
    658
    
    Memory Map and Register Definition
    659
    
    Functional Description
    670
- Chapter 19
  
  671
  - SSG Tone Generation
    671
  - SSG Start and Stop
    674
  - Register Reload
    675
  - SSG Output Control
    676
  - Introduction
    677
    
    Register Descriptions
    679
    
    Functional Description
    683
    
    Aligned 2 and 4 Byte Memory Write Access
    684
    
    Memory Read Access
    685
    
    ECC Algorithm
    686
- Chapter 21
  
  689
  - Introduction
    690
- Chapter 22
  
  691
  - Features
    691
  - External Signal Description
    692
    
    Memory Map and Registers
    693
    
    Register Descriptions
    697
    
    Functional Description
    717
    
    Internal NVM Resource
    718
    
    Allowed Simultaneous P-Flash and EEPROM Operations
    723
    
    Flash Command Description
    724
    
    Interrupts
    740
    
    Stop Mode
    741
    
    Unsecuring the MCU in Special Single Chip Mode Using BDM
    742
    
    Introduction
    743
    
    S12ZVH Family Reference Manual, Rev. 1.05 Freescale Semiconductor
    744
    
    External Signal Description
    745
    
    CANH — CAN Bus High Pin
    746
    
    Memory Map and Register Definition
    747
    
    Register Descriptions
    748
    
    Functional Description
    755
    
    Interrupts
    757
    
    Initialization/Application Information
    758
    
    Wake-Up Mechanism
    759
    
    Introduction
    761
    
    Block Diagram
    762
    
    VSUP — Voltage Supply Pin
    763
    
    Register Descriptions
    764
  - Functional Description
    769
  - Interrupts
    770
  - A.1 General
    773
    
    A.1.1 Pins
    774
    
    A.1.2 Current Injection
    775
    
    A.1.3 Absolute Maximum Ratings
    776
    
    A.1.4 ESD Protection and Latch-Up Immunity
    777
    
    A.1.5 Operating Conditions
    778
    
    A.1.6 Power Dissipation and Thermal Characteristics
    779
    
    A.1.7 I/O Characteristics
    782
    
    A.1.8 Supply Currents
    784
    
    A.1.9 ADC Conversion Result Reference
    786
- Appendix A
  
  773
  - B.1 ADC Operating Characteristics
    787
    
    B.1.2 ADC Accuracy
    789
  - C.1 Reset, Oscillator and PLL
    793
- Appendix D
  
  795
- Appendix B Appendix D
  
  796
- Appendix E
  
  797
  - E.1 LCD Driver
    797
  - F.1 MSCAN Electrical Characteristics
    799
- Appendix F
  
  801
- Appendix G
  
  801
  - G.1 NVM Timing Parameters
    801
  - G.2 NVM Reliability Parameters
    802
  - G.3 NVM Factory Shipping Condition
    803
- Appendix H
  
  805

Advertisement

Advertisement

Related Products

NXP Semiconductors Categories

Motherboard Microcontrollers Computer Hardware Control Unit Controller

More NXP Semiconductors Manuals