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The TCD status bits execute the following sequence for a software activated channel:
1. EDMA_TCD[START] = 1, EDMA_TCD[ACTIVE] = 0, EDMA_TCD[DONE] = 0 (channel
service request via software).
2. EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 1, EDMA_TCD[DONE] = 0 (channel is
executing).
3. EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 0, EDMA_TCD[DONE] = 0 (channel has
completed the minor loop and is idle), or
4. EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 0, EDMA_TCD[DONE] = 1 (channel has
completed the major loop and is idle).
The best method to test for minor loop completion when using hardware initiated service requests is to
read field EDMA_TCD[CITER] and test for a change. The hardware request and acknowledge handshakes
signals are not visible in the programmer's model.
The TCD status bits execute the following sequence for a hardware activated channel:
1. eDMA peripheral request asserts (channel service request via hardware).
2. EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 1, EDMA_TCD[DONE] = 0 (channel is
executing).
3. EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 0, EDMA_TCD[DONE] = 0 (channel has
completed the minor loop and is idle), or
4. EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 0, EDMA_TCD[DONE] = 1 (channel has
completed the major loop and is idle).
For both activation types, the major loop complete status is explicitly indicated via bit
EDMA_TCD[DONE].
Bit EDMA_TCD[START] is cleared automatically when the channel begins execution, regardless of how
the channel was activated.
8.5.6.2
Active channel TCD reads
The eDMA will read back the true EDMA_TCD[SADDR], EDMA_TCD[DADDR], and
EDMA_TCD[NBYTES] values if read while a channel is executing. The true values of the SADDR,
DADDR, and NBYTES are the values the eDMA engine is currently using in its internal register file and
not the values in the TCD local memory for that channel. The addresses (SADDR and DADDR) and
NBYTES (decrements to zero as the transfer progresses) can give an indication of the progress of the
transfer. All other values are read back from the TCD local memory.
8.5.6.3
Pre-emption status
Pre-emption is available only when fixed arbitration is selected for both group- and channel-arbitration
modes. A pre-emptable situation is one in which a pre-empt-enabled channel is running and a higher
priority request becomes active. When the eDMA engine is not operating in fixed group, fixed-channel
arbitration mode, the determination of the relative priority of the actively running and the outstanding
requests become undefined. Channel and group priorities are treated as equal (or more exactly, constantly
rotating) when round-robin arbitration mode is selected.
Freescale Semiconductor
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Direct Memory Access Controller (eDMA)
187
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