NXP Semiconductors MPC5644A Reference Manual page 987

Channel
0
1
2
8
15
1
0% RAM collision rate
2
CPU clock rate = 40 MHz, or 60 ns per clock period
To find the WCL for channel 0, assume channel 0 has just finished service. Map the channels in the
H-M-H-L-H-M-H sequence. See
= 10-CYCLE TIME SLOT TRANSITION
= 4-CYCLE NOP INSTRUCTION
Figure 24-73. Worst-case latency for channel 0 (second try)
Conclusion: with this system configuration, the WCL of both channel 0 and channel 1 is 3.85 ms, which
is within the limit of 4 ms needed for a 50-kHz PWM.
Next, find the WCL for channel 2. Assume channel 2 has just finished service. Map the channels in the
H-M-H-L-H-M-H sequence. See
= 10-CYCLE TIME SLOT TRANSITION
= 4-CYCLE NOP INSTRUCTION
Conclusion: with this system configuration, the WCL for channels 2 and 8 is 4.7 ms, which is within the
40 and 80 ms WCL requirements.
Freescale Semiconductor
Table 24-126. Second-Try system configuration
Priority
High PWM at 50 kHz (needs a 4-µs WCL)
High PWM at 50 kHz (needs a 4-µs WCL)
Middle PWM at 5 kHz (needs a 40-µs WCL)
Middle PPWA at 5 kHz (needs an 80-µs WCL)
Low
Figure 24-73.
WORST CASE LATENCY
H M H L H
CHANNEL 0 CHANNEL 1 CHANNEL 0
SERVICED SERVICED SERVICED
CHANNEL 2 CHANNEL 15
OR CHANNEL SERVICED
SERVICED
Figure 24-74.
WORST CASE LATENCY
H M H L H M
CHANNEL 2 CHANNEL 15 CHANNEL 8
SERVICED SERVICED SERVICED
CHANNEL 0 CHANNEL 1
SERVICED SERVICED
Figure 24-74. Worst-case latency for channel 2
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Time Processing Unit (eTPU2)
,
1 2
Function
DIO as input at rate of 1 ms
M H H M H L
H H M H L
CHANNEL 2
SERVICED
TPU CH0 WCL TIM 2
TPU CH0 WCL TIM 2
TPU CH2 WCL TIM 1 TPU CH2 WCL TIM 1
987