Page 1 MPC5644A Microcontroller Reference Manual Devices Supported: MPC5644A MPC5643A MPC5644ARM Rev. 6 16 Jan 2012 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 2 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 3: Table Of Contents
1.1 The MPC5644A Microcontroller Family ........27 1.2 MPC5644A and MPC5642A Device Comparison ......28 1.3 Device block diagram .
Page 4 6.3.3 Flash bus interface unit ......... . . 120 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 5 8.5.7 Channel linking ..........188 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 6 11.8.2 Reset effects on SRAM accesses ........215 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 7 14.1 Information Specific to This Device ........275 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 8 15.6.5 Priority ceiling protocol ......... . . 376 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 9 16.6.28Compare A Low Register (SIU_CARL) ......543 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 10 18.4.4 ECC registers ..........587 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 11 21.5.6 Booting from the External Bus Interface (EBI) ......637 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 12 23.3.12REACM Threshold Bank Register (REACM_THBK) ....711 23.3.13REACM ADC result maximum limit check register (REACM_ADCMAX) ..712 23.3.14REACM Modulation Range Pulse Width Register (REACM_RANGEPWD) . . 712 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 13 24.5 Functional description ..........810 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 14 25.6 Functional Description ..........1071 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 15 26.5.4 Output buffer description ........1204 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 16 29.3 Calculating a CRC checksum ......... . .1238 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 17 30.9.10Interrupts/DMA requests ........1318 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 18 32.1 Information specific to this device ........1389 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 19 33.4.2 PLL clocking ..........1448 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 20 34.2.1 Overview ........... . . 1626 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 21 36.3 External signal description ..........1660 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 22 38.3.1 DTS register access ..........1695 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 23 38.6 Example application ..........1699 Appendix A Revision history MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 24 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 25 Preface Overview The primary objective of this document is to define the functionality of the MPC5644A family of microcontrollers for use by software and hardware developers. The MPC5644A family is built on Power ® Architecture technology and integrates technologies that are important for today’s lower-end applications.
Page 26 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 27: The Mpc5644A Microcontroller Family
The MPC5644A has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by up to 192 KB on-chip SRAM and up to 4 MB of internal flash memory. The MPC5644A includes an external bus interface and a “calibration bus” that is only accessible when using the Freescale Vertical Calibration calibration tools.
Page 28: Mpc5644A And Mpc5642A Device Comparison
Introduction MPC5644A and MPC5642A Device Comparison Table 1-1 summarizes the features MPC5644A and MPC5642A microcontrollers. Table 1-1. MPC5644A and MPC5642A comparison Feature MPC5644A MPC5642A Process 90 nm Core e200z4 e200z4 SIMD Cache 8 KB instruction Non-Maskable Interrupt (NMI) NMI & Critical Interrupt...
Page 29 Introduction Table 1-1. MPC5644A and MPC5642A comparison (continued) Feature MPC5644A MPC5642A Micro Second Channel (MSC) bus downlink DSPI_A DSPI_B Yes (with LVDS) DSPI_C Yes (with LVDS) DSPI_D FlexRay System timers 5 PIT channels 4 STM channels 1 Software Watchdog eMIOS 24 ch.
Page 30: Device Block Diagram
Ballmap upwardly compatible with the standardized package ballmap used for various Freescale MPC5xxx family members, including MPC5554, MPC5567 and MPC5666. For Freescale VertiCal Calibration System only. Device block diagram Figure 1-1 shows a top-level block diagram of the MPC5644A. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 31 – Second gen. Enhanced Time Processing Unit – Variable Length (instruction) Encoding FlexCAN– Controller Area Network (FlexCAN) XOSC – XTAL Oscillator FMPLL – Frequency-Modulated Phase Locked Loop Figure 1-1. MPC5644A Block Diagram MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 32: Feature Summary
• 2 enhanced queued analog-to-digital converters (eQADCs) — Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers — 6 command queues — Trigger and DMA support MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 33: Feature Details
— 324 TEPBGA — 496-pin CSP (calibration tool only) 1.4.1 Feature details 1.4.2 e200z4 core MPC5644A devices have a high performance e200z448n3 core processor: • Dual issue, 32-bit Power Architecture embedded category CPU • Variable Length Encoding Enhancements • 8 KB instruction cache: 2- or 4- way set associative instruction cache •...
Page 34: Crossbar Switch (Xbar)
64 programmable channels, with minimal intervention from the host processor. The hardware micro-architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 35: Interrupt Controller
• Each interrupt source can assigned a specific priority by software • Preemptive prioritized interrupt requests to processor • ISR at a higher priority preempts executing ISRs or tasks at lower priorities MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 36: Memory Protection Unit (Mpu)
— 64-bit error registers, one for each XBAR slave port, capture the last faulting address, attributes, and detail information 1. EBI not available on all packages and is not available, as a master, for customer. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 37: Fmpll
Self-clocked mode (SCM) operation 1.4.8 The MPC5644A SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins.
Page 38: Flash Memory
1.4.9 Flash memory The MPC5644A provides up to 4 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used to store instructions or data, or both. The flash module includes a Fetch Accelerator that optimizes the performance of the flash array to match the CPU architecture. The flash module interfaces the system bus to a dedicated flash memory array controller.
Page 39 The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by Freescale and is identical for all MPC5644A MCUs. The BAM program is executed every time the MCU is powered-on or reset in normal mode. The BAM supports different modes of booting. They are: •...
Page 40: Emios
RAM. High-level assembler/compiler and documentation allows customers to develop their own functions on the eTPU2. MPC5644A devices feature the second generation of the eTPU, called eTPU2. Enhancements of the eTPU2 over the standard eTPU include: •...
Page 41 Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands. • Resource sharing features support channel use of common channel registers, memory and microengine time: MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 42: Reaction Module
The six command queues are prioritized with Queue_0 having the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 43 8 channels can be used as 4 pairs of differential analog input channels • Differential channels include variable gain amplifier for improved dynamic range • Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200 k100 k5 k MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 44: Dspi
DSPI The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the MPC5644A MCU and external devices. The DSPI supports pin count reduction through serialization and deserialization of eTPU and eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like protocol. This SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion, etc.
Page 45: Esci
Introduction Microsecond Bus protocol. There are three identical DSPI blocks on the MPC5644A MCU. The DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) to improve high speed operation. DSPI module features include: • Selectable LVDS pads working at 40 MHZ for SOUT and SCK pins for DSPI_B and DSPI_C •...
Page 46: Flexcan
1.4.17 FlexCAN The MPC5644A MCU includes three controller area network (FlexCAN) blocks. The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth.
Page 47: Flexray
Short latency time due to an arbitration scheme for high-priority messages • Low power mode, with programmable wake-up on bus activity 1.4.18 FlexRay The MPC5644A includes one dual-channel FlexRay module that implements the FlexRay Communications System Protocol Specification, Version 2.1 Rev A. Features include: • Single channel support •...
Page 48: Software Watchdog Timer (Swt)
Support for CRC-32 (Ethernet protocol): — X + X + 1 • Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency 1.AUTOSAR: AUTomotive Open System ARchitecture (see http://www.autosar.org) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 49: Error Correction Status Module (Ecsm)
Peripheral RAM (FlexRay, CAN, eTPU2 Parameter RAM) 1.4.23 External bus interface (EBI) The MPC5644A device features an external bus interface that is available in 324 TEPBGA and calibration packages. The EBI supports operation at frequencies of system clock /1, /2 and /4, with a maximum frequency support of 80 MHz.
Page 50: Power Management Controller (Pmc)
The NPC (Nexus Port Controller) block provides real-time Nexus Class3+ development support capabilities for the MPC5644A Power Architecture-based MCU in compliance with the IEEE-ISTO 5001-2003 and 2010 standards. MDO port widths of 4 pins and 12 pins are available in all packages.
Page 51: Development Trigger Semaphore (Dts)
1.4.28 Development Trigger Semaphore (DTS) MPC5644A devices include a system development feature, the Development Trigger Semaphore (DTS) module, that enables software to signal an external tool by driving a persistent (affected only by reset or an external tool) signal on an external device pin. There is a variety of ways this module can be used, including as a component of an external real-time data acquisition system.
Page 52 Introduction MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 53: Introduction
Memory Map Introduction Table 2-1 shows the memory map for the MPC5644A. All addresses on the MPC5644A, including those that are reserved, are identified in the table. The addresses represent the physical addresses assigned to each IP block. Memory map Table 2-1.
Page 54 Memory Map Table 2-1. MPC5644A memory map (continued) Start Address End Address Allocated Size Used Size Region Name 0xC3FB_C000 0xC3FB_FFFF 16 KB — 0xC3FC_0000 0xC3FC_3FFF 16 KB — eTPU Registers 0xC3FC_4000 0xC3FC_6FFF — — Reserved 0xC3FC_7000 0xC3FC_77FF 2 KB —...
Page 55 Memory Map Table 2-1. MPC5644A memory map (continued) Start Address End Address Allocated Size Used Size Region Name 0xFFFB_0000 0xFFFB_3FFF 16 KB — eSCI_A 0xFFFB_4000 0xFFFB_7FFF 16 KB — eSCI_B 0xFFFB_8000 0xFFFB_BFFF 16 KB — eSCI_C 0xFFFB_C000 0xFFFB_FFFF 16 KB —...
Page 56 Memory Map MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 57: Chapter 3
Signal Description Chapter 3 Signal Description This chapter describes signals that connect off chip. It includes a table of signal properties and the detailed descriptions of signals. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 58: Signal Properties
Signal Properties Table 1. MPC5644A signal properties Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset GPIO EMIOS14 eMIOS channel VDDEH7 — / Up — / Up — — GPIO[203] GPIO Slow EMIOS15 eMIOS channel VDDEH7 —...
Page 59 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset BOOTCFG[0] Boot Config. Input VDDEH6 BOOTCFG[0] / — / Down — — IRQ[2] External Interrupt Request Slow Down GPIO[211]...
Page 60 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset ADDR14 External address bus VDDE3 — / Up — / Up — — WE[3] Write/byte enables Fast GPIO[10] GPIO...
Page 61 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset ADDR24 External address bus VDDE-EH — / Up — / Up — — DATA24 External data bus Medium GPIO[20]...
Page 62 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset DATA3 External data bus VDDE5 — / Up — / Up — — ADDR19 External address bus Fast GPIO[31]...
Page 63 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset DATA14 External data bus VDDE5 — / Up — / Up — — ADDR30 External address bus Fast GPIO[42]...
Page 64 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset CAL_ADDR[13] Calibration address bus VDDE12 — / — — — — CAL_WE[3]/BE[3] Calibration write/byte enable Fast CAL_ADDR[14] Calibration address bus VDDE12 —...
Page 65 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset CAL_ADDR[28] Calibration address bus VDDE12 — / — — — — CAL_DATA[28] Calibration data bus Fast CAL_ADDR[29] Calibration address bus VDDE12 —...
Page 66 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset CAL_DATA[13] Calibration data bus VDDE12 — / Up — / Up — — — Fast CAL_DATA[14] Calibration data bus VDDE12 —...
Page 67 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset NEXUS EVTI Nexus event in VDDEH7 — / Up EVTI / Up 12,14 MultiV EVTO Nexus event out VDDEH7 —...
Page 68 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset MDO9 Nexus message data out VDDEH7 — — / — 12,14 ETPUA25_O eTPU A channel (output only) MultiV GPIO[80]...
Page 69 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset CAN_A_RX FlexCAN A RX VDDEH6 — / Up — / Up SCI_A_RX eSCI A RX Slow GPIO[84] GPIO CAN_B_TX...
Page 70 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset DSPI DSPI_A_SCK — — — — VDDEH7 — / Up — / Up — — DSPI_C_PCS[1] DSPI C peripheral chip select...
Page 71 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset DSPI_B_SOUT DSPI B data output VDDEH6 — / Up — / Up DSPI_C_PCS[5] DSPI C peripheral chip select Medium...
Page 72 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset Single Ended Analog Input — — VDDA I / — AN[5] / — DAN2- Negative Terminal Diff. Input Analog Single Ended Analog Input —...
Page 73 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset AN18 Single-ended Analog Input — — VDDA I / — AN[18] / — Analog AN19 Single-ended Analog Input —...
Page 74 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset AN34 Single-ended Analog Input — — VDDA I / — AN[34] / — Analog AN35 Single-ended Analog Input —...
Page 75 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset ETPUA3 eTPU A channel VDDEH4 — / WKPCFG GPIO / WKPCFG 58 ETPUA15_O eTPU A channel (output only) Slow...
Page 76 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset ETPUA11 eTPU A channel VDDEH1 — / — / ETPUA23_O eTPU A channel (output only) Slow WKPCFG WKPCFG RCH4_B...
Page 77 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset ETPUA20 eTPU A channel 0001 VDDEH1 — / — / IRQ[8] External interrupt request 0010 Slow WKPCFG WKPCFG RCH0_B...
Page 78 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset ETPUA27 eTPU A channel 0001 VDDEH1 — / — / IRQ[15] External interrupt request 0010 Slow + WKPCFG WKPCFG...
Page 79 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset EMIOS3 eMIOS channel VDDEH4 — / — / AA13 ETPUA3_O eTPU A channel (output only) Slow WKPCFG WKPCFG GPIO[182]...
Page 80 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset EMIOS13 eMIOS channel VDDEH4 — / — / AA16 DSPI_D_SOUT DSPI D data output Medium WKPCFG WKPCFG GPIO[192] GPIO...
Page 81 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset CLKOUT System clock output VDDE5 — CLKOUT — — Fast ENGCLK Engineering clock output VDDE5 — ENGCLK — Fast...
Page 82 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset VDDE12 External supply input for — — 1.8 V - 3.3 V I / — VDDE12 — — —...
Page 83 Table 1. MPC5644A signal properties (continued) Status Package pin # Voltage Name Function Field Type Pad Type After During Reset Reset VDDEH7 I/O Supply Input — — 3.3 V - 5.0 V I / — VDDEH7 — B22, C21, D15, D20,...
Page 84 The P/A/G column indicates the position a signal occupies in the muxing order for a pin—Primary, Alternate 1, Alternate 2, Alternate 3, or GPIO. Signals are selected by setting the PA field value in the appropriate PCR register in the SIU module. The PA field values are as follows: P - 0b0001, A1 - 0b0010, A2 - 0b0100, A3 - 0b1000, or G - 0b0000.
Page 85: Signal Details
Signal Details Table 3-3. Signal details Signal Module or Function Description CLKOUT Clock Generation MPC5644A clock output for the external/calibration bus interface ENGCLK Clock Generation Clock for external ASIC devices EXTAL Clock Generation Input pin for an external crystal oscillator or an external clock source based on the value driven on the PLLREF pin at reset.
Page 86 OE is used to indicate when an external memory is permitted to drive back read data. External memories must have their data output buffers off when OE is negated. OE is only asserted for chip-select accesses. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 87 For write transactions, TA is only asserted once at access completion, even if more than one write data beat is transferred. The Transfer Start signal (TS) is asserted by the MPC5644A to indicate the start of a transfer. WE[2:3] Write enables are used to enable program operations to a particular memory.
Page 88 MDO pins Nexus Nexus Ready Output (RDY) is an output that indicates to the development tools the data is ready to be read from or written to the Nexus read/write access registers. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 89 Module or Function Description BOOTCFG[0:1] SIU - Configuration Two BOOTCFG signals are implemented in MPC5644A MCUs. The BAM program uses the BOOTCFG0 bit to determine where to read the reset configuration word, and whether to initiate a FlexCAN or eSCI boot.
Page 90 MCU for all internal and external reset sources. There is a delay between initiation of the reset and the assertion of the RSTOUT pin. See Section 4.3.2, RSTOUT,” for details. Do not connect pin directly to a power supply or ground. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 91 GPIO204, GPIO206, GPIO207, GPIO219, EVTI, EVTO, MDO4, MDO5, MDO6, MDO7, MDO8, MDO9, MDO10, MDO11, MSEO0, MSEO1, RDY, TCK, TDI, TDO, TMS, JCOMP, DSPI_A_SCK, DSPI_A_SIN, DSPI_A_SOUT, DSPI_A_PCS[0], DSPI_A_PCS[1], DSPI_A_PCS[4], DSPI_A_PCS[5], AN12-SDS, AN13-SDO, AN14-SDI, AN15-FCK MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 92 Other Power Segments VDDREG — VRCCTL — — VDDPLL 1.2 V — VSTBY 0.95–1.2 V — (unregulated mode) 2.0–5.5 V — (regulated mode) — — Do not use VRC33 to drive external circuits. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 93: Reset Sources
Table 4-1. BOOTCFG options BOOTCFG[1 BOOTCFG[0] Meaning Boot from internal flash memory FlexCAN / eSCI boot Boot from external memory (no arbitration) Reserved This mode is only available in packages that have an EBI. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 94: Reset Vector
Depending on the PLL configuration, External Reference or Crystal Mode, the RSTOUT pin is asserted after a delay defined in Table 4-3, plus four cycles for sampling of the configuration pins. 1. BOOTCFG[0] is not available on all packages. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 95: Fmpll Lock Gating Signal
For the following reset source descriptions refer to the reset flow diagrams in Figure 4-1 Figure 4-2. Figure 4-1 shows the reset flow for assertion of the RESET pin. Figure 4-2 shows the internal processing of reset for all reset sources. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 96 RESET Asserted? Wait 2 Clock Cycles RESET Asserted? Set Latch, Wait 8 Clock Cycles RESET Set RGF Bit Asserted? To entry point in internal reset flow Figure 4-1. External reset flow diagram MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 97 Values Wait 4 Clock Cycles NOTES: 1. The clock count CNT depends on the reset source and type of clock reference. Please refer to Table 4-3. Figure 4-2. Internal reset flow diagram MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 98: Power-On Reset (Por)
(assertion of RSTOUT), as is the PLLREF value. Once the FMPLL Loss of Lock reset request signal is negated, the reset controller waits for a predetermined number of clock cycles (refer to Section 4.3.2, RSTOUT). Once the clock count finishes, the WKPCFG and BOOTCFG[0:1] pins are sampled. The reset MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 99: Loss Of Clock
Register and Timer Control Register, as for more information on the core watchdog timer and debug operation. Refer to Chapter 20, Software Watchdog Timer (SWT), for more information on the platform watchdog. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 100: Jtag Reset
The System Integration Unit (SIU) on this device includes two registers, SIU_RSR and SIU_SRCR, that affect the reset behavior of this device. See Chapter 16, System Integration Unit (SIU), for descriptions of these registers. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 101: Reset Configuration
When booting from the external flash device, the RCHW must reside in the first 16 bits of memory. BOOT_BLOCK_ADDRESS + 0x0000_0000 SWT WTE Boot Identifier = 0x5A Figure 4-3. Reset Configuration Half Word MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 102 PLL is programmed with different multipliers. Table 4-6. Watchdog timeout periods Crystal frequency (MHz) Core WD timeout (ms) SWT timeout (ms) 40.1 32.7 27.3 21.8 20.5 16.35 16.4 13.08 6.54 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 103: Reset Configuration Timing
‘1’ during POR assertion. NOTE: 1. The clock count CNT depends on the reset source and type of clock reference. Please refer to Table 4-3. Figure 4-4. Reset configuration timing MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 104: Reset Weak Pull Up/Down Configuration
The final value of WKPCFG is latched four clock cycles before the negation of RSTOUT. After reset, software may modify the weak pull up/down selection for all I/O pins through the PCR registers in the SIU. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 105: Overview
Table 5-2 lists the modules that support Module Disable Mode. The register and bit in each module that must be written to enter or MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 106: Clock Architecture
Clock architecture The following sections detail the MPC5644A clocking architecture. 5.3.1 Overview This section describes different sources for the system clocks. The MPC5644A clocking architecture consists of the following: • On-chip MHz oscillator: Range (4–40 MHz) •...
Page 107: Block Diagram
— MHz crystal oscillator bypassed • PLL enabled — MHz crystal oscillator (with crystal as the reference) output used as PLL reference frequency — MHz crystal oscillator (bypassed) output used as PLL reference frequency MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 108 System clock = 100 MHz 5.3.3.3 Support for FlexRay operation The MPC5644A MCU supports generation of the clock signals needed for the operation of the FlexRay module. Two options are supported for the generation of the FlexRay clock: • If the PLL is used with Frequency Modulation enabled, a 40 MHz crystal or external clock source must be used to supply the FlexRay clock.
Page 109: Fmpll Modes Of Operation
Phase detector, making the VCO run within its free-running frequency range of 25 MHz to 125 MHz, unconnected from the system clock (since bypass is the default mode at reset). If using crystal reference, MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 110 Bypass mode with external reference is the default mode at reset if the PLLREF pin is driven low. After reset, this mode can be entered by programming FMPLL_ESYNCR1[CLKCFG] as shown in Table 5-1. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 111 The PLL output frequency (before the system clock divider) must not exceed the maximum device operating frequency. Therefore, when operating at the maximum operating frequency, the only division factor allowed in the system clock divider is divide-by-1. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 112 Software controlled power management and clock gating is supported on a peripheral by peripheral basis, using a three tiered approach. The first tier is a clock gating feature implemented in some of the IP MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 113 5-2, along with the registers and bits that disable each module. The software controlled clocks are enabled when the CPU comes out of reset. 1. For compatibility with legacy devices, the default value of MDIS bit is zero. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 114 CPU is in wait state due to the execution of the WAIT instruction. NOTE To gate the CPU clock you need to first program the SIU_HLT register bit assigned for CPU and then execute the CPU WAIT instruction. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 115 SIU_ECCR[EBDF] selects a CLKOUT frequency of one half of the system clock frequency. The EBI supports gating of the CLKOUT signal when there are no external bus accesses in progress. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 116 The FlexCAN module does not support a divide-by-1 of the system clock above a certain frequency, defined in the devicedatasheet. When running at maximum system frequency this setting will have to be adjusted from its default value. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 117: Introduction
This chapter provides guidance for users to fully optimize their application to achieve the highest possible performance from the MPC5644A. It provides a description of the areas that should be focused on when optimizing an application for performance by describing the features and recommending settings to be applied.
Page 118: Configuring Hardware Features
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 1013; Read/Write; Reset - 0x0 Figure 6-1. Branch Unit Control and Status Register (BUCSR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 119: Frequency-Modulated Pll
6.3.2.2 Recommended configuration The default operating frequency of the MPC5644A device is 2 to 3 times the crystal reference frequency depending on the state of the PLL configuration pins as reset negates. Typically, the system frequency is increased shortly after reset negates to provide acceptable performance.
Page 120: Flash Bus Interface Unit
This also provides recommendations for the prefetch buffer settings. Note that the BIUCRx settings may vary between revisions of the MPC5644A. 6.3.4 Crossbar switch 6.3.4.1...
Page 121: Cache
6.3.5.1 Description The MPC5644A provides an 8 KB Instruction, 2-way or 4-way set-associative, Harvard cache design with a 32-byte line size. The cache is disabled by default when reset is negated. The cache improves system performance by providing low-latency instructions to the e200z4 instruction pipelines, which decouples processor performance from system memory performance.
Page 122 During cache invalidations, the parity check bits are written with a value dependent on the ICEDT selection. ICEDT should be written with the desired value for subsequent cache operation when ICINV is set to ‘1’ for proper operation of the cache. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 123: Memory Management Unit (Mmu)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 626; Read/Write Figure 6-3. MMU Assist Register 2 (MAS2) Table 6-3. MAS2 field descriptions Field Description Effective page number [0:21] MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 124: Application Software
A trade-off between code size and performance Although this is an extreme example, it highlights how significant the role of the compiler and linker is in determining the overall performance of an application. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 125: Signal Processing Extension
Impulse Response (FIR), Infinite Impulse Response (IIR) and Discrete Fourier Transforms (DFT). A more general benefit of the SPE instruction set is the ability to load/store 64-bits of data in single instruction. Thus highly load/store intensive functions make good candidates for SPE optimization. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 126: Hardware Single Precision Floating Point
VLE (variable-length encoding) APU, providing improved code density. The VLE-APU can be viewed as a supplement to the existing Power Architecture instruction set that can be conditionally applied to a portion of, or an entire application for which improved code density is desired. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 127: Peripherals And General Application Guidelines
(ADC) ,while maintaining circular buffers results of the ADC in the system RAM, with no core intervention. Section 6.6, Performance optimization checklist provides several system level examples of how to optimize an application. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 128: Performance Optimization Checklist
Take advantage of the SPE-APU to encode time critical functions using SPE assembly code. Variable Length Encoding Enabled with TLB_MAS2[VLE] Set compiler switches and configure the MMU to take advantage of the VLE-APU. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 129 • Reduce external bus wait states from default maximum settings. • Place time critical functions in internal memory. • Small, but frequently executed routines can be considered as candidates to be locked in cache. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 130 Device Performance Optimization MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 131: Overview
Core Chapter 7 e200z4 Core This chapter contains an overview of the e200z4 processor core integrated in MPC5644A devices. For ® detailed information see the publication e200z4 Power Architecture Core Reference Manual on www.freescale.com. NOTE There are two differences between the processor core in MPC5644A devices and the e200z4 documented in the core reference manual.
Page 132: Microarchitecture Summary
The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 133 32-bits and the normal integer type. Low latency fixed-point and floating-point add, subtract, multiply, multiply-add, multiply-sub, divide, compare, and conversion operations are provided, and most operations can be pipelined. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 134: Instruction Unit Features
Instruction buffer holds up to eight 32-bit instructions • Dedicated PC incrementer supporting instruction prefetches • Branch unit with dedicated branch address adder, and branch lookahead logic (BTB) supporting single cycle execution of successfully predicted branches MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 135: Integer Unit Features
• Correction/Auto-invalidation capability 7.3.5 MMU features The features of the MMU are as follows: • Virtual Memory support • 32-bit Virtual and Physical Addresses • 8-bit Process Identifier • 24-entry fully-associative TLB MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 136: E200Z4 System Bus Features
• Auxiliary interface for higher data input/output. • Registers for Program Trace, Data Trace, Ownership Trace, Data Acquisition, and Watchpoint Trigger control. • All features controllable and configurable via the JTAG port. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 137: Introduction
Slave read data Bus write data Bus address *n = 64 channels for eDMA eDMA Peripheral Request eDMA Done Figure 8-1. eDMA block diagram 8.1.2 Features The eDMA has these major features: MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 138: Modes Of Operation
In normal mode, the eDMA is used to transfer data between a source and a destination. The source and destination can be a memory block or an I/O block capable of operation with the eDMA. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 139: External Signal Description
EDMA_BASE + 0x0014 EDMA_EEIRL—eDMA enable error interrupt register on page 8-154 (channels 31–00) EDMA_BASE + 0x0018 EDMA_SERQR—eDMA set enable request register on page 8-155 EDMA_BASE + 0x0019 EDMA_CERQR—eDMA clear enable request register on page 8-155 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 140 EDMA_BASE + 0x010C EDMA_CPR12—eDMA channel 12 priority register on page 8-163 EDMA_BASE + 0x010D EDMA_CPR13—eDMA channel 13 priority register on page 8-163 EDMA_BASE + 0x010E EDMA_CPR14—eDMA channel 14 priority register on page 8-163 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 141 EDMA_BASE + 0x012C EDMA_CPR44—eDMA channel 44 priority register on page 8-163 EDMA_BASE + 0x012D EDMA_CPR45—eDMA channel 45 priority register on page 8-163 EDMA_BASE + 0x012E EDMA_CPR46—eDMA channel 46 priority register on page 8-163 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 142 EDMA_BASE + 0x1140 EDMA_TCD10—eDMA transfer control descriptor 10 on page 8-165 EDMA_BASE + 0x1160 EDMA_TCD11—eDMA transfer control descriptor 11 on page 8-165 EDMA_BASE + 0x1180 EDMA_TCD12—eDMA transfer control descriptor 12 on page 8-165 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 143 EDMA_BASE + 0x1540 EDMA_TCD42—eDMA transfer control descriptor 42 on page 8-165 EDMA_BASE + 0x1560 EDMA_TCD43—eDMA transfer control descriptor 43 on page 8-165 EDMA_BASE + 0x1580 EDMA_TCD44—eDMA transfer control descriptor 44 on page 8-165 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 144 Enable Error Interrupt Low (EDMA_EEIRL, channels 31–16) (EDMA_EEIRL, Channels 15–00) 0xFFF4_4018 eDMA Set Enable eDMA Clear Enable eDMA Set Enable eDMA Clear Enable Request Request Error Interrupt Error Interrupt (EDMA_SERQR) (EDMA_CERQR) (EDMA_SEEIR) (EDMA_CEEIR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 145 Channel 27 Priority Priority Priority Priority (EDMA_CPR16) (EDMA_CPR17) (EDMA_CPR18) (EDMA_CPR19) 0xFFF4_411C eDMA Channel 28 eDMA Channel 29 eDMA Channel 30 eDMA Channel 31 Priority Priority Priority Priority (EDMA_CPR16) (EDMA_CPR17) (EDMA_CPR18) (EDMA_CPR19) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 146: Register Descriptions
Reading reserved bits in a register returns the value of zero. Writes to reserved bits in a register are ignored. Reading or writing to a reserved memory location generates a bus error. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 147 When either of the minor loop offsets is enabled (SMLOE is set or DMLOE is set), the NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled (SMLOE is cleared and DMLOE is cleared), the NBYTES field becomes a 30-bit vector. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 148 NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 149 (DLAST_SGA) is not aligned on a 32-byte boundary. If minor loop channel linking is enabled on channel completion, a configuration error is reported when the link is attempted if bit EDMA_TCD[CITER.E_LINK] is not equal to bit EDMA_TCD[BITER.E_LINK]. All configuration error MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 150 A channel that experiences an error condition is not automatically disabled. If a channel is terminated by an error and then issues another service request before the error is fixed, that channel will execute and terminate with the same error condition. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 151 EDMA_TCD[SADDR] is inconsistent with EDMA_TCD[SSIZE]. Source Offset Error 0 No source offset configuration error 1 The last recorded error was a configuration error detected in field EDMA_TCD[SOFF], indicating EDMA_TCD[SOFF] is inconsistent with EDMA_TCD[SSIZE]. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 152 Both the eDMA request input signal and this enable request flag must be asserted before a channel’s hardware service request is accepted. The state of the eDMA enable request flag does not effect a channel service request made through software or a linked channel request. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 153 EDMA_TCD[D_REQ] is set, then the corresponding EDMA_ERQR bit is cleared after the major loop is complete, disabling the eDMA hardware request. Otherwise if the D_REQ bit is cleared, the state of the EDMA_ERQR bit is unaffected. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 154 Access: User read/write Reset Reset Figure 8-6. eDMA Enable Error Interrupt High Register (EDMA_EEIRH) Address: EDMA_BASE + 0x0014 Access: User R/W Reset Reset Figure 8-7. eDMA Enable Error Interrupt Low Register (EDMA_EEIRL) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 155 EDMA_ERQRL to be zeroed, disabling all eDMA request inputs. Reads of this register return all zeroes. If bit 0 is set, the CERQ command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 156 0 Normal operation 1 No operation, ignore bits 1–7. 1–7 Set Enable Error Interrupt SEEI[0:6] 0–32 (64 for eDMA) Set corresponding bit in EDMA_EIRRH or EDMA_EIRRL. 64–127 Set all bits in EDMA_EIRRH or EDMA_EEIRL. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 157 EDMA_IRQRL to be zeroed, disabling all eDMA interrupt requests. Reads of this register return all zeroes. If bit 0 is set, the CINT command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 158 0 Normal operation 1 No operation, ignore bits 1–7. CERR[0:6] Clear Error Indicator 0–32 (64 for eDMA) Clear corresponding bit in EDMA_ERH or EDMA_ERL. 64–127 Clear all bits in EDMA_ERH or EDMA_ERL. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 159 If bit 0 is set, the CDSB command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes. Offset: EDMA_BASE + 0x001F Access: User write-only CDSB[0:6] Reset Figure 8-15. eDMA Clear DONE Status Bit Register (EDMA_CDSBR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 160 EDMA_IRQRH and EDMA_IRQRL. Address: EDMA_BASE + 0x0020 Access: User R/W Reset Reset Figure 8-16. eDMA Interrupt Request High Register (EDMA_IRQRH) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 161 EDMA_ERH or EDMA_ERL, a ‘1’ in any bit position clears the corresponding channel’s error status. A ‘0’ in any bit position has no effect on the corresponding channel’s current error status. The EDMA_CER is provided so the error indicator for a single channel can be cleared. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 162 Registers EDMA_HRSH and EDMA_HRSL provide a bitmap for the implemented channels (32 or 64) to show the current hardware request status for each channel. EDMA_HRSH maps to channels 64–32 and EDMA_HRSL maps to channels 31-00. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 163 Otherwise, a configuration error is reported. The range of the priority value is limited to the MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 164 1 Channel n can be temporarily suspended by the service request of a higher priority channel. Disable pre-empt ability Channel n can suspend a lower priority channel. Channel n cannot suspend any channel, regardless of channel priority. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 165 0x1000 (32 x n) 0x0018 Last destination address adjustment / scatter-gather address (dlast_sga) 0x1000+(32 x n)+0x001c Beginning major iteration count (biter) Channel control/status Figure 8-23 Table 8-20 define the fields of the TCDn structure. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 166 The TCD structures for the eDMA channels shown in Figure 8-23 implemented in internal SRAM. These structures are not initialized at reset; therefore, all channel TCD parameters must be initialized by the application code before activating that channel. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 167 This flag selects whether the minor loop offset is applied to the destination address upon minor loop completion. 0 The minor loop offset is not applied to the daddr. 1 The minor loop offset is applied to the daddr. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 168 TCD bits [161:175] are used to form a 15-bit CITER field. Otherwise, • After the minor loop is exhausted, the DMA engine initiates a channel service request at the channel defined by CITER.LINKCH[0:5] by setting that channel’s EDMA_TCD[START] bit. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 169 Note: When the TCD is first loaded by software, this field must be set equal to the corresponding CITER field. Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 170 (when the DMA engine has begun processing the channel, not when the first data transfer occurs). Note: This bit must be cleared to write the MAJOR.E_LINK or E_SG bits. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 171 CITER = BITER = 1 with INT_HALF enabled will generate an interrupt as it satisfies the equation (CITER == (BITER >> 1)) after a single activation. 0 The half-point interrupt is disabled. 1 The half-point interrupt is enabled. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 172: Functional Description
(matching the maximum transfer size) and the necessary mux logic to support any required data alignment. The system read data bus is the primary input, and the system write data bus is the primary output. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 173: Edma Basic Data Flow
After the arbitration is complete, the activated channel number is sent through the address path and converted into the required address to access the TCD local memory. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 174 This source read/destination write processing continues until the inner minor byte count has been transferred. The eDMA done handshake signal is asserted at the end of the minor byte count transfer. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 175 TCD from memory using the scatter-gather address pointer included in the descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 8-26. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 176: Initialization / Application Information
After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. The DMA engine reads the entire TCD, including the primary MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 177 DMA arbitration can occur after each minor loop, and one level of minor loop DMA pre-emption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (biter). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 178: Dma Programming Errors
The DMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per-channel basis with the exception of two errors: MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 179: Dma Request Assignments
EQADC.FISR0[CFFF0] eQADC Command FIFO 0 Fill Flag eQADC_FISR0_RFDF0 EQADC.FISR0[RFDF0] eQADC Receive FIFO 0 Drain Flag eQADC_FISR1_CFFF1 EQADC.FISR1[CFFF1] eQADC Command FIFO 1 Fill Flag eQADC_FISR1_RFDF1 EQADC.FISR1[RFDF1] eQADC Receive FIFO 1 Drain Flag MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 180 Channel 0 Data Transfer Request Status eTPU_CDTRSR_A_DTRS1 ETPU.CDTRSR_A[DTRS1] eTPUA Channel 1 Data Transfer Request Status eTPU_CDTRSR_A_DTRS2 ETPU.CDTRSR_A[DTRS2] eTPUA Channel 2 Data Transfer Request Status eTPU_CDTRSR_A_DTRS1 ETPU.CDTRSR_A[DTRS14] eTPUA Channel 14 Data Transfer Request Status MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 181 SIU External Interrupt Flag 3 DECFIL_FILL_BUF_A DECFIL_A.DECFILTER_IB[INPBUF] Decimation Filter A Fill Buffer DECFIL_DRAIN_BUF_A DECFIL_A.DECFILTER_OB[OUTBUF Decimation Filter A Drain Buffer DECFIL_FILL_BUF_B DECFIL_B.DECFILTER_IB[INPBUF] Decimation Filter B Fill Buffer DECFIL_DRAIN_BUF_B DECFIL_B.DECFILTER_OB[OUTBUF Decimation Filter B Drain Buffer MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 182: Dma Arbitration Mode Considerations
Section 8.5.4.2, Round-robin group arbitration, fixed-channel arbitration but this time channels are serviced in channel number order. One channel only is serviced from each requesting group for each round robin pass through the groups. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 183: Dma Transfer
The final source and destination addresses are adjusted to return to their beginning values. EDMA_TCD[CITER] = EDMA_TCD[BITER] = 1 EDMA_TCD[NBYTES] = 16 EDMA_TCD[SADDR] = 0x1000 EDMA_TCD[SOFF] = 1 EDMA_TCD[SSIZE] = 0 EDMA_TCD[SLAST] = –16 EDMA_TCD[DADDR] = 0x2000 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 184 EDMA_ERQR, channel service requests are initiated by the slave device (ERQR should be set after TCD). Note that EDMA_TCD[START] = 0. EDMA_TCD[CITER = EDMA_TCD[BITER] = 2 EDMA_TCD[NBYTES] = 16 EDMA_TCD[SADDR] = 0x1000 EDMA_TCD[SOFF] = 1 EDMA_TCD[SSIZE] = 0 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 185 Æ first iteration of the minor loop c) read_byte(0x1014), read_byte(0x1015), read_byte(0x1016), read_byte(0x1017) d) write_word(0x2014) Æ second iteration of the minor loop e) read_byte(0x1018), read_byte(0x1019), read_byte(0x101A), read_byte(0x101B) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 186: Tcd Status
EDMA_TCD[START] was written to a ‘1’. Polling the EDMA_TCD[ACTIVE] bit may be inconclusive because the active status may be missed if the channel execution is short in duration. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 187 Channel and group priorities are treated as equal (or more exactly, constantly rotating) when round-robin arbitration mode is selected. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 188: Channel Linking
Table 8-24 summarizes how a DMA channel can link to another DMA channel, that is, use another channel’s TCD, at the end of a loop. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 189: Dynamic Programming
TCD.word7 after that channel’s TCD.done bit is set, indicating the major loop is complete. NOTE The user must clear the TCD.done bit before writing the TCD.major.e_link bit. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 190 (daddr) that was calculated using a scatter/gather address (written in the next step) instead of a dlast final offest value. Write theTCD.dlast_sga field with the scatter/gather address. Write 1b to the TCD.e_sg bit. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 191 • If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). • If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the new TCD’s e_sg value cleared the e_sg bit). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 192 Enhanced Direct Memory Access Controller (eDMA) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 193: Introduction
Table 9-1. Table 9-1. Master/Slave mappings Port Module Physical master ID Type Logical number e200z4 core instruction Master e200z4 core Load/Store Master e200z4 core Nexus Master eDMA Master FlexRay Interface Master Master MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 194: Features
It is possible to make single clock (zero wait state) accesses through the XBAR. If the targeted slave port of the access is busy or parked on a different master port the requesting master will simply see wait MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 195: Xbar Registers
The registers will still be readable, but future write attempts will have no effect on the registers and will be terminated with an error response. The memory map for the XBAR program-visible registers is shown in Table 9-2. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 196: Xbar Register Descriptions
Write 1 Self-clear reads 1 reads 0 only bit only bit to clear Figure 9-2. Key to Register Fields “BIT” refers to a field name in the register. Some fields span multiple bits. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 197 These bits are initialized by hardware reset. The reset value is 110. 000: This master has the highest priority when accessing the slave port. 111: This master has the lowest priority when accessing the slave port. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 198 111: This master has the lowest priority when accessing the slave port. Reserved This bit is reserved for future expansion. It is read as zero and should be written with zero for upward compatibility. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 199 Once the RO (Read Only) bit has been set in the SGPCR the SGPCR can only be read, attempts to write to it will have no effect on the SGPCR and result in an error response. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 200 1: The mX_high_priority input is enabled on this slave port. 16:21 Reserved These bits are reserved for future expansion. They are read as zero and should be written with zero for upward compatibility. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 201: Coherency
The values of the registers do not track with slave port related AHB accesses but instead track only with IP bus accesses. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 202: Function
The next master in line will be granted access to the slave port if the current master has no pending access request. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 203: Priority Assignment
Each master port needs to be assigned a unique 3-bit priority level. If an attempt is made to program multiple master ports with the same priority level within a register (MPR) the XBAR will respond with an error and the registers will not be updated. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 204 Multi-Layer AHB Crossbar Switch (XBAR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 205: Pbridge Features
10.3 PBRIDGE block diagram The PBRIDGE is the interface between the system bus interface and on-chip peripherals as shown in Figure 10-1. Crossbar Switch Peripheral Bridge B (PBRIDGE0) Figure 10-1. PBRIDGE interface MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 206: Pbridge Signal Description
Accesses to registers or register fields marked as reserved will return zeros on reads, and will be ignored on writes. Table 10-1. PBRIDGE registers Offset from PBRIDGE_BASE Register Location (0xFFF0_0000) 0x0000–0x0007 Master Privilege Control Registers (MPCR) on page 10-208 0x0008–0x001F Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 207 Reserved 0x0054 Reserved 0x0058 Reserved 0x005C Reserved OPACR5 Reserved 0x0060 OPACR6 OPACR6 OPACR6 OPACR6 OPACR6 Reserved OPACR7 0x0064 OPACR7 Reserved OPACR7 0x0068 OPACR8 OPACR8 OPACR8 OPACR8 OPACR8 Reserved 0x006C Reserved OPACR9 Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 208: Register Descriptions
Reset value MPCR 0 z4 core (instruction + load/store) 0b0111, meaning MTR = 1 MPCR 4 MTW = 1 MPL = 1 MPCR 6 FlexRay MPCR 7 MPCR 8 z4 core Nexus MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 209 Peripheral Reset value PACR 1 Crossbar 0100b, meaning SP = 1 PACR 4 WP = 0 TP = 0 PACR 14 PACR 15 PACR 16 ECSM PACR 17 PACR 18 Interrupt controller MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 210 OPACR 13 eSCI B OPACR 14 eSCI C OPACR 16 FlexCAN A OPACR 17 FlexCAN B OPACR 18 FlexCAN C OPACR 24 FlexRay OPACR 27 System Information Module OPACR 31 OPACR 58 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 211 OPACR 71 OPACR 72 eMIOS OPACR 79 OPACR 80 eTPU2 OPACR 81 Reaction module OPACR 82 eTPU parameter RAM OPACR 83 eTPU parameter RAM mirror OPACR 84 eTPU code RAM OPACR 92 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 212 Peripheral Bridge (PBRIDGE) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 213: Introduction
Chapter 11 General-Purpose Static RAM (SRAM) 11.1 Introduction The MPC5644A includes 192 KB of general-purpose SRAM. The first 32 KB of SRAM is powered by its own power supply pin during standby operation. 11.2 Features The SRAM controller includes these features: •...
Page 214: External Signal Description
SRAM does not detect all errors greater than 2 bits. Internal SRAM writes are done on byte boundaries: • 1 byte (0:7 bits) • 2 bytes (0:15 bits) • 4 bytes or 1 word (0:31 bits) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 215: Access Timing
If a reset event asserts during a read or write operation to SRAM, the completion of that access depends on the cycle at which the reset occurs. Data read from or written to SRAM before the reset event occurred is retained, and no other address locations are accessed or changed. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 216: Initialization And Application Information
# write all 32 GPRs to SRAM addi r11,r11,128 # inc the ram ptr; 32 GPRs * 4 bytes = 128 bdnz init_ram_loop # loop for 192K of SRAM # done MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 217: Introduction
The MI contains the registers and logic which control the operation of the FC. The MI is also the interface to the platform flash bus interface unit (PFBIU). The flash array’s core has three address spaces: low-address space, mid-address space, and high-address space (see Figure 12-1). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 218: Block Diagram
Figure 12-2 shows a block diagram of the flash memory module. The FBIU is addressed through the system bus while the flash control and status registers are addressed through the slave (peripheral) bus. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 219: Features
Configurable read buffering and line prefetch support. Device flash has 2 sets of 4 line read buffers—1 set for the 128-bit wide low- and medium-address space and 1 set for the 256-bit wide high address space. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 220: Modes Of Operation
1. Software executing from flash must not write to registers that control flash behavior, e.g., wait state settings or prefetch enable/disable. Doing so can cause data corruption. On MPC5644A devices these registers include BIUCR, BIUAPR, and BIUCR2.Further, flash configuration registers should be written only with 32-bit write operations to avoid any issues associated with register “incoherency”...
Page 221: Module Memory Map
0x0030_0000 0x0038_0000 0x0040_0000 Reserved 0x00EF_C000 Shadow row (Flash B) 0x00F0_0000 Reserved 0x00FF_C000 Shadow row (Flash A) 0x0100_0000 Reserved For read-while-write operations, the shadow row behaves as if it is in all partitions. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 222 —Bus interface unit configuration register on page 12-234 0x0020 BIUAPR —Bus interface unit access protection register on page 12-237 0x0024 BIUCR2 —Bus interface unit configuration register 2 on page 12-238 0x0028 – 0x0038 Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 223: Register Descriptions
Register is only accessible via Flash A. Treat as “Reserved” in Flash B. 12.3.2 Register descriptions This section lists the flash memory registers in address order and describes the registers and their bitfields. 12.3.2.1 Module Configuration Register (MCR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 224 The value of the MAS field corresponds to the configuration of the Mid-Address Space. MAS is read only. 0: Two 128 KB blocks 1: One 256 KB block (Only available if LAS = 0) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 225 1 at the end of program and erase high voltage sequences. DONE is set to a 1 within a 1 to 0 transition of EHV which aborts a high voltage operation. 0: Flash is executing a high voltage operation. 1: Flash is not executing a high voltage operation. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 226 UTE is low). ERS can be cleared by the user only when ESUS and EHV are low and DONE is high. ERS is cleared on reset. 0: Flash is not executing an erase sequence. 1: Flash is executing an erase sequence. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 227 The flash module does not allow the user to write bits simultaneously which put the device into an illegal state. This is implemented through a priority mechanism among the bits. The bit changing priorities are detailed in Table 12-5. Table 12-5. MCR bit set/clear priority levels Priority level MCR bit(s) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 228 For LME, the password 0xA1A1_1111 must be written to the LMLR. 0: Low/Mid-Address Locks are disabled, and can not be modified. 1: Low/Mid-Address Locks are enabled to be written. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 229 A reset value of 1* in Figure 12-5 indicates that the reset value of these registers is determined by Flash values in the shadow block. An erased shadow block causes the reset value to be 1. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 230 A reset value of 1* in Figure 12-6 indicates that the reset value of these registers is determined by Flash values in the shadow block. An erased shadow block causes the reset value to be 1. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 231 SLLOCK has the same description as LLOCK. SLLOCK is not writable unless SLE is high. 12.3.2.5 Low/Mid-Address Space Block Select Register (LMSR) The Low/Mid-Address Space Block Select Register (LMSR) provides a means to select blocks to be operated on during erase. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 232 The reset value is always 0, and register writes have no effect. 12.3.2.6 High-Address Space Block Select Register (HSR) The High-Address Space Block Select Register (HSR) provides a means to select blocks to be operated on during erase. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 233 The Address register (AR) provides the first failing address in the event module failures (ECC or PGM/Erase state machine) Offset 0x0018 Access: User read/write ADDR[14-13] Reset ADDR[12-0] Reset = Unimplemented or Reserved Figure 12-9. Address Register (AR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 234 The Bus Interface Unit Configuration Register (BIUCR) is used to specify operation of the dual-flash controller. Offset: FLASH_REGS_BASE + 0x001C Access: User read/write Reset WWSC RWSC PFLIM Reset Figure 12-10. Bus Interface Unit Configuration Register (BIUCR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 235 This field is set to 0b11 by hardware reset. 00: No additional wait-states are added 01: One additional wait-state is added 10: Two additional wait-states are added 11: Three additional wait-states are added MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 236 1: The line read buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers are successfully filled. Valid settings are specified in the device data sheet. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 237 Note: These bits refer to the master ID, not the master port number, as shown in the following: Master ID Module z4 Core Instruction z4 Core Load/Store eDMA FlexRay External Bus Interface (EBI) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 238 The User Test 0 (UT0) Register provides a means to control UTest. The UTest mode gives the users of the flash module the ability to perform test features on the flash. This register is only writable when the flash is put into UTest mode by writing a passcode. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 239 Array Integrity Checks. Normal user reads are not affected by MRE. MRE is not writable if AID is low. 0: Margin reads are not enabled. 1: Margin reads are enabled during Array Integrity Checks. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 240 (UMISR registers) can be checked. AID can not be written, and is status only. 0: Array integrity check is ongoing. 1: Array integrity check is done. 12.3.2.12 User Test 1 (UT1) Register The User Test 1 (UT1) Register provides added controllability to UTest. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 241 Word 1of the double word selected in the AR. 12.3.2.14 User Multiple Input Signature Register [0:4] (UMISRn) The User Multiple Input Signature Registers (UMISRn) provide a means to evaluate array integrity. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 242 Figure 12-17. User Multiple Input Signature Register 1 (UMISR1) Offset: FLASH_REGS_BASE + 0x0050 Access: User read/write MS[095-080] Reset MS[079-064] Reset = Unimplemented or Reserved Figure 12-18. User Multiple Input Signature Register 2 (UMISR2) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 243 Figure 12-19. User Multiple Input Signature Register 3 (UMISR3) Offset: FLASH_REGS_BASE + 0x0058 Access: User read/write Reset MS[143-128] Reset = Unimplemented or Reserved Figure 12-20. User Multiple Input Signature Register 4 (UMISR4) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 244 To be able to write the MISR registers: 1) Assert reset after each user margin read sequence so that MISRs can be written again. 2) Do a dummy program to a locked block after user margin read. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 245: Functional Description
The FC is also divided into blocks to implement independent erase or program protection. The shadow block exists outside the normal address space and is programmed, erased, and read independently of the MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 246: Utest Mode
It is not possible to do UTest operations on the shadow block. 3. If desired, Set the UT0[AIS] bit to 1 for sequential addressing only. NOTE For normal integrity checks of the flash memory, sequential addressing is recommended. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 247 It is possible to do User Mode array reads during the Factory Margin Read test, if desired, but the partition rules for Read While Write used during program and erase are in effect during Factory Margin Reads. 3. Set the UT0[MRE] bit. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 248 Check (UTO[EIE] high), the ADR register will not be loaded, and the address tagged to receive the UT0[DSI], UT1[DAI] and/or UT2[DAI] values will be persevered. 6. Once completed, clear the UT0[EIE] bit to 0. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 249: Flash Programming
This first write is referred to as an interlock write. If the program is not an erase-suspended program, the interlock write determines if the shadow or normal array space will be programmed and causes MCR[PEAS] to be set/cleared. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 250 CAUTION Aborting a program operation will leave the flash core addresses being programmed in an indeterminate data state. This may be recovered by executing an erase on the affected blocks. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 251 Note: PEG will remain valid under this condition until EHV is set high or PGM is cleared. Step 9 Write MCR PGM = 0 ESUS User mode read state Erase suspend Figure 12-21. Program Sequence MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 252: Flash Erase
2. Select the block, or blocks, to be erased by writing 1s to the appropriate bits in LMSR or HSR. If the shadow row is to be erased, this step may be skipped, and LMSR and HSR are ignored. For shadow row erase, see Section 12.4.7, Flash shadow block, for more information. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 253 Read While Write may also be used to read the array during an erase sequence providing the read is to a partition not selected for erase. An erase suspend can be initiated by changing the value of the MCR[ESUS] bit from a 0 to a 1. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 254 T esrt WARNING In an erase-suspended program, programming flash locations in blocks which were being operated on in the erase may corrupt flash core data. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 255: Flash Shadow Block
MCR[PEAS] = 1 only. After the user has begun an erase operation on the shadow block, the operation cannot be suspended to program the main address space and vice-versa. The user must terminate the shadow erase operation to program or erase the main address space. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 256: Flash Reset
12.4.9 DMA requests The flash has no DMA requests. 12.4.10 Interrupt requests The flash has no interrupt requests. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 257: Introduction
— 64-bit error registers, one for each XBAR slave port, capture the last faulting address, attributes, and detail information 1. EBI not available on all packages and is not available, as a master, for customer. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 258: Modes Of Operation
MPU_EAR0 — MPU error address register, slave port 0 on page 13-262 0x0014 MPU_EDR0 — MPU error detail register, slave port 0 on page 13-263 0x0018 MPU_EAR1 — MPU error address register, slave port 1 on page 13-262 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 259 0x04D0 MPU_RGD13 — MPU region descriptor 13 on page 13-264 0x04E0 MPU_RGD14 — MPU region descriptor 14 on page 13-264 0x04F0 MPU_RGD15 — MPU region descriptor 15 on page 13-264 0x00500–0x07FF Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 260: Register Descriptions
MPU_RGDAAC15 — MPU RGD alternate access control 15 on page 13-269 0x0840–0x3FFF Reserved 13.4.2 Register descriptions This section lists the MPU registers in address order and describes the registers and their bitfields. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 261 Hardware Revision Level This 4-bit read-only field specifies the MPU’s hardware and definition revision level. It can be read by software to determine the functional definition of the module. This field reads as 0 on MPC5644A. MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 262 Description 16–19 Number of Slave Ports This 4-bit read-only field specifies the number of slave ports [1–8] connected to the MPU. This field reads as 0b0010 on the MPC5644A at reset, indicating two slaves. 20–23 Number of Region Descriptors NRGD This 4-bit read-only field specifies the number of region descriptors implemented in the MPU.
Page 263 This 8-bit read-only field records the process identifier of the faulting reference. The process identifier is typically driven by processor cores only; for other bus masters, this field is cleared. 1. See Table 13-1 Section 13.2, MPU-to-XBAR slave port mapping, for MPU slave port details. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 264 – – – – – – SRTADDR[10:0] Reset – – – – – – – – – – – = not implemented Figure 13-4. MPU Region Descriptor n, Word 0 Register (MPU_RGDn.Word0) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 265 For these fields, the bus master number refers to the physical master ID defined in Table 9-1 Chapter 9, Multi-Layer AHB Crossbar Switch (XBAR). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 266 – – – – – = not implemented Refer to Table 9-1, in the XBAR chapter, to see the Master ID assignments. Figure 13-6. MPU Region Descriptor n, Word 2 Register (MPU_RGDn.Word2) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 267 (if not allowed by any other descriptor) and the access not performed. 13.4.2.4.4 MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3) The fourth word of the MPU region descriptor contains the optional process identifier and mask, plus the region descriptor’s valid bit. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 268 This 8-bit field specifies that the optional process identifier is to be included in the determination of whether the current access hits in the region descriptor. This field is combined with the PIDMASK and included in the region hit determination if MPU_RGDn.Word2[MxPE] is set. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 269 Figure 13-8. MPU RGD Alternate Access Control n (MPU_RGDAACn) Because the MPU_RGDAACn register is another memory mapping for MPU_RGDn.Word2, the field definitions shown in Table 13-10 are identical to those presented in Table 13-8. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 270 (if not allowed by any other descriptor) and the access not performed. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 271: Functional Description
The third condition reflects that priority is given to permission granting over access denying for overlapping regions as this approach provides more flexibility to system software in region descriptor MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 272: Initialization Information
Word0 and Word1 redefine the start and end addresses respectively and the write to Word3 re-enables the region descriptor valid bit. In many situations, all four words of the region descriptor would be rewritten. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 273 CP0 to CP1 and the access controls are defined by the logical OR of the two region descriptors. Thus, CP0 has (r w – | r – –) = (r w –) permissions, while CP1 has MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 274 PID=2). The core immediately takes the exception as a 'machine check'. In this case, modify the 'machine check' exception handler to expect this behavior. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 275: Information Specific To This Device
24-bit address bus (2 most significant signals multiplexed with 2 chip selects) • The MPC5644A MCU has only 16 data bus signals pinned out. The data bus can be multiplexed with the address bus to have a 32-bit data width mode.
Page 276: Overview
14.2.1 Overview On the MPC5644A microcontroller, the EBI supports two sets of external signals: the EBI bus signals and the calibration bus signals. They are very similar in function but have different purposes. The calibration bus is a powerful development feature that enables system designers to interface dual-port SRAM with a system under development.
Page 277 Region 0 Region 2 Region 3 Controls Controls Controls Controls WE[0:3] BDIP RD_WR ADDR[13:30] WE[0:1]/BE[0:1] DATA[0:31] External External External External Memory Memory Memory Memory Figure 14-1. External Bus Interface with Calibration Bus MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 278: Features
Single Master Mode is entered when EXTM=0 and MDIS=0 in the EBI_MCR. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 279 DATA pins will drive (for internal master cycles) the address value on the first clock of the cycle (while TS is asserted).The memory controller supports per-chip-select selection of multiplexing address/data through the BRx[AD_MUX] bit. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 280 0b000 12:27 ADDR[16:31] 0b001 GPIO[12:27] or 0b000 / DATA[16:31] / 0b100 FlexRay usage 0b010 ADDR[16:31] 28:43 DATA[0:15] 0b001 DATA[0:15] / 0b001 DATA[0:15] / 0b001 ADDR[16:31] ADDR[0:15] RD_WR 0b001 RD_WR 00b01 RD_WR 0b001 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 281: External Signal Description
ADDR[3:31] Address bus — BDIP Output Burst Data in Progress CLKOUT Output Clockout — CAL_CS[0:3] Output Calibration Chip Selects DATA[0:31] Data bus — Output Output Enable RD_WR Read_Write Transfer Acknowledge Transfer Start MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 282: Detailed Signal Descriptions
Section 14.5.1.3, Memory Controller with Support for Various Memory Types for details on chip-select operation. 14.3.2.5 DATA [0:31] — Data lines 0-31 The DATA[0:31] signals contain the data to be transferred for the current transaction. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 283 Write enables are used to enable program operations to a particular memory. These signals can also be used as byte enables for read and write operation by setting the WEBS bit in the appropriate Base Register. WE[0:3]/BE[0:3] are only asserted for chip-select accesses. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 284: Signal Output Buffer Enable Logic By Mode
14.4 Memory map/Register definition Table 14-4 shows the EBI registers. Table 14-4. EBI Address Map Address EBI_BASE (0xC3F8_4000) EBI Module Configuration Register (EBI_MCR) EBI_BASE+0x4 Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 285: Register Descriptions
IDLE). In those cases, the behavior is undefined. Exceptions that can be written while an EBI transaction is in progress: - All bits in EBI_TESR Section 14.6.1, Booting from external memory for related application information. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 286 A/D muxing with a 16-bit port, it is recommended to set D16_31 to 1. 1: DATA[16:31] signals are used for 16-bit port accesses 0: DATA[0:15] signals are used for 16-bit port accesses MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 287 DBM — Data Bus Mode The DBM bit controls whether the EBI is in 32-bit or 16-bit Data Bus Mode. 1: 16-bit Data Bus Mode is used 0: 32-bit Data Bus Mode is used MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 288 Table 14-6. EBI Transfer Error Status Register (EBI_TESR) Field Descriptions Name Description BMTF — Bus Monitor Timeout Flag BMTF This bit is set if the cycle was terminated by a bus monitor timeout. 1: Bus monitor timeout occurred 0: No error MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 289 This bit controls whether the bus monitor is enabled for internal to external bus cycles. The BME bit is ignored (treated as 0) for chip-select accesses with internal TA (SETA=0). 1: Enable bus monitor (for external TA accesses only) 0: Disable bus monitor MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 290 1: Address on Data Multiplexing Mode is enabled for this chip select. 0: Address on Data Multiplexing Mode is disabled for this chip select. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 291 1: Transfer Acknowledge (TA) is an input to the EBI, data phase will be terminated by an external device 0: Transfer Acknowledge (TA) is an output from the EBI, data phase will be terminated by the EBI MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 292 The appropriate CS signal does not assert unless the corresponding V-bit is set. 1: This bank is valid 0: This bank is not valid CAL_BR0-3 registers do not support burst operation. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 293 Base Register BA field for more details. Refer to the device-specific documentation to see which bits are tied off, if any, for a particular MCU. Tied-off bits can be read but not written. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 294 3-clock cycle wait states (4 clocks per data beat) CAL_BR0-3 registers do not support burst operation. #beats is the number of beats (4,8,16) determined by BL and PS bits in Base Register. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 295: Functional Description
(e.g., bank 0 is selected over bank 1). A match on a valid calibration chip-select register overrides a match on any non-calibration chip-select register, with CAL_CS0 having the highest priority. Thus the full priority of the chip-selects is: CAL_CS0,...,CAL_CS3,CS0,...,CS3. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 296 TA is used BSCY don’t care since external TA is used AD_MUX Address on Data multiplexing SETA Select external TA to terminate access MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 297 Each chip select can be configured (via the SETA bit) to have TA driven internally (by the EBI), or externally (by an external device). See Section 14.4.1.4, EBI Base Registers (EBI_BR0-EBI_BR3, EBI_CAL_BR0-3)” for more details on SETA bit usage. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 298 The Write/Byte Enable lines affected in a transaction for a 32-bit port (PS = 0) and a 16-bit port (PS=1) are shown in Table 14-11. Only Big Endian byte ordering is supported by the EBI. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 299 EBI_MCR. NOTE This feature must be disabled for multi-master systems. In those cases, one master is getting its clock source from the other master and needs it to stay valid continuously. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 300: External Bus Operations
The basic transfer protocol defines the sequence of actions that must occur on the external bus to perform a complete bus transaction. A simplified scheme of the basic transfer protocol is shown in Figure 14-8. ARBITRATION ADDRESS TRANSFER DATA TRANSFER TERMINATION Figure 14-8. Basic Transfer Protocol MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 301 Therefore, arbitration is not needed and is not shown in these diagrams. 14.5.2.4.1 Single beat read flow The handshakes for a single beat read cycle are illustrated in the following flow and timing diagrams. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 302 CS access & !SETA? asserts transfer acknowledge (TA) asserts transfer acknowledge (TA) receives data Figure 14-9. Basic Flow Diagram of a Single Beat Read Cycle MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 303 Figure 14-10. Single Beat 32-bit Read Cycle, CS Access, Zero Wait States CLKOUT ADDR[3:31] RD_WR BDIP DATA[0:31] Wait state DATA is valid CS[n] Figure 14-11. Single Beat 32-bit Read Cycle, CS Access, One Wait State MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 304 Figure 14-12. Single Beat 32-bit Read Cycle, Non-CS Access, Zero Wait States 14.5.2.4.2 Single beat write flow The handshakes for a single beat write cycle are illustrated in the following flow and timing diagrams. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 305 CS access & ! SETA? asserts transfer acknowledge (TA) asserts transfer acknowledge (TA) waits 1 clock stops driving data Figure 14-13. Basic Flow Diagram of a Single Beat Write Cycle MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 306 Figure 14-14. Single Beat 32-bit Write Cycle, CS Access, Zero Wait States CLKOUT ADDR[3:31] RD_WR BDIP DATA is valid DATA[0:31] Wait state CS[n] WE[0:3] Figure 14-15. Single Beat 32-bit Write Cycle, CS Access, One Wait State MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 307 TS assertion of the second access. See Section 14.5.2.8, Termination signals protocol for more details. The following diagrams show a few examples of back-to-back accesses on the external bus. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 308 Figure 14-17. Back-to-Back 32-bit Reads to the Same CS Bank CLKOUT ADDR[3:31] RD_WR BDIP DATA[0:31] DATA is valid DATA is valid CS[n] CS[y] Figure 14-18. Back-to-Back 32-bit Reads to Different CS Banks MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 309 External Bus Interface (EBI) CLKOUT ADDR[3:31] RD_WR BDIP DATA is valid DATA[0:31] DATA is valid Figure 14-19. Write After Read to the Same CS Bank MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 310 External Bus Interface (EBI) CLKOUT ADDR[3:31] RD_WR BDIP DATA is valid DATA is valid DATA[0:31] CS[n] Figure 14-20. Back-to-Back 32-bit Writes to the Same CS Bank MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 311 Figure 14-21. Read After Write to the Same CS Bank 14.5.2.5 Burst transfer The EBI supports wrapping 32-byte critical-doubleword-first burst transfers. Bursting is supported only for internally-requested cache-line size (32-byte) read accesses to external devices that use the chip selects MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 312 This case (of 2 external burst transfers being required) applies only to AMBA data bus width of 64 bits. Except for the special case of a 32-bit non-chip-select access in 16-bit data bus mode. See Section 14.5.2.9, Non-chip-select burst in 16-bit data bus mode. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 313 (TA) receives data assert BDIP next to last data beat? negate BDIP drives last data asserts transfer acknowledge (TA) receive last data Figure 14-22. Basic Flow Diagram of a Burst Read Cycle MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 314 TBDIP=0 in the appropriate EBI Base Register results in BDIP being asserted (SCY+1) cycles after the address transfer phase, and being held asserted throughout the cycle regardless of the wait MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 315 When using TBDIP=1, the BDIP behavior changes to toggle between every beat when BSCY is a non-zero value. Figure 14-26 shows an example of the TBDIP=1 timing for the same 4-beat burst shown in Figure 14-25. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 316 Non-Burstable Chip-Select Banks (BI=1) or Non-Chip-Select Access 1 beat 16-bit 1 beat 32-bit 1 beat 16-bit 1 beat 32-bit 1 beat 16-bit 1 beat 32-bit 1 beat 16-bit Burstable Chip-Select Banks (BI=0) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 317 32-byte write to a non-chip-select device using external TA, requiring eight 32-bit external transactions. Note that due to the use of external TA, RD_WR does not toggle MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 318 1st Address 0x10 (no carry) Masking Lower 4 Bits) 0x000 0x10 0x10 0x008 0x18 0x10 0x010 0x00 0x00 0x018 0x08 0x00 0x020 0x30 0x30 0x028 0x38 0x30 0x030 0x20 0x20 0x038 0x28 0x20 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 319 Figure 14-29. 32-Byte Read with B-T-B 16-Byte Bursts to 32-bit Port, Zero Wait States 14.5.2.6.4 Small access example #4: 64-bit read to 16-bit Port Figure 14-30 shows an example of a 64-bit read to a 16-bit port, requiring four 16-bit external transactions. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 320 EBI for request sizes not shown below is undefined. No error signal is asserted for these erroneous cases. Table 14-15. Transaction Sizes Supported by EBI # Bytes (internal master) # Bytes (external master) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 321 OP3, depending on the address of the access. • The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of the access. This can be seen in Figure 14-31. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 322 Table 14-17 lists the patterns of the data transfer for write cycles when accesses are initiated by the MCU. The bytes indicated as ‘—’ are not driven during that write cycle. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 323 1 cycle longer than required, as seen in Figure 14-33. However, the DATA does not need to be held 1 cycle longer by the slave, because the EBI latches DATA every cycle during non-chip-select accesses. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 324 (terminating the access) regardless of SCY. Table 14-18 summarizes how the EBI recognizes the termination signals provided from an external device. Table 14-18. Termination Signals Protocol Action Negated Negated No Termination MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 325 For this case, a special 2-beat burst protocol is used for reads and writes, so that a slave device (using the same EBI) can internally generate one 32-bit read or write access (thus 32-bit coherent), as opposed to two separate 16-bit accesses. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 326 16-bit data bus mode. CLKOUT ADDR[3:31] RD_WR BDIP TS (output) DATA[0:15] TA (input) DATA is valid Minimum DATA is valid 2 wait states Figure 14-34. 32-bit Read from MCU with DBM=1 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 327 Note that this figure is identical to Figure 14-18, except the CSy is replaced by CAL_CSy. Timing for other cases on calibration bus can similarly be derived from other figures in this document (by replacing CS with CAL_CS). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 328 AMBA AHB V6 specification. The EBI works under the assumption that all internal masters on the device do not produce any misaligned access cases (to the EBI) other than the ones below. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 329 For this case, the EBI internally treats HSIZE as 10 (4-byte access). Table 14-20 shows which external transfers are generated by the EBI for the misaligned access cases in Table 14-19, for each port size. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 330 Word @0x2,0xA 1100 0011 0011 0011 Word @0x3,0xB 1110 0001 1011 0011 0111 Word @0x5,0xD 1000 (2 AHB 0111 transfers) 1011 0011 0111 Word @0x6,0xE 1100 (2 AHB 0011 transfers) 0011 0011 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 331 When performing a small access read, as described in Section 14.5.2.6, Small accesses (Small port size and short burst length), with A/D multiplexing enabled for this access, the EBI inserts an idle clock cycle MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 332 DATA[16:31] (or DATA[0:15]) would be used for address and data on an external muxed device. ** Or DATA[0:15], based on D16_31 bit in EBI_MCR. Figure 14-37. Small access (32-bit read to 16-bit port) on Address/Data multiplexed bus MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 333: Initialization/Application Information
Burst Read operation to an SDR burst memory. Refer to Figure 14-14 for an example of the timing of a typical Single Write operation to SDR memory. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 334: Running With Asynchronous Memories
* Flash memories typically use one WE signal as shown, RAMs use 2 or 4 (16-bit or 32-bit) Figure 14-39. MCU Connected to Asynchronous Memory Figure 14-40 shows a timing diagram of a read operation to a 16-bit asynchronous memory using 3 wait states. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 335 16-bit asynchronous memory using 3 wait states. CLKOUT ADDR[3:31] WE[0:1] DATA[0:31] DATA is valid 3 Wait States Figure 14-40. Read Operation to Asynchronous Memory, Three Initial Wait States MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 336: Connecting An Mcu To Multiple Memories
Connecting an mcu to multiple memories The MCU can be connected to more than one memory at a time. Figure 14-42 shows an example of how two memories could be connected to one MCU. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 337: Ebi Operation With Reduced Pinout Mcus
Some MCUs with this EBI may not have all the pins described in this document pinned out for a particular package. Some of the most common pins to be removed are DATA[16:31] and arbitration pins (BB, BG, MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 338: Summary Of Differences From Mpc5Xx
Below is a summary list of the significant differences between this EBI and that of the MPC5xx parts. • No memory controller support for external masters — must configure each master in multi-master system to drive its own chip selects MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 339 — rationale: some internal registers must be accessed all 32 bits at once to function as expected • Added misaligned access support — rationale: some eSys cores require use of misaligned accesses for optimum performance MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 340 — rationale: new feature to reduce minimum pin count • Added support for using either half of data bus for 16-bit port transfers — rationale: helps A/D muxed usability, while maintaining backwards compatibility MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 341: Information Specific To This Device
® Interrupts implemented by the MCU are defined in the e200z4 Power Architecture Core Reference Manual, available on www.freescale.com. 15.2.1 Block diagram Figure 15-1 shows the details of the interrupt controller. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 342: Overview
Figure 15-2 shows a general diagram of INTC software vector mode. Table 15-1. Interrupt sources available Number of Interrupt Source (IRQs) Interrupts Available Software Watchdog SRAM error correction Flash error correction MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 343 IVPR and IVOR4. The interrupt exception handler reads the INTC_IACKR to determine the vector of the interrupt request source. Typical program flow for software vector mode is shown in Figure 15-3. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 344 It also provides 16 priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. The priority assigned to each interrupt source is programmable in the range 0 to 15, with 0 being the lowest and 15 being the highest priority. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 345: Features
In the software vector mode, there is a common interrupt exception handler address that is calculated by hardware as shown in Figure 15-5. The upper half of the interrupt vector prefix register (IVPR) is added to the offset contained in the external input interrupt vector offset register (IVOR4). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 346 However, disabling recognition of the external input before popping the LIFO eases the calculation of the maximum stack depth at the cost of postponing the servicing of the next interrupt request. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 347: External Signal Description
Refer to the Signals chapter for a list and number of the external interrupt pins. • Refer to the SIU chapter for more information on how to configure these pins. 15.4 Memory map and register definition Table 15-2 is the INTC memory map. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 348: Register Descriptions
(INTC_IACKR) are the same regardless of the size of the read. In either software or hardware vector mode, the size of a write to the INTC end-of-interrupt register (INTC_EOIR) does not affect the operation of the write. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 349 When the INTC end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the INTC_CPR’s PRI field. The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to Section 15.6.5, Priority ceiling protocol. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 350 LIFO, are the same regardless of the size of the read Reading the INTC_IACKR does not have side effects in hardware vector mode. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 351 When the VTES bit in the INTC Module Configuration Register (INTC_MCR) is asserted, INTVEC is shifted to the left one bit. Bit 29 is read as a ‘0’. VTBA1 is narrowed to 20 bits in width. Figure 15-10. INTC Interrupt Acknowledge Register (INTC_IACKR)—INTC_MCR[VTES] = 1 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 352 Writing a 1 to CLRn clears it. Writing a 0 to CLRn has no effect. If a 1 is written to a pair SETn and CLRn bits at the same time, CLRn is asserted, regardless of whether CLRn was asserted before the write. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 353 Although INTC_PSRn is 8-bits wide, you can use a single 16-bit or 32-bit access, provided that it does not cross a 32-bit boundary. NOTE Do not modify the PRI field in INTC_PSR when the IRQ is asserted. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 354: Functional Description
15-8. The Hardware Vector Mode Offset column lists the IRQ-specific offsets when using hardware vector mode. The Source column shows the C language syntax for the register bit label: module_register[bit]. Interrupt requests from the same module location are ORed together. The individual MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 355 Interrupt 8 0x0140 EDMA_IRQRL[INT09] eDMA channel Interrupt 9 0x0150 EDMA_IRQRL[INT10] eDMA channel Interrupt 10 0x0160 EDMA_IRQRL[INT11] eDMA channel Interrupt 11 0x0170 EDMA_IRQRL[INT12] eDMA channel Interrupt 12 0x0180 EDMA_IRQRL[INT13] eDMA channel Interrupt 13 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 356 SIU External Interrupt Flag 1 0x0300 SIU_EIISR[EIF2] SIU External Interrupt Flag 2 0x0310 SIU_EIISR[EIF3] SIU External Interrupt Flag 3 0x0320 SIU_EIISR[EIF15:EIF4] SIU External Interrupt Flags 15–4 eMIOS 0x0330 EMIOS_GFR[F0] eMIOS channel 0 Flag MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 357 Engine A Channel 7 Interrupt Status 0x04C0 ETPU_CISR_A[CIS8] eTPU Engine A Channel 8 Interrupt Status 0x04D0 ETPU_CISR_A[CIS9] eTPU Engine A Channel 9 Interrupt Status 0x04E0 ETPU_CISR_A[CIS10] eTPU Engine A Channel 10 Interrupt Status MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 358 FIFO 0 Pause Flag 0x0670 EQADC_FISR0[EOQF] eQADC command FIFO 0 command queue End of Queue Flag 0x0680 EQADC_FISR0[CFFF] eQADC Command FIFO 0 Fill Flag 0x0690 EQADC_FISR0[RFDF] eQADC Receive FIFO 0 Drain Flag MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 359 FIFO 5 Pause Flag 0x0800 EQADC_FISR5[EOQF] eQADC command FIFO 5 command queue End of Queue Flag 0x0810 EQADC_FISR5[CFFF] eQADC Command FIFO 5 Fill Flag 0x0820 EQADC_FISR5[RFDF] eQADC Receive FIFO 5 Drain Flag DSPI MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 360 DSPI_DSR[DPEF] 0x08E0 DSPI_DSR[EOQF] DSPI_D transmit FIFO End of Queue Flag 0x08F0 DSPI_DSR[TFFF] DSPI_D Transmit FIFO Fill Flag 0x0900 DSPI_DSR[TCF] DSPI_D Transfer Complete Flag 0x0910 DSPI_DSR[RFDF] DSPI_D Receive FIFO Drain Flag DSPI_DSR[DDIF] eSCI MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 361 LIN Status Register 2 Receive ESCIB_SR[LWAKE] Register Overflow ESCIB_SR[STO] ESCIB_SR[PBERR] ESCIB_SR[CERR] ESCIB_SR[CKERR] ESCIB_SR[FRC] ESCIB_SR[OVFL] 0x0960 Reserved Reserved 0x0970 Reserved Reserved FlexCAN_A and FlexCAN_C 0x0980 CANA_ESR[BOFF_INT] FLEXCAN_A Bus off Interrupt 0x0990 CANA_ESR[ERR_INT] FLEXCAN_A Error Interrupt MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 362 FLEXCAN_C Buffer 3 Interrupt 0x0B40 CANC_IFRL[BUF4] FLEXCAN_C Buffer 4 Interrupt 0x0B50 CANC_IFRL[BUF5] FLEXCAN_C Buffer 5 Interrupt 0x0B60 CANC_IFRL[BUF6] FLEXCAN_C Buffer 6 Interrupt 0x0B70 CANC_IFRL[BUF7] FLEXCAN_C Buffer 7 Interrupt 0x0B80 CANC_IFRL[BUF8] FLEXCAN_C Buffer 8 Interrupt MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 363 – 0x0D20 EDMA_ERRH[ERR63:ERR32] eDMA channel Error flags 63 0x0D30 EDMA_IRQRH[INT32] eDMA channel Interrupt 32 0x0D40 EDMA_IRQRH[INT33] eDMA channel Interrupt 33 0x0D50 EDMA_IRQRH[INT34] eDMA channel Interrupt 34 0x0D60 EDMA_IRQRH[INT35] eDMA channel Interrupt 35 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 364 Interrupt 60 0x0F00 EDMA_IRQRH[INT61] eDMA channel Interrupt 61 0x0F10 EDMA_IRQRH[INT62] eDMA channel Interrupt 62 0x0F20 EDMA_IRQRH[INT63] eDMA channel Interrupt 63 0x0F30 243–279 Reserved Reserved FlexCAN_B 0x1180 CANB_ESR[BOFF_INT] FLEXCAN_B Bus off Interrupt MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 365 PIT0 PIT[0] 0x12E0 PIT1 PIT[1] 0x12F0 PIT2 PIT[2] 0x1300 PIT3 PIT[3] 0x1310 0x1320 0x1330 ECSM_ESR[R1BC] Flash and SRAM single-bit ECC error correction ECSM_ESR[F1BC] – 0x1340 Reserved Reserved Flexray 0x15E0 GIFER[MIF] FlexRay MIF MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 366 DECFIL_B_Out Decimation B output (Drain) 0x1700 DECFIL_B_Err Decimation B Error 0x1710 369— Reserved Reserved Reaction Module – 0x1690 REACM_GE Reaction Channel Global Error – REACM[0] Reaction Channel 0 3Interrupt REACM[1] REACM[2] REACM[3] MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 367 Setting its enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the INTC as an interrupt event setting the flag bit. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 368: Priority Management
The priority arbitrator, selector, encoder, and comparator submodules shown in Figure 15-1 are used to compare the priority of the asserted interrupt requests to the current priority. If the priority of any asserted MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 369 The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in software vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode. The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 370: Details On Handshaking With Processor
This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog or epilog. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 371 The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is the same as in software vector mode. Refer to Section 15.5.3.1.2, End-of-interrupt exception handler. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 372: Initialization And Application Information
15.6.2 Interrupt exception handler These example interrupt exception handlers use Power Architecture assembly code. 15.6.2.1 Software vector mode interrupt_exception_handler: code to create stack frame, save working register, and save SRR0 and SRR1 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 373 4 instructions available, branch to continue interrupt_exception_handler_continuedx: code to create stack frame, save working register, and save SRR0 and SRR1 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 374: Isr, Rtos, And Task Hierarchy
Since the ISRs are outside the control of the RTOS, this ISR does not run unless called by another ISR or the interrupt exception handler, perhaps after executing another ISR. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 375: Order Of Execution
INTC_EOIR. ISR108 completes. Interrupt exception handler writes to INTC_EOIR. RTOS continues execution. ISR108 executes for peripheral interrupt request 100 because the first eight ISRs are for software configurable interrupt requests. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 376: Priority Ceiling Protocol
To prevent corrupting a coherent data block, use the following code to modify the PRI in INTC_CPR. Interrupts must be enabled before executing the following GetResource code sequence: GetResource: raise PRI mbar isync ReleaseResource: mbar lower PRI MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 377: Deadlines
(INTC_SSCIR0–INTC_SSCIR7). Writing a 1 to SETn causes a software configurable interrupt request. This software configurable interrupt request, which usually has a lower PRIn value in the INTC_PSRn, does not cause preemptive scheduling inefficiencies. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 378: Lowering Priority Within An Isr
For example, reading a specific register can clear the flag bits, and consequently their corresponding interrupt requests, too. This clearing as a side effect of servicing a peripheral interrupt request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 379: Examining Lifo Contents
INTC_CPR[PRI] onto the LIFO, therefore the LIFO contents cannot be restored in hardware vector mode. push_lifo: load stacked PRI value and store to INTC_CPR load INTC_IACKR if stacked PRI values are not depleted, branch to push_lifo MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 380 However, since the peripheral or software configurable interrupt requests are not cleared, the peripheral interrupt request to the processor re-asserts when INTC_CPR[PRI] is lower than the priorities of those peripheral or software configurable interrupt requests. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 381: Overview
— Allows selection of interrupt requests between external pins and DSPI — Allows selection of some eTPU inputs from external eTPU pins or deserialized output from the DSPI module — Allows selection of serialized data source for the DSPI MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 382: Modes Of Operation
SIU. The signals shown are external pins to the device. The SIU registers are accessed through the crossbar switch. Note that the Power-on Reset Detection block, Pad Interface/Pad Ring block, and Peripheral I/O Channels are external to the SIU. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 383: Signal Description
NMI_ GPIO[213] GPIO IRQ Inputs, IMUX Peripheral I/O Channels DSPI Signals, & eQADC Triggers Figure 16-1. SIU block diagram 16.5 Signal description Table 16-1 lists the external pins used by the SIU. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 384: Memory Map And Register Descriptions
16-388 SIU_BASE+0x8 Reserved SIU_BASE+0xC Reset Status Register (SIU_RSR) on page 16-390 SIU_BASE+0x10 System Reset Control Register (SIU_SRCR) on page 16-392 SIU_BASE+0x14 SIU External Interrupt Status Register (SIU_EISR) on page 16-393 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 385 SIU_BASE+0x904 External Interrupt IMUX Select Register (EIISR) on page 16-526 SIU_BASE+0x908 DSPI IMUX Select Register (DISR) on page 16-528 SIU_BASE+0x90C IMUX Select Register 3 (SIU_ISEL3) on page 16-530 SIU_BASE+0x910 – Reserved SIU_BASE+0x91F MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 386 Gaps exist in this memory space where I/O pins are not available in the specified package. The ETISR is sometimes referred to as ISEL0 The EIISR is sometimes referred to as ISEL1 The DISR is sometimes referred to as ISEL2 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 387: Mcu Id Register 2 (Siu_Midr2)
Indicates if Data Flash is present 1: Data Flash present 0: Data Flash not present 28–30 — Reserved for future enhancements Indicates if Data FlexRay is present 1: FlexRay present 0: FlexRay not present MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 388: Mcu Id Register (Siu_Midr)
Total flash memory size = (flash size 1) + (flash size 2) 16.6.3 MCU ID Register (SIU_MIDR) The MCU ID Register contains the part number and the package ID of the device. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 389 Minor MASKNUM [0–3] MCU minor mask number; the current value applies to revision 0 and will be updated for each mask revision Table 16-7. Memory size core dependency PARTNUM field z0, z1 z3, z4, z5 Reserved Reserved 128 KB 512 KB 256 KB 768 KB MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 390: Reset Status Register (Siu_Rsr)
The reset value of this bit is determined by the value latched on the associated pin at the negation of the last reset. The reset value of this bit is determined by the inverse of the value latched on the associated EVTO pin. Figure 16-4. Reset Status Register (SIU_RSR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 391 0: WKPCFG pin latched during the last reset was logical zero and weak pull down is the default setting. 17–2 — Reserved Auto Baud Rate 1: Auto Baud Rate Enabled. 0: Auto Baud Rate Disabled. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 392: System Reset Control Register (Siu_Srcr)
SIU_BASE + 0xE Reset Res. Reset = Unimplemented or Reserved This bit in the MPC5644A MCU has no effect as checkstop reset is not supported. Figure 16-5. System Reset Control Register (SIU_SRCR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 393: External Interrupt Status Register (Siu_Eisr)
This bit is set when a NMI interrupt occurs on the NMI input pin. 1: An NMI event has occurred on the NMI input 0: No NMI event has occurred on the NMI input MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 394: Dma/Interrupt Request Enable Register (Siu_Direr)
Request Flag bits cause assertion of the one interrupt request signal. SIU_BASE + 0x18 Reset Reset = Unimplemented or Reserved This bit is cleared only by a reset. Figure 16-7. DMA/Interrupt Request Enable Register (SIU_DIRER) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 395: Dma/Interrupt Request Select Register (Siu_Dirsr)
This bit selects between a DMA or interrupt request when an edge triggered event occurs on the corresponding IRQx input. 1: DMA request is selected (on this device these DMA connections do not exist, causing the interrupt to be inhibit) 0: Interrupt request is selected MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 396: Overrun Status Register (Siu_Osr)
SIU_OSR. If any Overrun Request Enable bit and the corresponding flag bit is set, the single combined overrun request from the SIU to the interrupt controller is asserted. SIU_BASE + 0x24 Reset Reset = Unimplemented or Reserved Figure 16-10. Overrun Request Enable Register (SIU_ORER) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 397: Irq Rising-Edge Event Enable Register (Siu_Ireer)
0: Rising edge event is disabled IREEx IRQ Rising-Edge Event Enable x This bit enables rising-edge triggered events on the corresponding IRQx input. 1: Rising edge event is enabled 0: Rising edge event is disabled MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 398: External Irq Falling-Edge Event Enable Register (Siu_Ifeer)
The External IRQ Digital Filter Register specifies the amount of digital filtering on the IRQ0 – IRQ15 inputs. The Digital Filter Length field specifies the number of system clocks that define the period of the digital filter. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 399: Irq Filtered Input Register (Siu_Ifir)
The MSB positions of the register correspond to NMI pins and the number of NMI pins are defined by a parameter. The LSB positions of the register corresponds to the IRQ pins and the number of IRQ pins is defined by a parameter. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 400: Pad Configuration Registers (Siu_Pcr)
Properties, for a definition of which I/O functions are available in each package. Table 16-18 lists and describes the fields contained in the PCRs. Not all fields appear in each PCR but each field has an identical function in each register where it resides. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 401 Controls output driver configuration for the pads. Either open drain or push/pull driver configurations can be selected. This feature applies to output pins only. 0 Disable open drain for the pad (push/pull driver enabled). 1 Enable open drain for the pad. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 402 0. Field bit ranges are the opposite—the least significant bit is referred to as bit 0. • Bit 0 is an example of a reserved field. It is read-only and always returns a value of 0. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 403 Register Bit Range = [4:5] Field Bit Range = [1:0] Register Address Bit Number Footnote Field Name SIU_BASE+0x40 Read values Write values WPE WPS Reset values Reset = Unimplemented or Reserved OBE bit is significant in GPIO Signal I/O direction. IBE bit is significant in GPIO “Signal”...
Page 404 GPI, set the IBE bit to one. When configured as CS[1] or ADDR[9], set the ODE bit to zero. See the EBI section for weak pull up settings when configured as CS[1]. Figure 16-17. Pad Configuration Register (SIU_PCR1) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 405 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 406 When configured as ADDR[12], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as ADDR[12] Figure 16-20. Pad Configuration Register (SIU_PCR8) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 407 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 408 When configured as ADDR[15], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as ADDR[15] Figure 16-23. Pad Configuration Register (SIU_PCR11) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 409 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 410 When configured as ADDR[18], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as ADDR[18] Figure 16-26. Pad Configuration Register (SIU_PCR14) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 411 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 412 When configured as ADDR[21] or DATA[21], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as ADDR[21] or DATA[21]. Figure 16-29. Pad Configuration Register (SIU_PCR17) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 413 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 414 When configured as ADDR[24] or DATA[24], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as ADDR[24] or DATA[24]. Figure 16-32. Pad Configuration Register (SIU_PCR20) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 415 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 416 When configured as ADDR[27] or DATA[27], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as ADDR[27] or DATA[27]. Figure 16-35. Pad Configuration Register (SIU_PCR23) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 417 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 418 When configured as ADDR[30], ADDR[6] or DATA[30], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as ADDR[30], ADDR[6] or DATA[30]. Figure 16-38. Pad Configuration Register (SIU_PCR26) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 419 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 420 When configured as DATA[1] or ADDR[17], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as DATA[1] or ADDR[17]. Figure 16-41. Pad Configuration Register (SIU_PCR29) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 421 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 422 When configured as DATA[4] or ADDR[20], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as DATA[4] or ADDR[20]. Figure 16-44. Pad Configuration Register (SIU_PCR32) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 423 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 424 When configured as DATA[7] or ADDR[23], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as DATA[7] or ADDR[23]. Figure 16-47. Pad Configuration Register (SIU_PCR35) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 425 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 426 When configured as DATA[10] or ADDR[26], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as DATA[10] or ADDR[26]. Figure 16-50. Pad Configuration Register (SIU_PCR38) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 427 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 428 When configured as DATA[13] or ADDR[29], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as DATA[13] or ADDR[29]. Figure 16-53. Pad Configuration Register (SIU_PCR41) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 429 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 430 When configured as RD_WR, the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as RD_WR. Figure 16-56. Pad Configuration Register (SIU_PCR62) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 431 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 432 When configured as WE[1]/BE[1], the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as WE[1]/BE[1]. Figure 16-59. Pad Configuration Register (SIU_PCR65) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 433 IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 434 When configured as TA and external master operation is enabled, the ODE bit should be set to zero. See the EBI section for weak pull up settings when configured as TA. Figure 16-62. Pad Configuration Register (SIU_PCR70) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 435 Figure 16-63. Pad Configuration Register (SIU_PCR75) Table 16-66. SIU_PCR75 PA values Signal Name Module Description PA value Primary MDO[4] Nexus Message data out O 0b01 ALT1 ETPU_A[2] eTPU eTPU channel 0b10 GPIO GPIO[75] GPIO 0b00 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 436 The ODE bit should be set to zero for MDO operation. The HYS bit has no effect on MDO operation. The WPE bit should be set to zero for MDO operation. Figure 16-65. Pad Configuration Register (SIU_PCR77) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 437 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 438 The WPE bit should be set to zero for MDO operation. Figure 16-68. Pad Configuration Register (SIU_PCR80) Table 16-71. SIU_PCR80 PA values Signal Name Module Description PA value Primary MDO[9] Nexus Message data out O 0b01 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 439 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 440 When configured as GPI, the IBE bit should be set to one. Figure 16-71. Pad Configuration Register (SIU_PCR83) Table 16-74. SIU_PCR83 PA values Signal Name Module Description PA value Primary CAN_A_TX FlexCAN FlexCAN transmit O 0b01 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 441 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 442 When configured as DSPI_C_PCS[4] or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. Setting the IBE bit to zero reduces power consumption. When configured as GPI, the IBE bit should be set to one. Figure 16-74. Pad Configuration Register (SIU_PCR86) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 443 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 444 GPDI register. For SCI loop back operation the IBE bit must be set to one. Setting the IBE bit to zero reduces power consumption. When configured as GPI, the IBE bit should be set to one. Figure 16-77. Pad Configuration Register (SIU_PCR89) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 445 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 446 When configured as GPI, the IBE bit should be set to one. Figure 16-80. Pad Configuration Register (SIU_PCR92) Table 16-83. SIU_PCR92 PA values Signal Name Module Description PA value Primary SCI_B_RX eSCI eSCI receive 0b01 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 447 Reset = Unimplemented or Reserved The SCKA function is not available on the MPC5644A. Do not select 0b01 or 0b11 for the PA field. When configured as GPO, the OBE bit should be set to one. When configured as DSPI_C_PCS[1] or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register.
Page 448 Reset = Unimplemented or Reserved The SINA function is not available on the MPC5644A. Do not select 0b01 or 0b11 for the PA field. When configured as GPO, the OBE bit should be set to one. When configured as DSPI_C_PCS[2] or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register.
Page 449 Reset = Unimplemented or Reserved The PCSA[0] function is not available on the MPC5644A. Do not select 0b01 or 0b11 for the PA field. When configured as GPO, the OBE bit should be set to one. When configured as DSPI_D_PCS[2] or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register.
Page 450 Reset = Unimplemented or Reserved The PCSA[1] function is not available on the MPC5644A MCU. Do not select 0b01 or 0b11 for the PA field. When configured as GPO, the OBE bit should be set to one. When configured as DSPI_B_PCS[2] or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register.
Page 451 Reset = Unimplemented or Reserved The PCSA[3] function is not available on the MPC5644A. Do not select 0b01 or 0b11 for the PA field. When configured as GPO, the OBE bit should be set to one. When configured as GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register.
Page 452 = Unimplemented or Reserved The PCSA[4] function is not available on the MPC5644A. Do not select 0b01 or 0b11 for the PA field. When configured as DSPI_D_SOUT, the OBE bit has no effect. When configured as GPO, the OBE bit should be set to one.
Page 453 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 454 GPI, the IBE bit should be set to one. Figure 16-92. Pad Configuration Register (SIU_PCR104) Table 16-95. SIU_PCR104 PA values Signal Name Module Description PA value Primary DSPI_B_SOUT DSPI Output 0b01 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 455 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 456 GPI, the IBE bit should be set to one. Figure 16-95. Pad Configuration Register (SIU_PCR107) Table 16-98. SIU_PCR107 PA values Signal Name Module Description PA value Primary DSPI_B_PCS[2] DSPI Chip select 0b01 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 457 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 458 GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. Setting the IBE bit to zero reduces power consumption. When configured as GPI, the IBE bit should be set to one. Figure 16-98. Pad Configuration Register (SIU_PCR110) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 459 16.6.15.78 Pad Configuration Register 114–125 (SIU_PCR114–SIU_PCR125) The SIU_PCR114 – SIU_PCR125 registers control the pin function, direction, and static electrical attributes of the ETPUA0 – ETPUA11 pins, which host the ETPU_A[0:11], ETPU_A[12:23] and GPIO[114:125] signals. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 460 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 461 ETPU_A[14] or when ETPU_A[2] or GPIO[116] are configured as outputs, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. The weak pull up/down selection at reset for the ETPU_A[2] pin is determined by the WKPCFG pin. Figure 16-102. Pad Configuration Register (SIU_PCR116) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 462 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 463 ETPU_A[17] or when ETPU_A[5] or GPIO[119] are configured as outputs, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. The weak pull up/down selection at reset for the ETPU_A[5] pin is determined by the WKPCFG pin. Figure 16-105. Pad Configuration Register (SIU_PCR119) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 464 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 465 ETPU_A[20] or when ETPU_A[8] or GPIO[122] are configured as outputs, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. The weak pull up/down selection at reset for the ETPU_A[8] pin is determined by the WKPCFG pin. Figure 16-108. Pad Configuration Register (SIU_PCR122) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 466 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 467 GPDI register. The weak pull up/down selection at reset for the ETPU_A[11] pin is determined by the WKPCFG pin. Figure 16-111. Pad Configuration Register (SIU_PCR125) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 468 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 469 The weak pull up/down selection at reset for the ETPU_A[14] pin is determined by the WKPCFG pin. Figure 16-114. Pad Configuration Register (SIU_PCR128) Table 16-117. SIU_PCR128 PA values Signal Name Module Description PA value Primary ETPU_A[14] eTPU eTPU channel 0b0001 ALT1 DSPI_B_PCS[4] DSPI Chip select 0b0010 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 470 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 471 ETPUA or GPO outputs, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. The weak pull up/down selection at reset for the ETPU_A[17] pin is determined by the WKPCFG pin. Figure 16-117. Pad Configuration Register (SIU_PCR131) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 472 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 473 ETPU_A[20] and GPIO[134] when configured as inputs. The weak pull up/down selection at reset for the ETPU_A[20] pin is determined by the WKPCFG pin. Figure 16-120. Pad Configuration Register (SIU_PCR134) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 474 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 475 ETPU_A[23] and GPIO[137] when configured as inputs. The weak pull up/down selection at reset for the ETPU_A[23] pin is determined by the WKPCFG pin. Figure 16-123. Pad Configuration Register (SIU_PCR137) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 476 IBE and OBE bits are ignored. The eTPU function controlled by this register has an additional dependency on the SIU_ISEL8 register settings. Please see Section 16.6.22, IMUX Select Register 8 (SIU_ISEL8), for more detail. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 477 ETPU_A[26] and GPIO[140] when configured as inputs. The weak pull up/down selection at reset for the ETPU_A[26] pin is determined by the WKPCFG pin. Figure 16-126. Pad Configuration Register (SIU_PCR140) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 478 IBE and OBE bits are ignored. The eTPU function controlled by this register has an additional dependency on the SIU_ISEL8 register settings. Please see Section 16.6.22, IMUX Select Register 8 (SIU_ISEL8), for more detail. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 479 Setting the IBE bit to zero reduces power consumption. The IBE bit must be set to one for GPIO when configured as input. The weak pull up/down selection at reset for the ETPU_A[29] pin is determined by the WKPCFG pin. Figure 16-129. Pad Configuration Register (SIU_PCR143) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 480 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 481 Setting the IBE bit to zero reduces power consumption. The IBE bit must be set to one for both EMIOS[0] and GPIO[179] when configured as inputs. Figure 16-132. Pad Configuration Register (SIU_PCR179) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 482 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 483 Setting the IBE bit to zero reduces power consumption. The IBE bit must be set to one for both EMIOS[3] and GPIO[182] when configured as inputs. The weak pull up/down selection at reset for the EMIOS[3] pin is determined by the WKPCFG pin. Figure 16-135. Pad Configuration Register (SIU_PCR182) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 484 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 485 Setting the IBE bit to zero reduces power consumption. The IBE bit must be set to one for both EMIOS[6] and GPIO[185] when configured as inputs. Figure 16-138. Pad Configuration Register (SIU_PCR185) Table 16-141. SIU_PCR185 PA values Signal Name Module Description PA value Primary EMIOS[6] eMIOS eMIOS channel 0b01 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 486 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 487 GPIO[188] when configured as inputs. Figure 16-141. Pad Configuration Register (SIU_PCR188) Table 16-144. SIU_PCR188 PA values Signal Name Module Description PA value Primary EMIOS[9] eMIOS eMIOS channel 0b001 ALT1 ETPU_A[9] eTPU eTPU channel 0b010 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 488 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 489 GPDI register. Setting the IBE bit to zero reduces power consumption. The IBE bit must be set to one for GPIO[191] when configured as an input. The weak pull up/down selection at reset for the EMIOS[12] pin is determined by the WKPCFG pin. Figure 16-144. Pad Configuration Register (SIU_PCR191) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 490 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 491 GPDI register. Setting the IBE bit to zero reduces power consumption. The IBE bit must be set to one for GPIO[194] when configured as inputs. Figure 16-147. Pad Configuration Register (SIU_PCR194) Table 16-150. SIU_PCR194 PA values Signal Name Module Description PA value Primary EMIOS[15] eMIOS eMIOS channel 0b01 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 492 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 493 In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 494 Setting the IBE bit to zero reduces power consumption. The IBE bit must be set to one for both EMIOS[20] and GPIO[199] when configured as inputs. The weak pull up/down selection at reset for the EMIOS[20] pin is determined by the WKPCFG pin. Figure 16-152. Pad Configuration Register (SIU_PCR199) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 495 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 496 In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 497 When configured as EMIOS or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. Setting the IBE bit to zero reduces power consumption. When configured as GPI, the IBE bit should be set to one. Figure 16-157. Pad Configuration Register (SIU_PCR204) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 498 When configured as GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. When configured as GPI, the IBE bit should be set to one. Setting the IBE bit to zero reduces power consumption. Figure 16-159. Pad Configuration Register (SIU_PCR207) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 499 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 500 When configured as GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. When configured as GPI, the IBE bit should be set to one. Figure 16-162. Pad Configuration Register (SIU_PCR210) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 501 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 502 When configured as GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. When configured as GPI, the IBE bit should be set to one. Figure 16-165. Pad Configuration Register (SIU_PCR213) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 503 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 504 Table 16-171. SIU_PCR216 PA values Signal Name Module Description PA value Primary AN[13] eQADC Analog input 0b0001 ALT1 MA[1] eQADC Mux address 0b0010 ALT2 ETPU_A[21] eTPU eTPU channel 0b0100 GPIO eQADC Serial data output O 0b0000 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 505 Input and output buffers are enabled/disabled based on PA selection. Both input and output buffer disabled for AN[15] function. Output buffer only enabled for FCK and ETPU functions. Figure 16-170. Pad Configuration Register (SIU_PCR218) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 506 Enables the pad as an output and drives the output buffer enable signal. 0 Disable output buffer for the pad. 1 Enable output buffer for the pad is enabled. Note: This field affects only the GPIO[219] pin. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 507 Refer to the electrical specifications for this information. 00 Minimum slew rate 01 Medium slew rate 10 Invalid value 11 Maximum slew rate Note: This field affects only the GPIO[219] pin. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 508 16.6.15.139Pad Configuration Register 220 (SIU_PCR220) SIU_BASE+0x1F8 Reset = Unimplemented or Reserved Figure 16-172. Pad Configuration Register (SIU_PCR220) Table 16-175. SIU_PCR220 PA values Signal Name Module Description PA value Primary MDO0 Nexus Nexus message data out — MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 509 16.6.15.142Pad Configuration Register 223 (SIU_PCR223) SIU_BASE+0x1FE Reset = Unimplemented or Reserved Figure 16-175. Pad Configuration Register (SIU_PCR223) Table 16-178. SIU_PCR223 PA values Signal Name Module Description PA value Primary MDO3 Nexus Nexus message data out — MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 510 16.6.15.145Pad Configuration Register 226 (SIU_PCR226) SIU_BASE+0x204 Reset = Unimplemented or Reserved Figure 16-178. Pad Configuration Register (SIU_PCR226) Table 16-181. SIU_PCR226 PA values Signal Name Module Description PA value Primary Nexus Read/write ready O — MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 511 CLKOUT pin is enabled and disabled by setting and clearing the OBE bit. The CLKOUT pin is enabled during reset. SIU_BASE+0x20A Reset = Unimplemented or Reserved CLKOUT pin is enabled and disabled by setting and clearing the OBE bit. Figure 16-181. Pad Configuration Register (SIU_PCR229) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 512 16.6.15.150Pad Configuration Register 231 (SIU_PCR231) SIU_BASE+0x20E Reset = Unimplemented or Reserved Figure 16-183. Pad Configuration Register (SIU_PCR231) Table 16-186. SIU_PCR231 PA values Signal Name Module Description PA value Primary EVTI Nexus Nexus event in — MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 513 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 514 16.6.15.154Pad Configuration Register 336 (SIU_PCR336) SIU_BASE+0x2E0 Reset = Unimplemented or Reserved Figure 16-187. Pad Configuration Register (SIU_PCR336) Table 16-190. SIU_PCR336 PA values Signal Name Module Description PA value Primary CAL_CS0 Calibration bus Calibration chip select — MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 515 Set IBE = 1 for input or OBE = 1 for output. For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits are ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 516 Calibration bus. SIU_BASE+0x2EA Reset = Unimplemented or Reserved Figure 16-191. Pad Configuration Register (SIU_PCR341) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 517 = Unimplemented or Reserved Figure 16-193. Pad Configuration Register (SIU_PCR343) Table 16-196. SIU_PCR343 PA values Signal Name Module Description PA value Primary CAL_TS Calibration bus Calibration transfer start ALT1 CAL_ALE Calibration bus Address Latch Enabl MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 518 SIU_PCR351 0x2FE DSPI_B -DSI1 ETPU_A_22 — EMIOS_10 GPIO351 SIU_PCR352 0x300 DSPI_B -DSI2 ETPU_A_21 — EMIOS_9 GPIO352 SIU_PCR353 0x302 DSPI_B -DSI3 ETPU_A_20 — EMIOS_8 GPIO353 SIU_PCR354 0x304 DSPI_B -DSI4 ETPU_A_19 — EMIOS_6 GPIO354 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 519 GPIO381 16.6.15.163Pad Configuration Register 382 – 389 (SIU_PCR382 – SIU_PCR389) The SIU_PCR382 – SIU_PCR389 registers control the muxing of the signals to the DSPI. PA field values are shown in Table 16-199. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 520 SIU_BASE 0b001 0b100 0b010 0b000 SIU_PCR 390 0x34C DSPI_C -DSI8 ETPU_A_4 — EMIOS_3 GPIO390 SIU_PCR 391 0x34E DSPI_C -DSI9 ETPU_A_5 — EMIOS_4 GPIO391 SIU_PCR 392 0x350 DSPI_C -DSI10 ETPU_A_6 — EMIOS_5 GPIO392 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 521: Gpio Pin Data Output Registers (Siu_Gpdo0_3 – Siu_Gpdo412_413)
GPIO pins is changed from input to output. Writes to the SIU_GPDOx_x registers have no effect on the state of the corresponding pins when the pins are configured for their primary function by the corresponding PCR. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 522: Gpio Pin Data Input Registers (Siu_Gpdi0_3 – Siu_Gpdi_232)
The definition of the SIU_GPDIx_x registers is given in Figure 16-200 Figure 16-201. Each of the GPDI bits corresponds to the pin with the same GPIO pin number. For example, GPDI0 is the pin data MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 523: Eqadc Trigger Input Select Register (Siu_Etisr)
CFIFO4, and so on. Additionally, each SIU_ETISR field offers selection among a group of signals using the corresponding field in the SIU_ISEL3 register. 1. The ETISR is sometimes referred to as ISEL0 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 524 GPIO[207] signal or, by assigning a value of 0b00 to the TSEL5 field, a variety of other signals can be selected using the eTSEL5 field of the SIU_ISEL3 register. SIU_BASE+0x900 TSEL5 TSEL4 TSEL3 TSEL2 TSEL1 TSEL0 Reset Reset = Unimplemented or Reserved Figure 16-203. eQADC Trigger Input Select Register (SIU_ETISR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 525 11 ETRIG[1] pin 10:11 eQADC Trigger Input Select 0. The eQADC trigger 0 input is as follows: TSEL0 00 eTSEL0 (described in SIU_ISEL3) 01 eTPU_A[30] channel 10 eMIOS[10] channel 11 ETRIG[0] pin 12:31 Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 526: External Irq Input Select Register (Siu_Eiisr)
External IRQ Input Select 11. IRQ[11] input is specified by ESEL11 as follows: ESEL11 00 IRQ[11] pin 01 DSPI_B[11] deserialized output 10 DSPI_C[12] deserialized output 11 DSPI_D[13] deserialized output 1.The EIISR is sometimes referred to as ISEL1 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 527 18:19 External IRQ Input Select 6. IRQ[6] is multiplexed on the TCRCLK_B pin, which is not available in any ESEL6 of the MPC5644A packages. IRQ[6] input is specified by ESEL6 as follows: 00 IRQ[6] pin 01 DSPI_B[6] deserialized output 10 DSPI_C[7] deserialized output...
Page 528: Dspi Input Select Register (Siu_Disr)
DSPI_B Slave Select Input Select. The source of the slave select input of DSPI_B is specified by SSSELB SSSELB as follows: 00 DSPI_B_PCS[0] pin 01 Reserved 10 DSPI_C_PCS[0] (Master) 11 DSPI_D_PCS[0] (Master) 1.The DISR is sometimes referred to as ISEL2 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 529 DSPI_D Slave Select Input Select. The source of the slave select input of DSPI_D is specified by SSSELD SSSELD as follows: 00 DSPI_D_PCS[0] pin 01 Reserved 10 DSPI_B_PCS[0] (Master) 11 DSPI_C_PCS[0] (Master) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 530: Imux Select Register 3 (Siu_Isel3)
Table 16-206. eQADC queue0 enhanced trigger selection eTSEL0 eQADC enhanced trigger input GPIO206 (eTRIG0) RTI Trigger PIT0 Trigger PIT1 Trigger PIT2 Trigger MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 531 AND PIT2 eMIOS10 AND PIT3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved eMIOS23 Table 16-207. eQADC queue1 enhanced trigger selection eTSEL1 eQADC enhanced trigger input GPIO207 (eTRIG1) RTI Trigger PIT0 Trigger MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 532 AND PIT0 eTPU31 AND PIT1 Reserved Reserved eTPU28 eTPU29 eTPU30 eTPU31 Reserved Reserved Reserved Reserved eMIOS11 AND PIT2 eMIOS11 AND PIT3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved eMIOS23 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 533 AND PIT0 eTPU30 AND PIT1 Reserved Reserved eTPU28 eTPU29 eTPU30 eTPU31 Reserved Reserved Reserved Reserved eMIOS10 AND PIT2 eMIOS10 AND PIT3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved eMIOS23 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 534 AND PIT0 eTPU30 AND PIT1 Reserved Reserved eTPU28 eTPU29 eTPU30 eTPU31 Reserved Reserved Reserved Reserved eMIOS10 AND PIT2 eMIOS10 AND PIT3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved eMIOS23 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 535 AND PIT0 eTPU30 AND PIT1 Reserved Reserved eTPU28 eTPU29 eTPU30 eTPU31 Reserved Reserved Reserved Reserved eMIOS10 AND PIT2 eMIOS10 AND PIT3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved eMIOS23 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 536 AND PIT0 eTPU30 AND PIT1 Reserved Reserved eTPU28 eTPU29 eTPU30 eTPU31 Reserved Reserved Reserved Reserved eMIOS10 AND PIT2 eMIOS10 AND PIT3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved eMIOS23 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 537: Imux Select Register 8 (Siu_Isel8)
ESEL2 0 DSPI_B[11] deserialized output 1 eTPU channel 26 24:26 Reserved eTPU input channel connected as follows: ESEL1 0 DSPI_B[12] deserialized output 1 eTPU channel 25 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 538: Imux Select Register 9 (Siu_Isel9)
Figure 16-208. IMUX Select Register 9 (SIU_ISEL9) Table 16-213. eQADC advance trigger selection eTSEL0A eQADC enhanced trigger input Reserved RTI Trigger PIT0 Trigger PIT1 Trigger PIT2 Trigger PIT3 Trigger Reserved Reserved eTPU30 AND PIT0 eTPU30 AND PIT1 Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 539: Imux Select Register 10 (Siu_Isel10)
16.6.24 IMUX Select Register 10 (SIU_ISEL10) The IMUX Select Register 10 (SIU_ISEL10) register contains bit fields that specify which eTPU output is connected to the decimation filter Integrator halt signal (HSELx) and Integrator reset signal MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 540 Table 16-214. Decimation filter control source selection Field Code Source ZSELA eTPU[22] eTPU[23] eTPU[24] eTPU[25] Others Unused HSELA eTPU[22] eTPU[23] eTPU[24] eTPU[25] Others Unused ZSELB eTPU[22] eTPU[23] eTPU[24] eTPU[25] Others Unused HSELB eTPU[22] eTPU[23] eTPU[24] eTPU[25] Others Unused MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 541: Chip Configuration Register (Siu_Ccr)
Those reflections always are suppressed. Furthermore, the suppression of reflections from the non-calibration bus onto the calibration bus is not enabled by CRSE. Those reflections are also always suppressed. 0 Calibration reflection suppression is disabled 1 Calibration reflection suppression is enabled Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 542: External Clock Control Register (Siu_Eccr)
Note: The EBTS bit must not be modified while an external bus transaction is in progress. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 543: Compare A High Register (Siu_Carh)
The SIU_CARL register holds the 32-bit value that is compared against the value in the SIU_CBRL register. The CMPAL field is read/write and is reset by the IP Green-Line synchronous reset signal. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 544: Compare B High Register (Siu_Cbrh)
The SIU_CBRL register holds the 32-bit value that is compared against the value in the SIU_CARL register. The CMPBL field is read/write and is reset by the IP Green-Line synchronous reset signal. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 545: System Clock Register (Siu_Sysdiv)
0 When CAN_CTRL[CLK_SRC] = 1, FlexCAN runs at the system frequency Section 5.3.3.4, Support for CAN interface operation. 16:26 Reserved Bypass bit BYPASS 1 System clock divider is bypassed 0 System clock divider is not bypassed MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 546: Halt Register (Siu_Hlt)
SIU_HLT is set and a WAIT instruction is executed. The CPU exits stop mode upon reception of any interrupt request. SIU_BASE + 0x9A4 Reset Reset = Unimplemented or Reserved Figure 16-217. Halt Register (SIU_HLT) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 547 1: Stop mode request 0: Normal operation Reserved PIT stop request PITSTP When asserted, a stop request is sent to the periodic interrupt timer module. 1: Stop mode request 0: Normal operation 14:16 Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 548: Halt Acknowledge Register (Siu_Hltack)
The bits in the SIU_HLTACK register indicate that the module requested to halt via the SIU_HLT register has completed the halt process and has entered a halted state with the module clocks disabled. This register is read-only. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 549 0: Normal operation EBI stop acknowledge When asserted, indicates that a stop acknowledge was received from the external bus controller which handles the calibration interface. EBIACK 1: Stop mode request 0: Normal operation MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 550 1: Stop mode request 0: Normal operation DSPI C stop acknowledge When asserted, indicates that a stop acknowledge was received from the DSPI C. SPICACK 1: Stop mode request 0: Normal operation MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 551: Core Mmu Pid Control Register (Siu_Empcr0)
Synchronization is implemented using Watchpoint Event 2 output in the processor core. The mechanism is detailed in Figure 16-219 Table 16-220. See application note AN4030 for more detail. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 552: Functional Description
1: When the PID remapping is enabled (EXT_PID_EN = 1), the processor MMU’s PID register bit 7 is logic 1. 16.7 Functional description The following sections provide an overview of the SIU operation features. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 553: System Configuration
System configuration 16.7.1.1 Boot configuration Two BOOTCFG signals are implemented in MPC5644A MCUs. The BAM program uses the BOOTCFG0 bit to determine where to read the reset configuration word, and whether to initiate a FlexCAN or eSCI boot. See Section 4.7.1, Reset configuration half word (RCHW), for details on the RCHW.
Page 554 When WKPCFG_NMI_GPIO213 is enabled as NMI, the pin will override the PCR configuration after reset. The SIU_DIRER selects between critical and non-maskable interrupt use, the SIU_EISR reports the status of NMI, and the SIU_IFEER selects edge sensitivity of the NMI input. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 555: Gpio Operation
Pin Configuration Register in the SIU where the GPIO function is selected for the pin. In addition, each device pin with GPIO functionality has an input data register (SIU_GPDIx_x) and an output data register (SIU_GPDOx_x). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 556: Internal Multiplexing
16-222. As shown in the figure, the IRQ[0] input of the SIU can be connected to either the eMIOS[14]_IRQ[0]_eTPU_A[29]_GPIO[193] pin, the DSPI_B[0] deserialized output signal, the DSPI_C[1] deserialized output signal or eMIOS[14] channel. The remaining IRQ inputs are 1. The EIISR is sometimes referred to as ISEL1. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 557 When SIU_ISEL8 is in its default state, the eTPU[29:24] will not be connected to their respective output pin, irrespective of the SIU_PCR[PA] field. The SIU_ISEL8 register must be modified if these signals are to be used as external inputs or outputs. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 558 System Integration Unit (SIU) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 559: Information Specific To This Device
FMPLL_ESYNCR1[EPREDIV] 0b1111 inhibit the clock to the phase detector FMPLL_ESYNCR1[EMFD] 0b0100000 divide-by-32 FMPLL_ESYNCR2[ERFD] 0b11 divide-by-16 17.2 Introduction This chapter describes the features and functions of the FMPLL module. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 560: Overview
2 normal modes: crystal or external reference • Programmable frequency modulation — Triangle wave modulation — Register programmable modulation frequency and depth 1. See Section 17.1, Information specific to this device, for information on crystal frequencies supported. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 561: Modes Of Operation
Clock Quality Monitor (CQM) will inhibit the system clock and keep system reset asserted while the crystal oscillator has not stabilized. The PLLREF input must be kept stable during the whole period while system reset is asserted. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 562: External Signal Description
EXTAL pin, rather than a crystal oscillator. The input frequency range is the same and frequency modulation is available. 17.3 External signal description Table 17-3 lists external signals used by the FMPLL during normal operation. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 563: Detailed Signal Descriptions
This section provides the memory map and detailed descriptions of all registers of the FMPLL. 17.4.1 Memory map Table 17-5 shows the memory map. Addresses are given as offsets of the module base address. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 564: Register Descriptions
After it is set to ‘1’, further write attempts to this bit will have no effect. 17.4.2.1 Synthesizer Control Register (SYNCR) This register is provided for backwards compatibility with previous devices. New applications should use ESYNCR1/ESYNCR2 instead of SYNCR. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 565 000xx Invalid 00100 Divide by 8 00101 Divide by 9 00110 Divide by 10 10011 Divide by 23 10100 Divide by 24 10101 Invalid 1011x Invalid 11xxx Invalid Reserved, should be cleared. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 566 Therefore, LOCIRQ has no effect in bypass mode. See Section 17.5.4.3, Loss-of-clock interrupt request. 0 Ignore loss-of-clock. Interrupt not requested. 1 Enable interrupt request upon loss-of-clock. 19–31 Reserved, should be cleared. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 567 FMPLL is in bypass mode (because, in bypass, the VCO clock is not monitored and a loss-of-clock on the reference clock causes reset). See Section 17.5.4, Loss-of-clock detection. 0 No loss-of-clock detected. Clocks are operating normally. 1 Loss-of-clock detected. Clocks are not operating normally. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 568 EMFD or CLKCFG[1:2] are changed in enhanced mode, and then asserted again when the PLL regains lock. If operating in bypass mode, the LOCK bit is still asserted or negated when the FMPLL acquires or loses lock. 0 FMPLL is unlocked. 1 FMPLL is locked. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 569 Enhanced Synthesizer Control Register 1 (ESYNCR1) Offset 0x0008 Access: User read/write CLKCFG EPREDIV Reset – EMFD Reset Reset value determined by the PLLREF pin. Figure 17-4. Enhanced Synthesizer Control Register 1 (ESYNCR1) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 570 0111 Divide by 8 1000 Divide by 9 1001 Divide by 10 1010 Divide by 11 1011 Divide by 12 1100 Divide by 13 1101 Divide by 14 1110 Divide by 15 1111 Clock inhibit MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 571 In bypass mode, the loss-of-clock function is always enabled, regardless of the state of the LOCEN bit. Furthermore, the LOCEN bit has no effect on the loss-of-lock detection circuitry. 0 Loss of clock disabled 1 Loss of clock enabled MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 572 FMPLL is locked. Writing to this register while the FMPLL is unlocked has no effect. Furthermore, when the PLL loses lock, frequency modulation is disabled and the FMPLL_SYNFMMR is reset. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 573 This 13-bit field is the binary equivalent of the modperiod variable derived from the formula: modperiod round ------------------  where f represents the frequency of the feedback divider, and f represents the modulation frequency. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 574: Functional Description
In legacy mode, the relationship between the output frequency f and input frequency f is determined by the PREDIV, MFD and RFD values programmed in the FMPLL_SYNCR, according to the following equation: Eqn. 17-1  ------------------------------------------------------ -    PREDIV MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 575 1. Note that changing only the CLKCFG[0] bit to move from bypass to normal or vice-versa, and keeping the values of the other FMPLL_ESYNCR1 fields unchanged, will not cause the PLL to lose lock or the lock flag to be cleared. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 576: Lock Detection
Additionally, the user may select to have the system enter reset, assert an interrupt request, or do nothing if/when the FMPLL reports this condition. 1. See Section 17.1, Information specific to this device, for information on crystal frequencies supported. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 577 If the reference fails in normal mode, then no backup clock selection occurs, and the FMPLL output continues to be the system clock. If the reference stops, the FMPLL will operate in free-running mode. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 578 LOCEN and LOCIRQ have no effect in bypass mode. If the reference fails in bypass mode with crystal reference, a system reset is asserted instead of an interrupt request. If the reference fails in bypass with MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 579: Frequency Modulation
MODPERIOD and INCSTEP fields of the FMPLL_SYNFMMR. = PLL nominal frequency MD = Modulation depth percentage Center Spread Down Spread 2 x MD Figure 17-8. Triangular frequency modulation MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 580 The FM parameters can only be changed, and FM can only be enabled, when the PLL is locked. Writing to the FMPLL_SYNFMMR while the PLL is unlocked has no effect. Furthermore, when the PLL loses MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 581 FM parameters have already propagated to the analog circuitry. Therefore, the sequence for programming FM is: 1. Poll FMPLL_SYNSR[LOCK] until it asserts. 2. Program the MODSEL, MODPERIOD and INCSTEP fields of the FMPLL_SYNFMMR. 3. Poll FMPLL_SYNFMMR[BSY] until it negates. 4. Assert FMPLL_SYNFMMR[MODEN]. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 582 Frequency-modulated phase locked loop (FMPLL) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 583: Overview
Miscellaneous Reset Status Register (ECSM_MRSR) 0x10 Reserved Miscellaneous Wakeup Control Register (ECSM_MWCR) 0x14 Reserved 0x18 Reserved 0x1C Reserved 0x20 Reserved 0x24 Miscellaneous User-Defined Control Register (ECSM_MUDCR) 0x28 Reserved 0x2C – 0x3C Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 584: Register Descriptions
Only one bit is set at any time in the ECSM_MRSR, reflecting the cause of the most recent reset as signalled by device reset input signals. The ECSM_MRSR can only be read from the IPS programming model. Any attempted write is ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 585: Miscellaneous Wakeup Control Register (Ecsm_Mwcr)
4. Once the appropriately-high interrupt request level arrives, the interrupt controller signals its presence, and the ECSM responds by asserting an “exit_low_power_mode” signal. 5. The external logic senses the assertion of the “exit” signal, and re-enables the appropriate clock signals. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 586: Miscellaneous User-Defined Control Register (Ecsm_Mudcr)
The ECSM_MUDCR is used to specify the number of additional wait states required for the device SRAM. Please see the device data sheet for details on the cut-off frequency for the addition of 1 wait state. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 587: Ecc Registers
Flash ECC Attributes Register (ECSM_FEAT) • Flash ECC Data Register (ECSM_FEDR) • RAM ECC Address Register (ECSM_REAR) • RAM ECC Syndrome Register (ECSM_PRESR) • RAM ECC Master Number Register (ECSM_REMR) • RAM ECC Attributes Register (ECSM_REAT) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 588 In many cases, this error termination is reported directly by the initiating bus master. However, there are certain situations where the occurrence of this type of MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 589 The occurrence of a non-correctable multi-bit flash error generates an ECSM ECC interrupt request as signalled by the assertion of ECSM_ESR[FNCE]. The faulting address, attributes and data are also captured in the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 590 3. Re-read the ECSM_ESR and verify the current contents matches the original contents. If the two values are different, go back to step 1 and repeat. 4. When the values are identical, write a ‘1’ to the asserted ESR flag to negate the interrupt request. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 591 ECSM_FEAT and ECSM_FEDR registers. To clear this interrupt flag, write a ‘1’ to this bit. Writing a ‘0’ has no effect. In the event that multiple status flags are signaled simultaneously, the ECSM records the event with the R1BC as highest priority, then F1BC, then RNCE, and finally FNCE. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 592 Register address: ECSM Base + 0x004A (0xFFF4_004A) ERRBIT[6:0] Reset = Unimplemented Figure 18-6. ECC Error Generation Register (ECSM_EEGR) This field is writable only in test mode in cut 1.0 devices. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 593 The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 594 ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM. After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly re-enable the error generation logic. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 595 ECSM_EEGR[FRC1NCI]) and ECSM_EEGR[ERRBIT] equals 64, then no data inversion will be generated. The only allowable values for the four control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in unpredictable operations. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 596 ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers, and the appropriate flag (FNCE) in the ECC Status Register to be asserted. This register can only be read from the IPS programming model; any attempted write is ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 597 This register can only be read from the IPS programming model; any attempted write is ignored. Register address: ECSM Base + 0x0057 (0xFFF4_0057) WRITE SIZE[2:0] PROT0 PROT1 PROT2 PROT3 Reset — — — — — — — — = Unimplemented Figure 18-9. Flash ECC Attributes (ECSM_FEAT) Register MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 598 (FNCE) in the ECC Status Register to be asserted. The data captured on a multi-bit non-correctable ECC error is undefined. This register can only be read from the IPS programming model; any attempted write is ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 599 ECSM_PRESR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers, and the appropriate flag (RNCE) in the ECC Status Register to be asserted. This register can only be read from the IPS programming model; any attempted write is ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 600 The ECSM_PRESR can only be read from the IPS programming model; any attempted write is ignored. Register address: ECSM Base + 0x0065 (0xFFF4_0065) PRESR[7:0] Reset — — — — — — — — = Unimplemented Figure 18-12. RAM ECC Syndrome Register (ECSM_PRESR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 601 0x4A DATA ODD BANK[4] 0x4C DATA ODD BANK[5] 0x4F DATA ODD BANK[21] 0x51 DATA ODD BANK[6] 0x52 DATA ODD BANK[7] 0x54 DATA ODD BANK[8] 0x57 DATA ODD BANK[22] 0x58 DATA ODD BANK[9] MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 602 ECC EVEN[4] 0xA0 ECC EVEN[5] 0xC0 ECC EVEN[6] 0xC3 DATA EVEN BANK[0] 0xC5 DATA EVEN BANK[1] 0xC6 DATA EVEN BANK[2] 0xC9 DATA EVEN BANK[3] 0xCA DATA EVEN BANK[4] 0xCC DATA EVEN BANK[5] MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 603 ECSM_REAR, ECSM_PRESR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers, and the appropriate flag (RNCE) in the ECC Status Register to be asserted. This register can only be read from the IPS programming model; any attempted write is ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 604 Register address: ECSM Base + 0x0067 (0xFFF4_0067) WRITE SIZE[2:0] PROT0 PROT1 PROT2 PROT3 Reset — — — — — — — — = Unimplemented Figure 18-14. RAM ECC Attributes (ECSM_REAT) Register MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 605 32-bit word. The upper 32 bits will read back all zeroes as defined. This register can only be read from the IPS programming model; any attempted write is ignored. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 606 REDH[31:0] This 64-bit register contains the data associated with the faulting access of the last, REDL[31:0] properly-enabled RAM ECC event. The register contains the data value taken directly from the data bus. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 607: Information Specific To This Device
The STM programming model has fourteen 32-bit registers. The STM registers can only be accessed using 32-bit (word) accesses. Attempted references using a different size or to a reserved address generates a bus error termination. 19.4.1 Memory map The STM memory map is shown in Table 19-1. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 608: Register Descriptions
19-610 0x0048 STM Channel 3 Compare Register(STM_CMP3) on page 19-611 0x004C – 0x3FFF Reserved — — — 19.4.2 Register descriptions The following sections detail the individual registers within the STM programming model. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 609 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-2. STM Count Register (STM_CNT) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 610 0 = The channel is disabled. 1 = The channel is enabled. 19.4.2.4 STM Channel n Interrupt Register (STM_CIRn) The STM Channel n Interrupt Register (STM_CIRn) has the interrupt flag for channel n of the timer. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 611 Description Compare value for channel n If the STM_CCRn[CEN] bit is set and the STM_CMPn register matches the STM_CNT register, a channel interrupt request is generated and the STM_CIRn[CIF] bit is set. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 612: Functional Description
STM_CIR[CIF] bit and generate an interrupt request when the channel compare register matches the timer counter. The interrupt request is cleared by writing a ‘1’ to the STM_CIRn[CIF] bit. A write of ‘0’ to the STM_CIRn[CIF] bit has no effect. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 613: Introduction
32-bit (word) accesses. References using a different size are invalid. Other types of invalid accesses include: writes to read-only registers, incorrect values written to the service register when enabled, accesses to reserved addresses and accesses by masters without permission. If the RIA bit in the MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 614: Memory Map
The SWT_MCR contains fields for configuring and controlling the SWT. The reset value of this register is device specific. Some devices can be configured to automatically clear the SWT_MCR[WEN] bit during the boot process. This register is read-only if either the SWT_MCR[HLK] or SWT_MCR[SLK] bits are set. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 615 0 = SWT_MCR, SWT_TO SWT_WN and SWT_SK are read/write registers if HLK = 0 1 = SWT_MCR, SWT_TO, SWT_WN and SWT_SK are read-only registers Clock Selection Selects the clock that drives the internal timer 0 = System clock 1 = Oscillator clock MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 616 The SWT Time-Out (SWT_TO) register contains the 32-bit time-out period. The reset value for this register is device specific. This register is read-only if either the SWT_MCR[HLK] or SWT_MCR[SLK] bits are set. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 617 When window mode is enabled, the service sequence can only be written when the internal down counter is less than this value. 20.3.2.5 SWT Service Register (SWT_SR) The SWT Time-Out (SWT_SR) service register is the target for service operation writes used to reset the watchdog timer. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 618 SWT Service Key Register (SWT_SK) The SWT Service Key (SWT_SK) register holds the previous (or initial) service key value. This register is read-only if either the SWT_MCR[HLK] or SWT_MCR[SLK] bits are set. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 619: Functional Description
If the SWT_MCR[KEY] bit is zero, the fixed sequence 0xA602, 0xB480 is written to the SWT_SR[WSC] field to service the watchdog. If the SWT_MCR[KEY] bit is set, then MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 620 Then the SWT can be disabled (SWT_MCR[WEN] cleared) and the value of the SWT_CO read to determine if the internal down counter is working properly. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 621: Overview
The BAM program is not executed when the device comes out of reset in OnCE debug mode. The user must provide the required device initialization using the development tool before accessing the device resources. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 622: Internal Boot Mode
0xFFFF_F000 – 0xFFFF_FFFF BAM program 0xFFFF_FFFC Device reset vector 0xFFFF_FFF8 BAM Last executed instruction 21.5 Functional description 21.5.1 BAM Program flow chart The BAM program flow chart is shown in Figure 21-1. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 623: Bam Program Operation
The BAM is accessed by the device core after the negation of RSTOUT, before user code starts. First, the BAM program configures the core MMU to allow access to all device internal resources, according to Table 21-2. This MMU setup remains the same for internal Flash boot mode. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 624 [0:1] 0x00FF_FDE 0x00FF_FDE state password state !0x55AA Internal—Censored Enabled Disable Flash Any value 0x55AA Internal—Public Enabled Enabled Public 0x55AA Serial—Flash password Enabled Disable Flash Any value !0x55AA Serial—Public password Disable Enabled Public MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 625 0xFEED_FACE_CAFE_BEEF) or needs to be compared to a Flash password - 64-bit data, stored in the shadow row of internal flash at address 0x00FF_FDD8. If the bit is set, the BAM uses the Flash serial password, if the bit is cleared, it uses the public password. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 626: Reset Configuration Half Word (Rchw)
RCHW should reside in the very first 16-bit half word of the flash. Figure 21-4 shows the fields of the RCHW. BOOT_BLOCK_ADDRESS SWT WTE Boot Identifier = 0x5A Figure 21-4. Reset configuration half word MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 627 The watchdog timeout periods, when the watchdogs are controlled by RCHW, are shown in Table 21-5. Table 21-5. Watchdog timeouts Crystal frequency (MHz) Core WD timeout (ms) SWT timeout (ms) 40.1 32.7 27.3 21.8 20.5 16.35 16.4 13.08 6.54 327,680 system clocks 261,600 system clocks MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 628: Internal Boot Mode
BOOT_BLOCK_ADDRESS is the address from Table 21-6 where the BAM finds a valid RCHW. If the BAM program finds a valid RCHW, the core watchdog is enabled if the RCHW[WTE] bit is programmed MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 629 • eDMA • e200z4 processor 64-bit Password Enable/disable Compare Nexus client TAP controller JTAG Port Controller 64-bit Password CENSOR_CTRL register Debug/Calibration Tool Access Figure 21-6. Enabling JTAG/Nexus port access on a censored device MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 630: Serial Boot Mode
Fixed Baud Rate is selected. SIU_RSR[ABR] bit reflects the inverted state of the EVTO pin, thus to select Baud Rate Detection mode, the EVTO pin needs to be driven low. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 631 11.18 The SWT is used as a watchdog during serial boot mode, but the core watchdog is enabled just before switching to the user application to provide compatibility with earlier MPC55XX parts. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 632 TXD signal. It is the responsibility of the host computer to compare the echoes with the sent data and restart the process if an error is detected. 21.5.5.3 Serial boot mode download protocol The download protocol follows four steps: 1. Host sends 64-bit password. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 633 2. Download start address, size of download, and VLE bit. The next 8 bytes received by the device are considered to contain a 32-bit start address, the VLE mode bit, and a 31-bit code length (see Figure 21-8). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 634 To provide compatibility with older devices, the BAM writes the core time base registers (TBU and TBL) with 0x0 and enables the core watchdog to cause a reset after a time-out period of MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 635 The CAN controller can be programmed with 8 to 25 number of quanta per bit. The bit timing parameters, selected by the baud rate detection routine, are shown in Table 21-9. (See FlexCAN chapter for the parameters definition). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 636 Max baud rate for SCI Min baud rate for SCI xtal [MHz] [bit/s] /25/256) [bit/s] /160) [bit/s] /16/2 ) [bit/s] 1250 1875 11.5 2500 100K 15.2 3125 125K Limited to 1 Mbit/s by CAN standard MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 637: Booting From The External Bus Interface (Ebi)
Selects ADDR[12:15] and sets pads to 20 pF drive strength SIU_PCR[12:27] 0x40C Selects ADDR[16:31], sets pads to medium slew rate and enables weak pull device for pads SIU_PCR[28:43] 0x440 Selects DATA[0:15] and sets pads to 20 pF drive strength MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 638 SIU_PCR[68:69] 0x443 Selects OE and TS functions, sets pads to 20 pF drive strength, enables weak pull device for pads and enables pullup MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 639: Device-Specific Features
PWM waveforms or measuring input pulse width. It is implemented with its own configuration of timer channels to suit the target applications needs, while maintaining full backwards compatibility with previous eMIOS implementations. The MPC5644A has one eMIOS200 module that implements twenty-four 24-bit counters.
Page 640: Features
Global enable feature for all eMIOS and eTPU timebases • Dedicated pin for each channel (not available on all package types) Each channel (0–23) supports the following functions: • General-purpose input/output (GPIO) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 641: Modes Of Operation
IP interface. 22.2.3 Channel configurations Table 22-1 shows all configurations available in the MPC5644A eMIOS200. These modes are described Section 22.5.1.1, Channel modes of operation. NOTE Not all configurations are available on all channels. If an unimplemented mode is selected (by writing a reserved value to MODE[0:6] in a channel’s...
Page 642: External Signals Description
Configurable Enhanced Modular IO Subsystem (eMIOS200) Table 22-1. All available MPC5644A eMIOS channel configurations (continued) Description Name Location Output Pulse Width and Frequency Modulation Buffered OPWFMB on page 22-674 Output Pulse Width Modulation Buffered OPWMB on page 22-679 22.3 External signals description Each channel has one external input and one external output signal.
Page 643 Configurable Enhanced Modular IO Subsystem (eMIOS200) Table 22-2. MPC5644A eMIOS memory map (continued) Offset from EMIOS_BASE Register Location (0xC3FA_0000) 0x0038–0x003F Reserved Channel 1 registers 0x0040 EMIOS_CADR[1]—A Register on page 22-653 0x0044 EMIOS_CBDR[1]—B Register on page 22-653 0x0048 EMIOS_CCNTR[1]—Counter Register on page 22-654 0x004C EMIOS_CCR[1]—Control Register...
Page 644 Configurable Enhanced Modular IO Subsystem (eMIOS200) Table 22-2. MPC5644A eMIOS memory map (continued) Offset from EMIOS_BASE Register Location (0xC3FA_0000) 0x00B4 EMIOS_ALTA[4] —Alternate A Register on page 22-660 0x00B8–0x00BF Reserved Channel 5 registers 0x00C0 EMIOS_CADR[5]—A Register on page 22-653 0x00C4 EMIOS_CBDR[5]—B Register...
Page 645 Configurable Enhanced Modular IO Subsystem (eMIOS200) Table 22-2. MPC5644A eMIOS memory map (continued) Offset from EMIOS_BASE Register Location (0xC3FA_0000) 0x0130 EMIOS_CSR[8]—Status Register on page 22-659 0x0134 EMIOS_ALTA[8] —Alternate A Register on page 22-660 0x0138–0x013F Reserved Channel 9 registers 0x0140 EMIOS_CADR[9]—A Register...
Page 646 Configurable Enhanced Modular IO Subsystem (eMIOS200) Table 22-2. MPC5644A eMIOS memory map (continued) Offset from EMIOS_BASE Register Location (0xC3FA_0000) 0x01AC EMIOS_CCR[12]—Control Register on page 22-655 0x01B0 EMIOS_CSR[12]—Status Register on page 22-659 0x01B4 EMIOS_ALTA[12] —Alternate A Register on page 22-660 0x01B8–0x01BF...
Page 647 Configurable Enhanced Modular IO Subsystem (eMIOS200) Table 22-2. MPC5644A eMIOS memory map (continued) Offset from EMIOS_BASE Register Location (0xC3FA_0000) 0x0228 EMIOS_CCNTR[16]—Counter Register on page 22-654 0x022C EMIOS_CCR[16]—Control Register on page 22-655 0x0230 EMIOS_CSR[16]—Status Register on page 22-659 0x0234 EMIOS_ALTA[16] —Alternate A Register on page 22-660 0x0238–0x023F...
Page 648 Configurable Enhanced Modular IO Subsystem (eMIOS200) Table 22-2. MPC5644A eMIOS memory map (continued) Offset from EMIOS_BASE Register Location (0xC3FA_0000) 0x02A4 EMIOS_CBDR[20]—B Register on page 22-653 0x02A8 EMIOS_CCNTR[20]—Counter Register on page 22-654 0x02AC EMIOS_CCR[20]—Control Register on page 22-655 0x02B0 EMIOS_CSR[20]—Status Register...
Page 649: Global Registers
22.4.2 Global registers All global control registers are 32-bit wide but some do not use the most significant 8 bits because the MPC5644A has 24 channels and 24-bit counters. 22.4.2.1 eMIOS200 Module Configuration Register (EMIOS_MCR) The EMIOS_MCR contains global control bits for the eMIOS200 module.
Page 650 0010 eTPU engine A, TCR2 0011 Reserved 0100–1111 Reserved GPRE[0:7] Global Prescaler The GPRE bits select the clock divider value for the global prescaler. GPRE Divide ratio 0000_0000 0000_0001 0000_0010 0000_0011 1111_1110 1111 1111 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 651 Output Update Disable Register (EMIOS_OUDR) Address: EMIOS_BASE (0xC3FA_0000) + 0x0008 Access: User read/write Reset R OU OU9 OU8 OU7 OU6 OU5 OU4 OU3 OU2 OU1 OU0 Reset Figure 22-4. eMIOS200 Output Update Disable Register (EMIOS_OUDR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 652: Channel Registers
1 Channel [n] disabled 22.4.3 Channel registers All channel control registers are 32-bit wide but some do not use the most significant 8 bits because the MPC5644Ahas 24 channels and 24-bit counters. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 653 Depending on the channel’s configuration, it may or may not have the EMIOS_CBDR. This means that if at least one mode that requires the register is implemented, then the register is present. Otherwise, it is absent. MPC5644A has register B (EMIOS_CBDR) in all channels. Table 22-7. EMIOS_CADR[n], EMIOS_CBDR[n], and EMIOS_ALTA[n] values assignment...
Page 654 Depending on its configuration, a channel may have an internal counter or not. If at least one mode that requires the counter is implemented, the counter is present, otherwise it is not. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 655 Output Disable Select The ODISSL bits select one of the four output disable input signals. ODISSL Input signal Output disable input 0 Output disable input 1 Output disable input 2 Output disable input 3 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 656 The input signal is synchronized before arriving to the digital filter. Filter Clock Select The FCK bit selects the clock source for the programmable input filter. 0 Prescaled clock 1 Main clock MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 657 • Counter bus[D] is driven by channel 16 and can supply time base to channels 16 to 23. Note: When BSL = 1, Channels 0, 8 and 16 must be in MCB mode. Reserved All channels: internal counter MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 658 0000110 Double Action Output compare (with FLAG set on B match) 0000111 Double Action Output compare (with FLAG set on both match) 0001000 through Reserved 1001111 101000b Modulus Counter Buffered (Up counter) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 659 ‘1’. 0 An overflow has not occurred. 1 An overflow has occurred. UCIN Unified Channel Input Pin The UCIN bit reflects the input pin state after being filtered and synchronized. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 660: Functional Description
Counter bus selector, which selects the time base to be used by the channel for all timing functions 1. The eMIOS200 Unified Channel has a reduced set of functions when compared to MPC5500 Unified Channel implementations. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 661 Programmable Prescaler Filter Channel Controller Match Logic Mode Logic Control Signals Channel Data Path uc_cnt_rd_data[n] Comparator A Counter Bus Comparator B Counter Bus[0] Counter Bus[1] uc_cnt_rd_data[n] Figure 22-12. Unified Channel block diagram MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 662 General Purpose Registers Control Block global counter bus BSL[1]+logic local counter bus [B/C/D] internal counter BSL[0] A Comparator BSL[1]+logic B Comparator Datapath BSL[1]+logic Figure 22-13. Unified Channel Control and Datapath block diagrams MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 663 SAIC mode is entered exiting from GPIO mode the channel is ready to capture events. The events are captured as soon as they occur thus reading register A always returns the value of the latest captured event. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 664 When SAOC mode is entered exiting from GPIO mode the output flip-flop is set to the complement of the EDPOL bit in the EMIOS_CCR[n]. The counter bus can be either internal or external and is selected through BSL[0:1] bits. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 665 0x001100 0x001000 FLAG pin/register 0x001000 A1 value 0xxxxxxx 0 x001000 0x001000 0x001000 Notes: 1. CADR[n] = A2 A2 = A1 according to OU[n] bit Figure 22-17. SAOC example toggling the output flip-flop MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 666 A1 are not blocked at any time. The input pulse width is calculated by subtracting the value in B1 from A2. Figure 22-19 shows how the channel can be used for input pulse width measurement. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 667 EMIOS_CADR[n]. Note that even in this case B1 register updates will be blocked after EMIOS_CADR[n] read, thus a second EMIOS_CBDR[n] is required in order to release B1 register updates. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 668 EMIOS_CBDR[n] is read. After EMIOS_CBDR[n] is read, register A1 content is transferred to register B1 and the transfers from B2 to B1 are re-enabled to occur at the transfer edges, which is the leading edge in the Figure 22-22 example. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 669 At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level corresponding to a comparison event in comparator A or B, respectively. Note that the FLAG bit is not affected by these forced operations. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 670 1. CADR[n] = A1 (when reading) Notes: 2. CBDR[n] = B1 (when reading) A2 = A1according to OU[n] bit B2 = B1according to OU[n] bit Figure 22-24. Double Action Output Compare with FLAG set on both matches MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 671 A1 match occurs. The internal counter is set to 0x1 when its value matches A1 value and a clock tick occurs (either prescaled clock or input pin event). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 672 If A2 is written in cycle n, this new value will be used in cycle n+1 for A1 match. Flags are generated only at A1 match start if MODE[5] is 0. If MODE[5] is set to 1 flags are also generated at the cycle boundary. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 673 Thus A1 receives this new value at the next cycle boundary. Note that the update disable bits OU[n] of EMIOS_OUDR can be used to disable the update of register A1. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 674 Note that in the example shown in Figure 22-30 the internal counter prescaler has a ratio of two. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 675 This allows using the A1 posedge match to mask the B1 negedge match when they occur at the same time. The result is that no transition occurs on the output flip-flop and a 0% duty cycle is generated. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 676 B2 data written on cycle n were loaded to A1 or B1, respectively, thus generating matches in cycle n+1. Note that the FLAG has a synchronous operation, meaning that it is asserted one system clock cycle after the FLAG set event. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 677 EDPOL should be set to 0. Note that both the channel and global prescalers are set to 0x0 (each divide ratio is one), meaning that the channel internal counter transitions at every system clock cycle. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 678 A1 match, thus the output flip-flop is set to the complement of EDPOL bit. This cycle corresponds to a 100% duty cycle signal. The same output signal can be generated for any A1 value greater or equal to MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 679 Any value written to A2 or B2 on cycle n is loaded to A1 and B1 registers at the following cycle boundary (assuming OU[n] bit of EMIOS_OUDR is not asserted). Thus the new values will be used for A1 and B1 matches in cycle n+1. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 680 B1 = 0x8 negedge signal. In this case A1 match has precedence over B1 match, causing the output pin to remain at EDPOL bit value, thus generating a 0% duty cycle signal. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 681 Disable does not modify the Flag bit behavior. Note that there is one system clock delay between the assertion of the output disable signal and the transition of the output pin to EDPOL. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 682 22.5.1.2 Input programmable filter (IPF) The IPF ensures that only valid input pin transitions are received by the channel edge detector. A block diagram of the IPF is shown in Figure 22-39. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 683 In order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. Write ‘0’ at both bit EMIOS_MCR[GPREN] and UCPREN bit in EMIOS_CCR[n], thus disabling prescalers; MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 684: Ip Bus Interface Unit (Biu)
The STAC client submodule runs with the system clock, and its time slot timing is synchronized with the eTPU timing on reset. The time slot sequence is 0-1-2-3. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 685 When bit EMIOS_MCR[FRZ] is set and the module is in debug mode, the operation of the STAC client submodule is not affected; that is, there is no freeze function in this submodule. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 686: Global Clock Prescaler Submodule (Gcp)
If the internal prescalers are set after enabling the global prescaler, the internal counters may increment in the same ratio but at a different clock cycle. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 687 6. [timebase channel] Set prescaler ratio. 7. [timebase channel] Enable channel prescaler. 8. [output channel] Disable channel prescaler. 9. [output channel] Set A/B register. 10. [output channel] Select timebase input through BSL[1:0] bits. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 688 Configurable Enhanced Modular IO Subsystem (eMIOS200) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 689: Introduction
Section 23.3.7, REACM Channel n Configuration Register (REACM_CHCRn)) 3. Threshold data (see Section 23.3.12, REACM Threshold Bank Register (REACM_THBK)) 4. Timer bank data (see Section 23.3.10, REACM Shared Timer Bank Registers (REACM_STBK)) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 690 In both cases the reaction module only enters debug mode if enabled by bit REACM_MCR[FREN]: • If the FREN bit and the FRZ bit are both is asserted the module enters debug mode. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 691: Block Diagram
System (eTPU Timer channels) channels side port device pins ADC sampled (PSI) data rchn_a Reaction Module Reaction rchn_b Channels register access rchn_c can be driven by Figure 23-1. Reaction module system interconnection MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 692 Channels Modulation rchn_a Control Bank rchn_b reaction rchn_c channel Timer Holdoff Bank Threshold Comparator Bank eQADC ADC result side port greater or equal ADC TAG Figure 23-2. Channel interaction with internal submodules MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 693 MODULATION_ADDR field in the REACM_CHCRn. The original value of this field is preserved, thus when a new modulation cycle is initiated the same modulation address value may be used. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 694 (PSI) router info ADC TAG store ADC result Figure 23-3. Reaction module block diagram Table 23-1 lists the MPC5644A reaction module outputs. Table 23-1. Reaction module outputs Reaction channel Output pin rch0_a eTPU14 rch0_b eTPU20 MPC5644A Microcontroller Reference Manual, Rev. 6...
Page 695: Signal Description
OFF during a certain amount of time. The hold-off counter itself is located inside each one of the channels. 23.2 Signal description Table 23-2 shows the chip-level signals for the Reaction Module. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 696: Reacm_Rchn — Reacm Channel (N) Output Pin A, B And C
0x0100 + REACM Channel n Configuration Register (REACM_CHCRn) on page (n*0x10) (n = 0–5) 23-703 0x0100 + REACM Global Error Flag Register (REACM_GEFR) (n = 0–5) on page (n*0x10 + 0x4) 23-706 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 697: Reacm Module Configuration Register (Reacm_Mcr)
(REACM_MWBK) 23-714 0x0730 – 0x0FFF Reserved 23.3.2 REACM module configuration register (REACM_MCR) The REACM module configuration register (REACM_MCR) contains the control bits to configure the general operation of the Reaction Module. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 698 Reaction Module is in stopped by a device stop request. 0 Debug Mode disabled 1 Debug Mode enable Timer Prescaler Enable TPREN The TPREN bit enables the Shared Timer Prescaler in the Reaction Module. 0 Prescaler Disabled 1 Prescaler Enabled MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 699: Reacm Timer Configuration Register (Reacm_Tcr)
HPRE does not affect TPRE and modifying TPRE does not affect HPRE. Address: REACM_BASE (0xC3FC_7000) + 0x0004 Access: User read/write HPRE[11:0] Reset TPRE[7:0] Reset Figure 23-5. REACM Timer Configuration Register (REACM_TCR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 700: Reacm Threshold Router Register (Reacm_Thrr)
ADC result is used for the channel modulation being executed. Address: REACM_BASE (0xC3FC_7000) + 0x0008 Access: User read/write Reset THRADC1[3:0] THRADC0[3:0] Reset Figure 23-6. REACM Threshold Router Register (REACM_THRR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 701: Reacm Adc Sensor Input Register (Reacm_Sinr)
TAG value to execute a comparison and to evaluate an eventually new value for the channel outputs. Address: REACM_BASE (0xC3FC_7000) + 0x0010 Access: User read/write ADC_TAG[3:0] Reset ADC_RESULT[15:0] Reset Figure 23-7. REACM ADC Sensor Input Register (REACM_SINR) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 702: Reacm Global Error Flag Register (Reacm_Gefr)
MAXL, OCDF, SCDF, SQER, RAER, or TAER error flags as described in Section 23.3.8, REACM Channel n Status Register (REACM_CHSRn). The EFn bit is automatically cleared if the corresponding channel flags are all cleared. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 703: Reacm Channel N Configuration Register (Reacm_Chcrn)
Reaction module. In order for this functionality to be used it is required that CHEN[1:0] = 11. 1 Channel executes modulation 0 Channel does not perform modulation MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 704 Note that disabling the channel through CHOFF does not disable the channel operation, only the channel outputs are forced to DOFF state. 1 Output Disable Enabled 0 Output Disable Disabled 11–12 Reserved, should be cleared. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 705: Reacm Channel N Status Register (Reacm_Chsrn)
The REACM Channel n Status Register (REACM_CHSRn) provides access to the channel flags and flag clear bits. It also provides access to the current values of the channel output being driven and the Modulation Word being accessed by the channel. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 706 Section 23.6, “Monitored modulation. This Flag is set if the channel activation window signal is set (eTPU channel or SWMC bit). 1 Short Circuit Detected 0 Normal Operation MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 707 1 Clears MAXL bit 0 No action Open Circuit Detection Flag Clear OCDFC The OCDFC clears the OCDF flag if write 0x1. This bit reads always as 0x0 1 Clears OCDF bit 0 No action MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 708: Reacm Channel N Router Register (Reacm_Chrrn)
ADC result data. The channels have access to any 16 timer inputs and any ADC sample tag from 0 to 15. Note that this architecture allows several reaction channels to point to the same timer channel or to the same ADC result. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 709 The CHIR[3:0] field selects which eTPU channel is used by the reaction channel for the modulation. See Table 23-13 for valid values. Table 23-13. REACM_CHRRn[CHIR] values CHIR[3:0] eTPU A channel 0b0000 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 0b1010 0b1011 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 710: Reacm Shared Timer Bank Registers (Reacm_Stbk)
The timer values are programmed by software and addressed by the reaction channel based on the data read from a Modulation Word. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 711: Reacm Threshold Bank Register (Reacm_Thbk)
ADC. Based on that comparison the reaction channel decides the Channel output value to be either HOD or LOD. Address: REACM_BASE (0xC3FC_7000) + (from 0x0400 to 0x045C) Access: User read/write Reset THRESHOLD_VALUE[15:0] Reset Figure 23-14. REACM Threshold Bank Register (REACM_THBK) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 712: Reacm Adc Result Maximum Limit Check Register (Reacm_Adcmax)
23.3.14 REACM Modulation Range Pulse Width Register (REACM_RANGEPWD) The REACM Modulation Range Pulse Width Register (REACM_RANGEPWD) provides the value used to check if the PWM pulse width generated during the modulation process is larger than a maximum pulse MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 713: Reacm Modulation Minimum Pulse Width Register (Reacm_Minpwd)
The checking is performed by using the channel internal Hold-off timer during appropriate times on the channel operation when this counter is not being used for the hold-off modulation cycle. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 714: Reacm Modulation Control Word Bank Registers (Reacm_Mwbk)
Address: REACM_BASE (0xC3FC_7000) + (from 0x0700 to 0x072C) Access: User read/write MM[1:0] SM[1:0] HOD[2:0] LOD[2:0] Reset THRESPT[5:0] STPT[3:0] HDOFFTPT[3:0] Reset Figure 23-18. REACM Modulation Control Word Bank Registers (REACM_MWBK) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 715 OFF state. Note: Set HOD[2:0]=LOD[2:0] when using threshold-threshold modulation together with sequence advance, in order to avoid fast glitches during the sequence advance Reserved, should be cleared. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 716 Advance to the next modulation word when a threshold level is achieved achieved. The threshold level is defined by the THRESPT pointer. See section Section 23.10.1, Advancing modulation phase on a threshold level. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 717: Functional Description
Channel Configuration register. The MM and SM fields in the Modulation Word provide the Modulation Mode and Sequencer Mode control, respectively. Figure 23-19 describes the internal architecture of the reaction channel and its interconnection with other submodules. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 718 In the middle there is the PWM waveform which is used to drive the power on and off at the load, thus generating the third waveform which represents the current passing through the load. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 719: Modulation Control Words Bank
(CHEN is configured). Therefore, when the modulation cycle is triggered by the timer window start event, all needed information for the modulation is already stored inside the channel. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 720: Shared Timer Bank
The valued pointed by TIMERPT is loaded into one of the three counters which counts down until reaching zero. At this time a timeout indication is sent to the requesting channel and the timer is deallocate, moving back to IDLE state. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 721: Hold-Off Timer Bank
This bank is shared among all channels and is addressed based on the HDOFFPT pointer in the Modulation Control Word. Figure 23-22 shows a block diagram of this bank and its interconnections. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 722: Threshold Bank And Comparator
The COMP (comparison result) is routed to the channel selected by the received TAG. Once having received the comparison result the channel takes the appropriate actions in order to execute the modulation mode as defined by the modulation control word. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 723: Adc Interface
The ADC Interface data (ADC_TAG and ADC_RESULT) should not be updated until all Reaction Channels (with ADCR = ADC_TAG) process the received data. The OVR flag is set in the case of an MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 724 The ADC interface and the threshold bank can operate in a learn mode, meaning that the received ADC result can be stored in the threshold bank and used for comparisons. This functionality allows the user to MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 725: Prescalers
I/O level. The banked mode architecture allows the stacking of up to four reaction channels. Figure 23-26 shows the connection between two adjacent channels, CH0 and CH1. The REACM_CHCRn BSB bits are used to control the configuration of channel output logic. Thus if BSB[0] MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 726 The Banked Mode support hardware is implemented on groups of four channels. The groups are defined as CH[3:0] and CH[5:4]. Thus CH[3] and CH[5] do not connect to the subsequent channel which are CH[4] and CH[0] respectively. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 727: Modulation Modes
The output controls are then driven with LOD[2:0] for a fixed amount of time defined by the hold-off timer. Note that the upper threshold limit and the hold-off timer pointer are indicated by the modulation word in the REACM_MCR register. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 728: Limitations On The Modulation Process
DOFF field. NOTE No error flag is set if this violation occurs. Figure 23-29 describes the channel behavior if the minimum time between two consecutive timer control pulses is violated. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 729 DOFF which causes the modulation to end. Note that an early end of pulse only affects the current modulation cycle. Meaning that on the next modulation cycle the modulation word 0 is executed first and all subsequent words are executed in the appropriate sequence. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 730 • a sequence advance event (timeout or threshold, depending on SM). • a new sample is received (no matter if the comparison matches or not). • a hold-off timeout. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 731: Monitored Modulation
RANGE_PWD and MIN_PWD registers, as shown in Figure 23-31. NOTE Consider an uncertainty of (+1) in the value MIN_PWD and (MIN_PWD + RANGE_PWD) when calculating the pulse width limits. The Hold-off prescaler contributes to this uncertainty. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 732 PWM pulse is still high, meaning that the outputs did not switched to LOD. In this case the OCDF flag is set in the CHSR, Channel Status register, of the corresponding channel. See Figure 23-10. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 733 PWM pulse load hdo timer with MIN_PWD SCDR bit is set in the status register an interrupt is generated if enabled timeout occurred in hdo Figure 23-33. Short circuit detection using hold-off timer MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 734: Dma Support
Channel. The DMA request signal is asserted when the Modulation Word 1 is executed by the channel. This signal remains asserted until a DMA done signal is issued by the DMA controller. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 735: Reset Overview
Error Flag register to evaluate which channel issued the interrupt. After that the Channel Status register need to be read to distinguish between the several interrupt sources by evaluating the flags MAXL, OCDF, SCDF, TAER, and SQER. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 736: Interrupt Sources
The current is sampled by the ADC and the result is sent to the Reaction Module, allowing closed loop control. NOTE This injector bank architecture does not allow both injectors to operate at the same time since the sensor in the feedback loop is shared by both injectors. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 737 Note that only one channel is active at a given time since the eTPU time windows are not active at the same time for both reaction channels. Please see Figure 23-36 for more details. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 738 CH1 is used to control Injector B. However, the Vboost/Vbatt selection is controlled by CH0 ch0_a output only since when Vboost driver is switched off Vbatt power source is applied to the injectors by the direct bias of the diode connecting Vbatt to the injector bank. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 739 It is important to notice that even if two reaction channels control different injectors they can share the data stored in the Modulation Word Control. In this case both channels should execute the same type of MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 740 ADC result is ignored by the Reaction module. After CHEN field is programed, the reaction channels wait until a timer window is initiated by eTPU for the modulation process to start. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 741 I0 is read from Threshold Bank by using THRESPT = 0x0 that points to address 0 of this bank • I1 is read from Threshold Bank by using (THRESPT + 1) = 0x1 • Hold-off timer is not used, therefore HDOFFPT can have any value (X) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 742: Advancing Modulation Phase On A Threshold Level
23-40. This functionality is used to assure a specific current level was achieved before the reaction channel advances to the next modulation phase, thus making sure that the solenoid had the fastest opening speed. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 743: Controlling The Loop Function
The LOOP field in the Modulation Word controls the sequencing of Modulation Words to be executed by the channel. If LOOP = 1 and a phase is ended the next Modulation Word address returns to the initial MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 744: Banked Mode
Injector D Injector C boost Injector B ch2_b Injector A circuit logic ch2_c ch3_a banked ch3_b logic ch3_c Sensor Sensor Figure 23-42. Four channels controlling two injector banks in banked mode MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 745: Information Specific To This Device
• Reduced latency: pin actions are immediate. • Reduce or eliminate host interrupt service time. • Double action channel capability reducing the channel request rate. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 746: Overview
CPU. Instructions execute faster, service time is reduced and program memory compacted. Instructions executed by the eTPU are connected directly to the eTPU timing hardware and allow parallelism of hardware related actions. 24.2.1 Overview Figure 24-1 shows a top-level eTPU block diagram. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 747 Memory (SCM). Shared Parameter RAM (SPRAM)—holds eTPU application parameters and work data. It is accessed by Host and the microengine. Bus Interface Unit (BIU)—allows Host to access eTPU registers, SCM and SPRAM. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 748 SPRAM is used for both eTPU engine’s data storage and for passing information between the eTPU engines and the host CPU. Figure 24-2 shows the block diagram for the eTPU engine. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 749 TCRCLK clock pin. In addition, the TCR2 timebase can be derived from special angle-clock hardware which enables implementing angle-based functions. This feature is added to support advanced angle based engine control applications. For further details refer to Section 24.5.6, Time Bases. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 750 In addition, the Host writes to the Host Service Request and channel configuration registers to further define Function operation for each initialized channel. Refer to Section 24.5.2, Host interface for a detailed description. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 751 Out of reset, all channels are disabled. The Host CPU makes a channel active by assigning it one of three priorities: high, middle, or low. The Scheduler determines the order in which channels are serviced based MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 752: Features
NOTE The MPC5644A eTPU has one eTPU2 engine. On devices with two eTPU engines, the eTPU parameter RAM (SPRAM), code memory (SCM) and Bus Interface Unit (BIU) are shared by both engines, enabling processor core-to-eTPU communication and eTPU engine-to-engine communication.
Page 753 — Global parameter address mode allows access to common Channel data of up to 256 32-bit parameters (1024 bytes) — Support for indirect and stacked data access schemes. — Parallel execution of: data access, ALU, Channel control and flow control subinstructions in selected combinations. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 754 • Input and Output features separated in channel logic and microinstructions, allowing input and output signals to be processed separately or combined. • Increased time resolution and execution unit to 24 bits MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 755 • Channel Flags 0 and 1 can now be tested for branching, besides selecting the entry point. • Channel digital filters can be bypassed. • Scheduler priority-passing mechanism can now be disabled. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 756: Modes Of Operation
ETPU_ECR bit MDIS, saving power. Input sampling stops. eTPU engines can be in Module Disable Mode independently. Module Disable Mode stops only the engine clock, so that the Shared BIU, and Global Channel registers MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 757 Stop Mode as soon as VIS = 0. NOTE An engine can stay in Module Disable mode when it leaves Stop Mode if its bit MDIS = 1, even if the other leaves it. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 758: External Signal Description
Each channel output signal is associated with a channel. The microcode may affect the logic level of an output signal by implementing one of two actions: • Specify the logic level output to the signal when there is a match or a transition. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 759 For generation of very short pulses the eTPU pads have to be programmed by the system integration for fast operation mode with the voltage levels defined for fast pad operation in the MCU technology. 1. Sampled on the T4 microcycle phase, see Section 24.7.1, Microcycle and I/O timing. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 760: Memory Map/Register Definition
Table 24-4 shows a detailed memory map. Offsets are relative to the eTPU base address, which is MCU-dependent. NOTE For MPC5644A, the eTPU2 base address is 0xC3FC_0000. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 761 Section 24.4.2.1, ETPU_MCR – eTPU Module Configuration Register). Table 24-4. Detailed memory map Offset Location 0x00 ETPU_MCR – eTPU Module Configuration Register on page 24-767 0x04 ETPU_CDCR – eTPU Coherent Dual-Parameter Controller Register on page 24-771 0x08 RESERVED MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 762 0x5C RESERVED 0x60 ETPU_WDTR_1 – eTPU 1 Watchdog Timer Register on page 24-790 0x64 RESERVED 0x68 ETPU_IDLE_1 – eTPU 1 Idle Counter Register on page 24-791 0x6C RESERVED 0x70 RESERVED 0x74 RESERVED MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 763 ETPU_CDTRSR_1 – eTPU 1 Channel Data Transfer Request Status Register on page 24-793 0x214 RESERVED 0x218 RESERVED 0x21C RESERVED 0x220 ETPU_CIOSR_1 – eTPU 1 Channel Interrupt Overflow Status Register on page 24-794 0x224 RESERVED 0x228 RESERVED 0x22C RESERVED MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 764 ETPU_C0HSRR_1 – eTPU 1 Channel 0 Host Service Request Register on page 24-809 0x40C RESERVED 0x410 ETPU_C1CR_1 – eTPU 1 Channel 1 Configuration Register on page 24-803 0x414 ETPU_C1SCR_1 – eTPU 1 Channel 1 Status and Control Register on page 24-806 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 765 SCM access is available only when bit VIS = 1 on register ETPU_MCR, under certain conditions (see Section 24.4.2.1, ETPU_MCR – eTPU Module Configuration Register). SCM can only be written in 32-bit accesses. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 766 Enhanced Time Processing Unit (eTPU2) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 767: System Configuration Registers
1: Negate Global Exception, clear status bits MGE1, MGE2, ILF1, ILF2 and SCMMISF 0: Keep Global Exception request and status bits MGE1, MGE2, ILF1, ILF2 and SCMMISF as is. GEC works the same way in Module Disable Mode. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 768 The ILF2 bit is set by the microengine to indicate that an illegal instruction was decoded in Engine B. This bit is cleared by host writing 1 to GEC. See Section 24.5.9.5, Illegal Instructions, for more details. 1: Illegal Instruction detected by eTPU B. 0: Illegal Instruction not detected. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 769 0: MISC operation disabled. The MISC logic is reset to its initial state. SCMMISEN resets automatically when MISC logic detects an error, i.e., when SCMMISF transitions from 0 to 1, disabling the MISC operation. 23-24 Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 770 Engine is stopped in Module Disable or Stop Modes, but accesses to registers in Stop Mode is defined in the MCU level. Engine is stopped in Module Disable or Stop Modes, but accesses to registers in Stop Mode is defined in the MCU level. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 771 (concatenation of the fields CTBASE and PARAM0/1). 3. If it is a read transfer, i.e., from channel to host, read the two parameters from the temporary area into host memory/registers. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 772 This bit selects the width of the parameters to be transferred between the PB and the target address. 1: Transfer 32-bit parameters. All 32 bits of the parameters are written in the destination address. 0: Transfer 24-bit parameters. The upper byte remains unchanged in the destination address. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 773 ETPU_MISCCMPR. If there is a mismatch, the MISC stops, issues a Global Exception and the SC MM I SF bit in the ETPU_MCR assumes value 1. If no mismatch is found, MISC repeats the procedure automatically. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 774 Writes to unimplemented addresses do not return an error and can write on unspecified mirror addresses, so they should be avoided. The reset value is MCU dependent. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 775 Global Exception. Figure 337. ETPU_SCMOFFDATAR Register Table 24-8. ETPU_SCMOFFDATAR field description Field Description 0-31 ETPUSCMOFFDATA[31:0]—SCM Off-range read data value Section 24.5.2.6.3, SCM off-range data. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 776 TST, halted, stopped, or idle (no thread executing). Note: Only on rare occasions (e.g., during a long stall, see Section 24.5.10.2.10, Microengine stall) FEND can be read as 1, because it negates as soon as the end begins execution. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 777 See Section 24.5.10.2, Development support features, for further details about entering Halt Mode. 1: eTPU engine is halted 0: eTPU engine is not halted. 9-11 Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 778 Table 24-10. Filter prescaler clock control Sample on system Filter control clock divided by: Note: A new value written to FPSCK only becomes effective when the filter prescaler finishes the current count. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 779 Section 24.5.3.2.1, Primary scheme – priority among channels on different levels). 1: Scheduler priority passing mechanism disabled. 0: Scheduler priority passing mechanism enabled. Note: SPPDIS bit must not be changed while any channel is enabled. 25-26 Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 780 Table 24-12. Entry table base address options Entry table base address for Entry table base address for host address microcode address 00000 0x000 0x000 00001 0x800 0x200 00010 0x1000 0x400 11110 0xF000 0x3C00 11111 0xF800 0x3E00 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 781: Time Base Registers
This register configures several timebase options. Offset: eTPU_A: eTPU_Base + 0x020 eTPU_B: eTPU_Base + 0x040 Access: User read/write TCR2CTL TCRCF TCR2P Reset R TCR1CTL TCR1P Reset = Unimplemented or Reserved Figure 24-6. ETPU_TBCR Register MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 782 TCR2 frozen, except as STAC client do not use with AM = 1 TCRCLK edges are not detected by the EAC logic, but they can still be detected by the channel 0 logic if AM = 01. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 783 (see Section 24.5.5.3, Transition Detection and Time Base Capture). If AM must be changed with GTBE = 1, the recommended procedure is described in Section 24.5.7.11, Restarting angle logic. Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 784 TCR1 prescaler TCR1 frozen, except as a STAC client; All other combinations of TCR1CTL and TCR1CS are reserved. This selection must not be used in Angle Mode. 19-23 Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 785 TCR1 is clocked from the output of a prescaler. The input to the prescaler is the internal eTPU system clock divided by 2, system clock, or the output of TCRCLK filter, or Peripheral Timebase input. The prescaler divides this input by (TCR1P+1) allowing frequency divisions from 1 up to 256. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 786 Reset = Unimplemented or Reserved Figure 24-7. ETPU_TB1R Register Table 24-18. ETPU_TB1R field description Field Description Reserved 8-31 TCR1[23:0]—TCR1 value TCR1 value used on matches and captures. See Section 24.5.6, Time Bases. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 787 Reset = Unimplemented or Reserved Figure 24-8. ETPU_TB2R Register Table 24-19. ETPU_TB2R field description Field Description Reserved 8-31 TCR2[23:0]—TCR2 value TCR2 value used on matches and captures. See Section 24.5.6, Time Bases. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 788 Note: When TCR1 is configured as a STAC Bus Client (REN2 = 1, RSC2 = 0) the eTPU Angle Clock hardware cannot be used. Note: RSC1 must not be changed when the respective REN1 bit is asserted. Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 789 / imported from other device. In eTPU context, a resource can be TCR1 or TCR2 (either Time or Angle values). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 790: Engine Related Registers
(in busy length mode) before the current running thread is forced to end. For more information on Watchdog operation, see Section 24.5.1.4, Watchdog. Note: The TST microcycles are also counted by the watchdog. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 791 Section 24.5.10.4.1, Idle Counter. ICLR—Idle Clear This write-only bit is used to clear the idle count IDLE_CNT. 1: Clear the idle count IDLE_CNT 0: Do not clear idle count IDLE_CNT MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 792: Channel Registers Layout
These bits, except the service and watchdog status, are mirrored in the individual channel registers, grouped by channel. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 793 Section 24.5.2.2, Interrupts and data transfer requests) from all channels are grouped in ETPU_CDTRSR. Their bits are mirrored from the Channel Status/Control registers (see Section 24.4.7.2, ETPU_CxSCR – eTPU Channel x Status Control Register). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 794 ETPU_CIOSR. Their bits are mirrored from the Channel Status/Control registers (see Section 24.4.7.2, ETPU_CxSCR – eTPU Channel x Status Control Register) and a write of ‘1’ clears a status bit. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 795 0: indicates that no interrupt overflow occurred in the channel. 0-31 CIOCx—Channel x Interrupt Overflow Clear 1: clear status bit. 0: keep status bit unaltered. For details about interrupt overflow, see Section 24.5.2.2.2, Interrupt and data transfer request overflow. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 796 DTROCx—Channel x Data Transfer Request Overflow Clear 1: clear status bit. 0: keep status bit unaltered. For details about data transfer request overflow, see Section 24.5.2.2.2, Interrupt and data transfer request overflow. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 797 Field Description 0-31 CIEx—Channel x Interrupt Enable 1: interrupt enabled for channel x 0: interrupt disabled for channel x. For details about interrupts see Section 24.5.9.3.10, Channel interrupt and data transfer requests. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 798 DTREx—Channel x Data Transfer Request Enable 1: Data Transfer request enabled for channel x. 0: Data Transfer request disabled for channel x. For details about interrupts see Section 24.5.9.3.10, Channel interrupt and data transfer requests. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 799 Only one bit may be asserted in this register at a given time. When no channel is being serviced the register read value is 0x00000000. ETPU_CSSR is a read-only register. The register can be read during normal eTPU operation for monitoring the scheduler activity. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 800 Indicates that channel x is currently being serviced. It is updated at the 1st microcycle of a Time Slot Transition (see Section 24.5.1.2, Time slot transition), or when the microengine ends the thread. 1: channel x is currently being serviced 0: channel x is not currently being serviced MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 801: Channel Configuration And Control Registers
There are 64 structures defined, one for each available channel in the eTPU System (32 for each engine). The base address for the structure presented can be calculated by using the following equation: MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 802 Enhanced Time Processing Unit (eTPU2) Channel_Register_Base = ETPU_Engine_Channel_Base + (channel_number * 0x10) where: ETPU_Engine_Channel_Base = ETPU_Base + 0x400 for Engine 1 ETPU_Engine_Channel_Base = ETPU_Base + 0x800 for Engine 2 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 803 Section 24.5.9.3.10, Channel interrupt and data transfer requests. CPR[1:0]—Channel Priority This field defines the priority level for the channel, used by the Hardware Scheduler (see Section 24.5.3, Scheduler). 00: Disabled 01: Low 10: Middle 11: High MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 804 ODIS bit, the channel output signal to the opposite of this polarity (see Figure 24-37). 1: output active high (output disable drives output to low) 0: output active low (output disable drives output to high) 18-20 Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 805 ETPU_Base + 0x8000 + CPBA*8 with parameter sign extension: ETPU_Base + 0xC000 + CPBA*8 Note: The fields ETCS, CFS and CPBA must only be changed while the channel is disabled (field CPR = 00). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 806 Section 24.4.6.1, ETPU_CISR – eTPU Channel Interrupt Status Register. See also Section 24.5.9.3.10, Channel interrupt and data transfer requests. CIOS—Channel Interrupt Overflow Status 1: interrupt overflow asserted for this channel 0: interrupt overflow negated for this channel MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 807 Signals. If the channel input and output signals are connected to the same pad, OPS reflects the value driven to the pad (if OBE = 1). This is not necessarily the actual pad value, which drives the value in the bit IPS. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 808 Each function uses this field for specific configuration. These bits can be tested by microengine code (see Section , Conditional/Unconditional branch). These bits are equivalent to the TPU/TPU2/TPU3 Host Sequence (HSQ) bits. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 809 Entry Point yet, but it does not abort the service thread from that point on. For more details, see Section 24.5.1.1, Entry points, and Section 24.5.2.5, Host service requests. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 810: Functional Description
The mechanism to select a thread based on the channel Function and type of event is described in the Section 24.5.1.1, Entry points. The priority mechanism that determines the order of Thread execution amongst pending service requests is described in Section 24.5.3, Scheduler. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 811 Unused Entry Points may be used for microcode, so this organization extends the microcode continuous area to the MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 812 Link service request allows one channel to activate another (see Section 24.5.5.5, Channel Link). 4. Host Service Request (Host writes a non-zero value to the HSR bits of the channel; see Section 24.5.2.5, Host service requests). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 813 In this scheme, shown in Table 24-36, all seven HSR combinations are used and other event type columns are marked “x” when HSR is non-zero, indicating that Host Service Request has priority over any other MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 814 TransB TransA pin state flag1 flag0 s [C4-C0] bits 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 815 3. HSR = 110 or 111, which are both coded into Entry Point 5 The remaining Entry Points use both channel flags for better state decoding, making this scheme better suited for Functions which need more states and/or faster state decoding, without needing many HSRs. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 816 Pin State Flag1 Flag0 s [C4-C0] Bits 00000 00001 00010 00011 00100 10x/001 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 817 Figure 24-26. MICROCODE ADDRESS Figure 24-26. Entry Point Format PP—Preload Parameter Field Description 0-13 Microcode Address MICROCODE This field specifies the microcode address on which the thread is to begin execution ADDRESS MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 818 • Formation of the entry point address. • Copy the ME bit in the Entry Point into MEF. • Access to the entry point location and getting the first microinstruction address. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 819 Registers B, C, D and SR are not altered by TST and keep their values from the previous thread. The values of registers A, MACL and MACH are not guaranteed at the thread start. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 820 INST Entry Point Y 1st Inst Y 2nd Inst SPRAM Wait TST1 TST2 TST3 Y 1st Inst Y 2nd Inst X END Y 3rd Inst Figure 24-27. TST Timing – No Wait-states MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 821 Y2nd Inst Addr Y Entry Addr Y1st Inst Addr Entry Point Y 1st Inst INST SPRAM Wait X END TST1 TST2 TST3 Y 1st Inst TST1 wait Figure 24-28. TST Timing – 1 Wait-State MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 822 A forced END by host writing to the ETPU_ECR bit FEND (see Section 24.4.2.5, ETPU_ECR – eTPU Engine Configuration Register). • A forced END caused by Watchdog timeout (see Section 24.5.1.4, Watchdog). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 823: Host Interface
Section 24.4.2, System configuration registers. Detailed explanation on the configured functionalities is found throughout Section 24.5, Functional description, and a specification for the initial configuration sequence is found on Section 24.6.1, Configuration sequence. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 824 Global Exception source status bits (ILF1, ILF2, SCMMISF, MGE1, MGE2). If GEC is written 1 at the same time any of the sources issues a Global Exception, both the interrupt and the status bit of that source MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 825 16-bit-wide bus cycle to a two-byte aligned address, or 8-bit wide bus cycle to any byte address. The address of the 24-bit parameters and the most significant byte depends on the endianness of the MCU. For more details, see the Section 24.6.6, Endianness. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 826 Also, temporary parameter areas should be reserved to be used by the coherent parameter transfer mechanisms described in Section 24.5.4, Parameter sharing and coherency, if necessary. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 827 Host CPU can request immediate service from a channel by writing a non-zero value to the Host Service Request register field HSR (see Section 24.4.7.3, ETPU_CxHSRR – eTPU Channel x Host Service MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 828 Only 32-bit aligned writes are allowed to SCM from the Host. Write accesses of other sizes store unpredictable values into SCM. NOTE It is necessary to turn VIS bit on to set software breakpoints (see Section 24.5.10.2.5, Software breakpoints). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 829: Scheduler
Thread execution. Since one microengine handles several channels operating concurrently, the Function threads must be executed serially. 1. Only part of these suggested operations can be parallelized in a single instruction, see Section 24.5.9.7, Microinstruction formats. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 830 Clear all grant bits of disabled channels. 1. Grant bits are also cleared in the next clock, when the service channel is chosen, or when the microengine is idle, using the same scheme. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 831 If the Scheduler was not reset to time slot one and two channels requested service at the same time, one with high priority and the other with low priority, the channel to be serviced would be the low-priority channel. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 832 In cycle B there are also no middle-level service requests before time slot six, so it passes the priority to a requesting high-level channel. During time slot six no more high level requests are left, but two new MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 833 5 (assigned to High). The second high priority channel is serviced on the next time slot, jumped to 7 because there is no middle request, ending cycle B. Cycle C starts with time slot 2, as there MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 834 (primary scheme) and its service grant bit is asserted. At the end of the thread, the service grant bit is negated (no more requests of high priority level channels). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 835 Number of active channels • Number of channels on a priority level • Number of available time slots on a priority level • Number of microcycles required to execute a thread of a Function MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 836: Parameter Sharing And Coherency
Host must coherently access parameters which are also shared by both engines. 1. A microengine access to the SPRAM in the moment CDC is performing the transfer may suffer a maximum of two wait-states. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 837 Microengine are not atomic with respect to the other. For multiple Microengine-Host coherency, the software methods described in Section 24.6.3, Multiple parameter coherency methods, or similar ones, must be used. Some of these methods rely on the fact that MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 838 1. The maximum number of Host wait states on CDC occurs when both microengines overlap their TSTs, delayed 3 system clocks from each other. 2. One microcycle takes two system clocks. Microengines get wait-states in multiples of microcycles, while Host and CDC wait-states are multiples of system clocks. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 839 24.5.4.5 SPRAM Arbitration Up to four entities can access SPRAM: • Two Microengines (in a dual eTPU engine system) • The Coherent Dual-parameter Controller (CDC) • The Host CPU (direct memory-mapped access) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 840: Enhanced Channels
1. If microengine tries to access the SPRAM in the following microcycles, the third and fourth consecutive accesses are considered the first and second of a new back-to-back dual access. 2. The microengine access slot is between its own T4 and T2 edges (see Section 24.7.1, Microcycle and I/O timing). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 841 Many event combinations are allowed for a channel, given the possibility of configuring pairs of matches and transitions for the dual-action logic, where each event MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 842 Enhanced Digital Filter, which eliminates spurious glitches on input pin signal. Output Buffer Enable is meant to control output MCU pad signal driver. A high level diagram of Channel logic and registers is shown in Figure 24-36. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 843 (Filter) Filter to branch = Channel 0 only PSTO Synchr. Output Buffer Enable Synchr. Output Signal ipp_obe_etpuch channel output Input Signal Input Signal TCRCLK channel input Figure 24-36. Channel Logic Block Diagram MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 844 A 24-bit Match register (Match A or Match B), which holds a match value. This value is compared against the selected match time base (TCR1 or TCR2). • A 24-bit Capture register (CaptureA or CaptureB), which samples the selected capture time base (TCR1 or TCR2) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 845 Table 24-41 summarizes Event Registers accesses. 1. The thread selected is determined by the Entry Point which, in turn, is determined partially by the channel latches. See Section 24.5.1.1.2, Entry point address generation. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 846 TBSA/B are 3-bit registers which have the following effect on channel configuration: • Selection of the timebase (TCR1 or TCR2) to be compared against the match values in MatchA and/or MatchB registers. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 847 Table 24-43. Pin Control Registers microcode accesses Sampled Update to Microcode Reset Register Access Type from channel channel fields value IPACA, IPACB write only immediate IPACA, IPACB 000,000 OPACA, OPACB write only immediate OPACA, OPACB 000,000 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 848 Detect input signal = 1 on Match Transition detection sets output signal high reserved Transition detection toggles output signal n.a. n.a. Match A is used for IPACA/OPACA, and Match B for IPACB/OPACB. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 849 (PSTO) or input (PSTI) pin state, or on sampled pin state (PSS, which is stable as long as CHAN does not change). 1. The filter can be bypassed. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 850 Table 24-46. TBSA Output Buffer control Microcode TBSA[2:0] meaning when TBSA[3] = 1 enable output buffer disable output buffer do nothing other values reserved 1. Output Buffer Enable: there is one independent OBE signal for each channel. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 851 Figure 24-37. Pin State Input/Output Logic 24.5.5.1.3 General Channel Registers These registers control other aspects of channel logic. Except for CHAN, they are unique per channel. Table 24-47 summarizes the registers and access options. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 852 CHAN register value Table 24-48. CHAN-selected features Selected by Feature used CHAN Channel-relative SPRAM access Branch using PSS, PRSS, PSTI and PSTO channel flags MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 853 UDCM register (see Section , UDCM – User Defined Channel Mode). Table 24-49. PDCM encoding PDCM Channel mode 0000 em_b_st 0001 em_b_dt 0010 em_nb_st 0011 em_nb_dt MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 854 Entry Table selection . SRI is asserted during reset and is controlled by microcode field MTD. 1. In TPU, SRI also blocked TDL and MDL branches and enabled any transition to capture time base. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 855 OPACA/B registers (Output Pin Action Control 1/2) and, in some cases, by IPACA/B registers. Refer to Section , IPACA,IPACB and OPACA,OPACB – Input and Output Pin Action Control Registers. 1. Microcode can also negate MRLEA/B. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 856 MEF is asserted unconditionally soon after a thread ends. 1. Before that, microcode should also negate MRLA (MRLB), otherwise an old match may be recognized by the scheduler and serviced as a new one MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 857 MRLA/B flag will keep negated, and MRLE will stay asserted. If a match is reprogrammed on TCR1 running at T2/T4 timing (TCR1CS = 1, see Section 24.4.3.1, ETPU_TBCR – eTPU Time Base Configuration Register), a match can occur after MRLA/B is cleared, together with the MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 858 Channel Mode. The IPACA and IPACB registers indicate the programmed edges of the first and second detected transition, respectively. 1. In TPU3, when TCR1 was counting at maximum rate of system clock divided by 2, the next value was captured. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 859 Time Base capture, flag setting (MRLA/B, TDLA/B), match disabling (MRLEA/B), output signal transition, and Service Request. Those 1.TCCEA provides compatibility with TPU when service request is inhibited. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 860 Table 24-50. MSR[1:0] signals – Match Service Requests Value issue no Service Requests on Matches issue Service Request on Match B only MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 861 Active value meaning M1ET Transitions are initially blocked, (Match A Enable Transitions) and Match A enables Transitions M1EM2 Match B is initially blocked (Match A Enables Match B) and Match A enables Match B MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 862 Signals TSR, TCAP and TBM2 replace the signal DTM used in previous eTPU versions. bm_dt and sm_dt are exceptions in the match blocking logic by transitions. See Section , Both Match Request Modes (bm_st, bm_dt), and Section , Single match modes (sm_st, sm_dt). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 863 Enhanced Time Processing Unit (eTPU2) sm_st_e is an exception in the capture scheme. See Section , Single match enhanced mode (sm_st_e). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 864 T1ET2 MSR[0] (channels 1, 2 only) MSR[1] Tooth Detection MSR[1] (see figure 59) MSR[0] Match A SR TransA SR TransB SR Match B SR Figure 24-39. Channel Mode Logic and Event Flags MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 865 Care must be taken to change channel modes, and is advisable to reset channel flags MRLA/B, TDLA/B and MRLEA/B before writing PDCM, or to UDCM when user-defined mode is selected. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 866 TDL ucode TDL NOTE: all flip-flops but MRLE reset-dominant; all control signals active high. Match A SR TransA SR TransB SR Match B SR Figure 24-40. Either Match, Blocking Modes (em_b_st, em_b_dt) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 867 TDL NOTE: all flip-flops but MRLE reset-dominant; all control signals active high. Match A SR TransA SR TransB SR Match B SR Figure 24-41. Either Match, Non Blocking Modes (em_nb_st, em_nb_dt) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 868 Both Match Request Modes (bm_st, bm_dt) In these modes, match service request is generated only after both match recognitions occurred. By definition this is a non-blocking match mode: match recognitions do not block each other, implementing MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 869 These are ordered match modes on which Match A recognition must precede Match B recognition (ordered 1->2). Match A asserts MRLA and enables Match B and transitions. Match B asserts MRLB, generates a match service request, and blocks both transitions. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 870 Figure 24-44. Ordered Modes with Match B Request (m2_o_st, m2_o_dt) Single match modes (sm_st, sm_dt) Single match modes support single or double transition with single match recognition. MRLB is never set, and MRLEB has no effect. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 871 TDL ucode TDL NOTE: all flip-flops but MRLE reset-dominant; all control signals active high. Match A SR TransA SR TransB SR Match B SR Figure 24-45. Single match modes (sm_st, sm_dt) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 872 Trans. Event A ucode TDL ucode TDL NOTE: all flip-flops but MRLE reset-dominant; all control signals active high. Match A SR TransA SR Match B SR Figure 24-46. Single match enhanced mode (sm_st_e) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 873 Another possible use of this mode is allocating one match recognition for transition timeout and the other for another non-critical timed task, adding functionality to a single channel. Since the transition detection MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 874 If MRLA is negated and MRLB is asserted, the conditional window did not open at all (for example: a time window is open only after a specific angle, otherwise it is not opened). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 875 MRLA assertion until the microcycle on which MRLB is asserted. When TDLA is asserted inside the window range it disables both matches, captures both time bases and generates a transition service request. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 876 TCRCLK input and the filtered input comes from the TCRCLK filter output. The edge is selected by IPACA/B, and is independent of the edge selection by ETPU_TBCR field TCR2CTL. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 877 On an output signal these modes are useful in combination with the ME bit set on the entry point, to define an interlaced operation. For example, each match recognition can set a pin action, and the second pin MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 878 These modes can also be used for deferred pulse generation with microcode service request after its trailing edge (if Match A condition comes after Match B condition). Another option is having Match A recognition MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 879 If it does not, the driver output is probably shorted, and the channel output must be turned off immediately to avoid damaging the device. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 880 Transition detection. Depending on the Channel Mode, these Match and Transition may have conflicting effects on other Transition/Match blocking or enabling. In these cases, blocking always prevails over enabling, effective on the next microcycle. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 881 IPACA:= 100; OPACA:= 100; MatchA:= window open time,input sampling; IPACB:= 000; OPACB:= 001; MatchB:= window close time = MatchA + pulse width; PDCM:= em_nb_dt; enables Match A Match B Input signal Output signal Figure 24-47. Input/Output combination MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 882 SPRAM parameters. All links are negated on reset. 1. That can only happen if the link service request came from the other engine or from the serviced channel itself. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 883 Continuous mode may reject a real signal transition and delay the response to the MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 884 384 / 256 (257 / 383) not avail. 512 / 256 (257 / 511) 768 / 512 (513 / 767) This table shows pulse widths and delays in number of periods of the system clock. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 885: Time Bases
24.5.6 Time Bases Each eTPU engine has two Time Counter Registers, TCR1 and TCR2. They provide 24-bit time bases, shared by all 32 channels. Any channel can use both time bases to: MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 886 TCR1 can be driven externally by the TCRCLK input, after the digital filter. The TCR1 clock source is configured by the TCR1CTL bit, as shown in Figure 24-49. For more information on clock source selection, please refer to Section 24.4.3.1, ETPU_TBCR – eTPU Time Base Configuration Register. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 887 Timer Count Register 2 – TCR2 The TCR2 is a 24-bit counter which can be used in the following modes: • Pin Transition Mode: Count the rise, fall or both transitions of TCRCLK signal. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 888 EAC and Channel 0. The TCRCLK synchronizer is an improved filter that provides best latency while maintaining proper noise filtering (see Section 24.4.3.1, ETPU_TBCR – eTPU Time Base Configuration Register, field TCRCF[1:0]—TCRCLK Signal Filter Control). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 889 (two filter clocks). Otherwise the TCRCLK is filtered with the same filter clock as the channel input signals. For details on TCRCLK and channels digital filter MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 890 EAC operation, the TCRCLK digital filter is used both by the EAC and by channel 0 to get full synchronization between the two logics. The eTPU Angle Counter (EAC) logic runs continuously and updates the TCR2 Angle counter, eliminating the microcode latency in updating the TCR2 value. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 891 STAC Controller, and there may be a client linked to that server by the ETPU_REDCR bits SRV1/2 on each engine. When the server address on the STAC bus matches the value in SRV1/2, the MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 892 = 0. Microcode can always write to TCR1/2 registers, with either value of etpu_gtbe_in. NOTE The timebase prescalers are reset when the GTBE input is negated. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 893: Eac – Etpu Angle Counter
(depending on the ETPU_TBCR field AM) to generate angle information on the TCR2 bus which is passed to all the local engine channels. The EAC helps to implement a digital angle PLL (see Table 24-55), which MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 894 When eTPU is not in angle mode (AM bit is negated in ETPU_TBCR), all angle mode registers can be used as general purpose registers. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 895 The HOLD bit can be used for synchronizing the EAC tooth count, in case that a false physical tooth is detected due to noise. Normal Operation. Force EAC to halt until detection of a physical tooth. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 896 MISSCNT = 0 Missing a physical tooth naturally causes EAC to get into Halt mode. 24.5.7.2.2 TCR2 – Timer Counter 2 In Angle Mode TCR2 counts angle ticks instead of time. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 897 This number, decremented by one, works as a down-counter preload value. A value of INTEGER = 0 represents an integer of 32768. A new value written is reloaded into the counter (becoming effective) when a new tick starts or a tooth is detected or inserted via IPH. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 898 (end of ticks) TCR1<estimated tooth t TCR1>estimated tooth time PHYSICAL TOOTH HIGH RATE MODE HALT MODE N TICKS TCR1>estimated tooth time --> DECELERATION TCR1<estimated tooth time --> ACCELERATION Figure 24-55. EAC “PLL” MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 899 Tooth Program Register Count Contol & High Rate Logic Dummy Tooth Count TCR2 Reset Last Tooth Angle Mode TCR2 Time Base AM (ETPU_TBCR) Angle Counter Logic Figure 24-56. eTPU angle counter system MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 900 0 up to TICKS, is controlled by the Angle Tick Generator logic and cannot be accessed by microcode. Refer to Figure 24-57 for a generic presentation of the angle tick count and the measurement of a single tooth period. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 901 2. The tooth period (TCR1ToothPeriod) is not, in general, the value of estimated tooth time. It is obtained by microcode by subtracting TCR1 values between two teeth detections. Its comparison with the estimated tooth time indicates acceleration (if minor) or deceleration (if greater) to the microcode. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 902 Angle Tick Generator. Count Control logic is responsible for advancing, holding and resetting the TCR2 and Tooth Tick Counter in the proper timing, such that the TCR2 time base will reflect MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 903 The microcode which services the EAC channel physical tooth transition may update TRR according to various conditions to give the best estimation of the current tooth period, according to the previous tooth period and other engine parameters. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 904 TCR1 value during the service time, and TCR1 value captured in the EAC channel due to the physical tooth pin transition. The duration of the Halt mode is obtained using the estimated tooth time. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 905 Rate Mode does not alter the immediate EAC state, but it is still detected by the EAC channel logic and can, therefore, alter future EAC behavior (for instance, closing the tooth detection window (see Section 24.5.7.10, Angle logic and channel modes). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 906 EAC channel capture register which captured TCR1 on the physical pin transition. 1. The effect of microcode writes to fields HOLD and IPH is immediate in High Rate mode. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 907 “dummy” tooth, the Angle Tick Counter is incremented as if there was a physical tooth. A “dummy” tooth can be inserted only during Normal or High Rate operation modes. The microcode inserts “dummy” teeth by writing to the MISSCNT field in TPR. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 908 (either the missing teeth are both last in an engine cycle or both not last, but not last in one engine cycle and first in the next). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 909 The microcode can detect the situation when the acceleration in not realistic, or when immediately after the detection of this extreme acceleration, the following tooth indicates extreme deceleration back to the original RPM. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 910 Angle logic is disabled. The Angle Logic state-machine resets to Normal mode and the tick prescaler to the initial count by AM = 00, but not the microengine registers TPR and TRR. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 911 Because of different results depending on the EAC mode at the time of TPR write, it is not advisable to write 1 to IPH and change TICKS at the same microinstruction. A consistent behavior is obtained if IPH MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 912: Microengine
Latency is worsened when channels from a same eTPU engine contend for microengine service. Figure 24-62 a block diagram of microengine architecture is shown. Microengine features are summarized as follows: MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 913 Section 24.5.8.2, ALU and Post-ALU Shifter. • MDU (MAC/Divide Unit) performs integer MAC, multiply and divide operations. • Fixed Microinstruction Size of 32 bits. • Fixed-length instruction execution (2 system clocks) • Static superscalar operation MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 914 MN, MV, MZ, MC MB Flags to ERTA to Branch Logic Channels + TCRs ERTB MRLA, MRLB, TDLA, TDLB, PSTI, PSTO TCR1 to Branch Logic Microengine’s DataPath TCR2 eTPU CHANNELS Figure 24-62. Microengine Block Diagram MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 915 Section , Indirect addressing mode). The DIOB is automatically loaded with one parameter before the thread starts (parameter preload). For more information see Section 24.5.1.1.5, Entry point format, and Section 24.5.1.2, Time slot transition. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 916 PC when a return from subroutine is executed. The RAR is loaded with value 0x3FFF during TST. For more information about subroutine call and return see Section 24.5.9.4.2, Branch operations, and Section 24.5.9.4.4, Return from subroutine, respectively. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 917 For more information about flag generation, see Section 24.5.9.2.3, Flags sampling control. ALU flags can be used as branch condition (see Section , Conditional/Unconditional branch) or conditional ALU/MDU operation (see Section 24.5.9.2.7, Conditional ALU/MDU operation execution). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 918 Overflow flag behavior for addition is defined in Table 24-61. Overflow flag for Absolute operation is explained in Section 24.5.8.2.8, Absolute value MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 919 ALU adder output can be 1-bit shifted or 1-bit rotated right as follows: Shift right: if BINV==1 result[23:0] = adder_output[24:1] else 1. ALU operations only occur on formats where a destination field is found (T2ABD/T2D). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 920 8 bits rotate right adder carry from bit 7 to bit 8 16 bits rotate right adder carry from bit 15 to bit 16 24 bits rotate right alu_adder_output[24] MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 921 Table 24-66. Types of Bitwise Operations ALUOP BINV Operation 10000 AS | BS 10000 AS | (~BS) 10001 AS ^ BS 10001 AS ^ (~BS) 10010 AS & BS 10010 AS & (~BS) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 922 = AS[31 - BS[4:0]] if C_flag == 1 result = AS | (1 << (31 - BS[4:0])) else result = AS & ~(1 << (31 - BS[4:0])) C_flag = temp_C_flag MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 923 AS bit 23 after size override and sign extension (if any, see Section 24.5.9.2.8, A-Source size override), regardless of A-source register size, is used to check the operand signal and is copied to MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 924 B-source operand BINV Operation performed signed AS mdu_op BS AS mdu_op (-BS) reserved reserved 1. There is no distinct selection of 24-bit fractional multiplication, for it works exactly as a 24-bit ordinary multiplication. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 925 MC and MV flags are reset. MZ is set if result is 0, resets otherwise. MN is set if result is negative. 24.5.8.3.4 Unsigned multiplication (multu) MDU unsigned multiplication is defined as follows: MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 926 MACH and MACL form a 48-bit fixed point number with a 24-bit mantissa, both for 8- and 16-bit operations. To calculate the unsigned numerator of the fractional part (with denominator MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 927 MDU Carry Flag – MC MDU carry flag indicates if the result cannot be represented by a 48-bit number, in Signed and Unsigned Multiply Accumulates. It is reset in the other operations. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 928 Reflects the selected channel (CHAN) 1. Serviced channel does not change during execution of a thread, and it is the channel that requested a service (initial value of CHAN register when a thread starts). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 929: Microinstruction Set
Section 24.5.9.7, Microinstruction formats. Parallelism conflicts may arise when two operations are executed in the same microinstruction. These situations are explained in Section 24.5.9.6, Microinstruction parallelism issues. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 930 Since the SPRAM word address is shifted two bits up in DIOB, its contents hold the same parameter address value used by Host. The equation is: physical_address = DIOB[13:2], or physical_address = (truncated) DIOB / 4 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 931 RSIZ field is not available, SPRAM access will be 24 bits by default. When performing a Zero SPRAM write operation (see Section 24.5.9.1.5, Zero SPRAM operation), RSIZ defines the size of operation regardless of the P/D field (Section 24.5.9.1.2, SPRam source/destination registers). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 932 24-76, thus allowing stack operations. DIOB is incremented and decremented in word addresses, only from bits 15 downto 2, i.e.: the bits 23 to 16 and 1 to 0 are left untouched by STC pre-decrement and post-increment. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 933 In formats without ABSE/ABDE, the field T4BBS determines the register sets used by T2ABD and T4ABS, as shown in Section , Microinstructions Without Fields ABSE and ABDE. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 934 Sizes can be 8, 16 or 24 bits. Registers that are not exactly of one of these sizes are treated as the immediately upper size (e.g., CHAN[4:0] is an 8-bit source). See Section 24.5.9.2.3, Flags sampling control, for more information. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 935 AS[23:0] = MACH[23:0] 1000 AS[23:0] = P[23:0] AS[23:0] = MACL[23:0] 1001 AS[23:0] = A[23:0] AS[4:0]=CHAN[4:0] 1010 AS[23:0] = SR[23:0] AS[14:2] = CHAN_BASE 1011 AS[23:0] = DIOB[23:0] AS[13:0] = ENGINE_BASE 1100 AS[23:0] = TCR1[23:0] Reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 936 T2ABD = 0011 with first register set also writes to MatchB register of the selected channel if field ERWB = 0. if no destination is selected, ALU flags are updated, although the result is lost. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 937 8 bits 8 bits 16 or 24 bits 16 bits 16 bits 16 bits 8 or 16 bits 24 bits 16 bits 8 or 16 bits 16 bits 24 bits 16 bits MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 938 The data selected as second source (T4BBS) can be inverted (bitwise boolean NOT) before operation. This is controlled by microinstruction field BINV (1 bit, Table 24-86). A zero value for BINV activates B-source inversion. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 939 There are three types of shift operations: ALU, post-ALU and Shift Register. ALU shift operations are covered in Section 24.5.9.2.10, ALU/MDU Operation Selection. Post-ALU and Shift Register are covered in the following sections. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 940 The 3-bit field AS/CE allows conditional execution of arithmetic operation, as shown in Table 24-90. The same field can also be used for overriding the size of A-Source (see Section 24.5.9.2.8, A-Source size override). MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 941 Table 24-91. A-Source size override AS/CE Meaning A-source size override to 8 bits A-source size override to 16 bits Used for conditional execution (see Section 24.5.9.2.7, Conditional ALU/MDU operation execution) execute unconditionally/no size override MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 942 Section 24.5.8.3, MAC and Divide Unit (MDU). Table 24-94. ALU Operation Selection – ALUOP ALUO Operation Comment 00000 AS mults BS[7:0] signed multiplication 00001 AS multu BS[7:0] unsigned multiplication 00010 AS fmults BS[7:0] signed fractional multiplication MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 943 AS determined by BS[4:0] 11110 AS clrb BS[4:0] clear bit in AS determined by BS[4:0] 11111 n.a. RESERVED Addition/Subtraction is selected by field BINV (see Section 24.5.9.2.4, B-Source inversion) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 944 AD[7:0] = AS[7:0] | #imm8, AD[23:8] = bitwise OR AS[23:8] 01001 AD[7:0] = AS[7:0] ^ #imm8, AD[23:8] = bitwise XOR AS[23:8] 01010 AD[7:0] = AS[7:0] & #imm8, AD[23:8] bitwise AND = AS[23:8] MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 945 8 for #imm8=2; 16 for #imm8=3 11100 AS exch #imm8[4:0] exchange C flag and AS bit determined by #imm8[4:0] (see Section 24.5.8.2.6, Exchange bit) 11101 n.a. reserved 11110 n.a. reserved 11111 n.a. reserved MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 946 Match TB selection TBSA[3] = 0 greater or equal TCR1 TCR1 equal-only TCR2 TCR2 action set OBE = 1 TBSA[3] = 1 set OBE = 0 do nothing reserved all other values MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 947 Match A is used for IPACA/OPACA, and Match B for IPACB/OPACB. 24.5.9.3.4 Immediate pin state control It is possible to change output signal state immediately by using PSC (2 bits) and PSCS (1 bit) fields. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 948 MRLA, MRLB (1 bit each) and TDL (1 or 2 bits, depending on the format). The flags cleared by these microcode fields are the actual channel flags, and also the ones sampled into the branch logic. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 949 Matches 1 and 2, as shown in Table 24-106. Table 24-106. Two-bit MRLE MRLE Meaning Disable Match A (clear MRLEA) Disable both Matches (clear MRLEA and MRLEB) Disable Match B (clear MRLEB) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 950 Table 24-108. Predefined Channel Modes PDCM Channel mode 0000 em_b_st 0001 em_b_dt 0010 em_nb_st 0011 em_nb_dt 0100 m2_st 0101 m2_dt 0110 bm_st 0111 bm_dt 1000 m2_o_st 1001 m2_o_dt 1010 user-defined channel mode 1011 reserved 1100 sm_st MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 951 DIOB register. Flow Control microoperations are also provided to repeat a given microinstruction, to finish the current thread execution, and to halt the microengine. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 952 BCC is false branch if condition determined by BCC is true Table 24-113. Branch Condition Selection – BCC Meaning Meaning 001110 Flag 0 001111 Flag 1 100000 V ALU flag 110000 PSS channel flag MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 953 (see Section 24.5.9.4.4, Return from subroutine). Table 24-114. Return and Dispatch – R/D Meaning return from subroutine (see Section 24.5.9.4.4, Return from subroutine) dispatch jump dispatch call don’t change microinstruction flow MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 954 / call / dispatch jump / dispatch call / return is executed do not flush pipeline when jump / call / dispatch jump / dispatch call / return is executed MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 955 HALT case. If the microengine decodes an illegal instruction, the following actions are taken: • a Global Exception is issued. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 956 Table 24-117. DIOB load from SPRAM and ALU DIOB selected as DIOB selected as DIOB load value SPRAM read destination? ALU destination? DIOB, --DIOB (pre-decrement), or DIOB++ (post-increment) SPRAM read data (post-inc and pre-dec ignored) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 957 If ERTA/B is the destination of an ALU operation at the same instruction, MatchA/B gets the ALU result (see Section 24.5.9.6.3, ERTA/B as ALU destination and ERWA/B), but the ERTA/B not being written still receives the old MatchA/B values. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 958 CHAN. When a pin action is commanded through PCS/PSCS and a CHAN assignment is done simultaneously, the output signal affected is selected with the old CHAN value. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 959 Enhanced Time Processing Unit (eTPU2) 24.5.9.7 Microinstruction formats Table 24-118. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 960 Table 24-118. Microinstruction Formats format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 IMM[15:13] IMM[7:2] IMM[23:16] IMM[11:9] T4ABS T2ABD CCSV ALUOP AS/CE ALUOP I[3:2] I[1:0] [1:0]...
Page 961 Table 24-118. Microinstruction Formats (continued) format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 1 1 BCC[4:0] BAF[13:0] AID[2:0] rsv SMPR format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ALU Operations Channel Control/Config Operations RAM Operations...
Page 962: Test And Development Support
CBT = 0 it halts immediately. As a particular case, microengines come halted out of reset if device debug request is asserted, since CBI reset value is 1. Microengine does not execute out of reset, MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 963 SPRAM read and/or write to a given address and/or write data. The breakpoint is always qualified by the SPRAM address, but the following variations are allowed: — break on write only, read only, or read-and-write. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 964 When a thread is ending, it goes to Idle or TST only if there is neither a hardware breakpoint request (signal ndedi_thread_break negated) nor a request to stop (MDIS = 1 or device debug request = 1). When thread is ending and there are simultaneous hardware breakpoint (ndedi_thread_break active) and stop MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 965 NOP, and load PC with the address of the removed breakpoint. So, when halt state is suspended, the original microinstruction will be fetched while NOP is executed, and program flow continues normally from then on. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 966 PC+P or RAR, respectively. If branch condition is not satisfied, PC value stays unaltered. The flush control (field FLS) also works, so that a successful forced branch with flush replaces the prefetched MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 967 SCM ROM replacement by Emulation RAM is MCU-dependent. The SCM may even be divided into a ROM part and a RAM part. In this case, both MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 968 Both microengines in idle state (no channel is being serviced) or stopped, in any combination (e.g., engine 1 idle with engine 2 stopped) • ETPU_MCR bit VIS = 0 • ETPU_MCR bit SCMMISEN = 1 MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 969: Initialization/Application Information
(FM bits). • Write to SPRAM for parameter initialization of each configured channel. 1. Except when device debug request is asserted on power-on reset: in this case, the microengines wake-up in halt state. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 970: Reset Options
Also note that for transfers of a pair of parameters, the 1. This operation is done before enabling active channels to avoid time events happening before the channel initialization. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 971: Programming Hints And Caveats
This mechanism can be combined with finite (timed out) loops for better latency. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 972: Estimating Worst-Case Latency
WCL analysis should be applied. The second-pass analysis is not a generalized formula, but rather uses specific system details for a realistic worst-case estimation. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 973 Since there is only one eTPU Microengine (in each eTPU engine), the eTPU cannot actually execute the software for multiple functions simultaneously. However, the hardware for each of the channels is MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 974 5 requests service from the eTPU Microengine to execute thread 2. A PWM wave is kept running on the system by the eTPU executing thread 2, then thread 3, then thread 2, then thread 3, and so on. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 975 24-67). Note that in eTPU, when no service request exists, the scheduler goes to thread 1, but WCL calculation considers full load. Time Slot Transitions (10 CPU Clock Cycle Each) Time Slots of Varying Lengths Figure 24-66. Time-slot sequence MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 976 Each channel has two register bit: a service request register (SRR) and a service grant register (SGR). The SRR is set when a channel requests service. After the channel has been granted service, the SGR is set and the SRR is cleared. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 977 RAM. Also coherent Microengine to Microengine communication of more than one parameter may be rare. To find a realistic RCR, CPCR the system designer should evaluate the Host code and find MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 978 SGRs. The worst-case latency is the time from the end of the channel’s service until the end of the channel’s next service. See Figure 24-68. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 979 Worst-Case Latency Channel X Other Channels Serviced Channel X Channel X Serviced Next Serviced Figure 24-68. First-pass worst-case latency To estimate worst-case latency: • Find the worst-case service time for each active channel. • Using the H-M-H-L-H-M-H time-slot sequence, map the channels that are granted for each time slot. •...
Page 980 Table 24-120. Longest threads and RAM accesses for old TPU functions (continued) Function Longest thread RAM accesses SPWM Mode 0 Mode1 Mode 2 20 (no linking) 22 (linking Angle-Angle Mode Angle-Time Mode PPWA Mode 0 Mode 1 Mode 2 Mode 3 Assumes one master and one slave.
Page 981 Figure 24-69. Next Servicing for Channel 0 Channel 1 will be serviced in the middle-priority time slot before channel 0 is serviced again. 3. Add time for the six-clock CPU time-slot transitions. See Figure 24-69 Table 24-122. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 982 Figure 24-70 Table 24-123. Table 24-123. Worst-case latency for channel 1 Two Channel 0 worst-case service times 50 clocks Channel 1 worst-case service time 46 clocks Channel 2 worst-case service time 11 clocks MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 983 Two Channel 1 worst-case service time 92 clocks Channel 2 worst-case service time 11 clocks Seven 6-clock time-slot transitions 42 clocks Total clocks 245 clocks 245 clocks * 25 ns/clock = 6125 ns MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 984 For example, when estimating WCL for a high-priority channel, do not start the mapping in the last high-priority slot in a seven-slot sequence, as that is a best case for a high-priority channel since another high-priority time slot is next. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 985 Table 24-125. First-Try system configuration Channel Priority Function High PWM at 50 kHz (needs a 4-µs WCL) High PWM at 50 kHz (needs a 4-µs WCL) High PWM at 5 kHz (needs a 40-µs WCL) MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 986 Conclusion: with this system configuration, worst-case latencies for channels 0 and 1 are too high (WCL for channel 1 is the same as WCL for channel 0). Try a different system configuration. Second-Try system configuration The second-try system configuration is shown in Table 24-126. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 987 Figure 24-74. Worst-case latency for channel 2 Conclusion: with this system configuration, the WCL for channels 2 and 8 is 4.7 ms, which is within the 40 and 80 ms WCL requirements. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 988: Endianness
4*n + 3 24.7 Appendices 24.7.1 Microcycle and I/O timing 24.7.1.1 Execution and channel timing Figure 24-75 shows the main timings related to microinstruction execution when channels and timebases run on T2 timing. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 989 Pre-fetch uInstr uInst uInst uInst = Set Pin Execution Pin Action Updated Pin Value due uInstr Note: *TCR clock/prescaler selection = 4x system clock Figure 24-75. Execution, Timebase and Channel T2 Timing MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 990 T2 and T4. Thus, the eTPU has two types of timing states: MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 991 Figure 24-77. T2 timing WAIT-T4 T CLOCKS SYS.CLOCK PC A1 INST (A1) (A1) (A2) Figure 24-78. T4 timing 24.7.1.2 Input/Output signal delays The synchronizer, filter and edge detection logic delay the input signal transitions. MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 992: Initialization Code Example
#define ETPU_CDTRER_1_OFFSET 0x250 //Data TransF Interrupt Enable Register //channel0 configuration registers #define ETPU_C0CR_1_OFFSET 0x400 //Channel0 Configuration Register #define ETPU_C0SCR_1_OFFSET 0x404 //Channel0 Status Control Register #define ETPU_C0HSRR_1_OFFSET 0x408 //Channel0 Host Service Req. Register MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 993 0x00000200 //SCM MISC enable #define VIS 0x00000040 //SCM visibility #define GTBE 0x00000001 //Global time base enable //ETPU_TBCR_1 fields - Time Base Configuration Register #define TCRCLK_FILTER_TWOSAMPLE 0x00000000 //TCRCLK filter in Two sample mode MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 994 ETPU_C0SCR_1 = (FUNCTION_MODE(0)); // no parity for transmitter ETPU_C1SCR_1 = (FUNCTION_MODE(0)); // no parity for receiver //write to spram for parameter initialization of each configured //channel MATCH_RATE_TX = MATCH_RATE_TRANS(0x412); //setup match rate for transmitter MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 995: Predefined Channel Mode Summary
DATA_UART_TX = DATA_WORD_TX(0x000000AA); //load first byte to be transmitted=AA DATA_SIZE_TX = DATA_SIZE_TRANS(8); //8-bit data word for transmitter MATCH_RATE_RX = MATCH_RATE_REC(0x412); //setup match rate for receiver DATA_SIZE_RX = DATA_SIZE_REC(8); //8-bit data word for receiver //Write to Channel host service request registers(ETPU_CxHSRR) to //initialize active channels(Channel 0 and 1) ETPU_C0HSRR_1 = HOST_SERV_REQ(3);...
Page 996 There are three columns for each event: one for event type, one for enable/disable actions and one for capture. Event type column can be matchA, matchB, transA and transB (for double transition modes). Enable/disable actions column (identified as “[blocks](enables)” in column head) specifies which other events are enabled or disabled. Initially disabled events (specified in “initially blocked”...
Page 997 Table 24-129. Predefined channel mode summary 1st event 2nd event 3rd event 4th event initially Mode [blocks] [blocks] [blocks] [blocks] blocked event type Capt. event type Capt. event type Capt. event type Capt. (enables (enables) (enables) (enables) em_nb_st none matcha/b none matchB/A none...
Page 998 Table 24-129. Predefined channel mode summary (continued) 1st event 2nd event 3rd event 4th event initially Mode [blocks] [blocks] [blocks] [blocks] blocked event type Capt. event type Capt. event type Capt. event type Capt. (enables (enables) (enables) (enables) m2_st transA matchA (transA) matchB...
Page 999: Misc Algorithm
/* final signature calculated */ The value calculated by this algorithm must be loaded into register ETPU_MISCCMPR prior to activating the SCM MISC calculator in eTPU. Once the MISC calculator is activated (bit SCMMISEN in register MPC5644A Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
Page 1000 1. eTPU MISC hardware is optimized to read 32-bit words from memory and to calculate this CRC in parallel, rather than shifting one bit at a time. The actual implementation inside eTPU, although bringing to the same results, does not match exactly the algorithm shown here. MPC5644A Microcontroller Reference Manual, Rev. 6 1000 Freescale Semiconductor...

NXP Semiconductors MPC5644A Reference Manual

Chapter 1

Chapter 15 Interrupt Controller

Chapter 13

Memory Protection Unit (MPU)

Chapter 12 Flash Memory

Chapter 33 Flexray

Chapter 19 Software Watchdog Timer (SWT)

Chapter 18 Error Correction Status Module (ECSM)

Chapter 35 Power Management Controller (PMC)

Chapter 38 Development Trigger Semaphore (DTS)

Chapter 3

Chapter 2

Chapter 4

Chapter 5 Clock Architecture

Chapter 6

Chapter 7

Chapter 8 Edma Basic Data Flow

Chapter 9

Chapter 10

Chapter 11

Chapter 23

Chapter 16

Chapter 17

Chapter 21

Chapter 22

Chapter 24

Chapter 25

Quick Links

Related Manuals for NXP Semiconductors MPC5644A

Summary of Contents for NXP Semiconductors MPC5644A