Reacm Global Error Flag Register (Reacm_Gefr) - NXP Semiconductors MPC5644A Reference Manual

Microcontroller
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Reaction Module (REACM)
Field
0–11
Reserved, should be cleared.
12–15
TAG value
ADC_TAG
The ADC_TAG[3:0] represents the TAG for the ADC conversion which is used by the Reaction
[3:0]
Module to select the reaction channel to execute the modulation.
16–31
ADC conversion result value
ADC_RESULT
The ADC_RESULT[15:0] represents the value resulting from an ADC conversion. This value is
[15:0]
used for the Reaction Channel Modulation process or for capturing by the Threshold Bank.
23.3.6

REACM Global Error Flag Register (REACM_GEFR)

The REACM Global Error Flag Register (REACM_GEFR) helps the software in the resolution of error
conditions signaled by the reaction channels. This allows a faster service in error handling. This register
mirrors the Error Flag in the REACM Channel n Status Register (REACM_CHSRn).
Address: REACM_BASE (0xC3FC_7000) + 0x0020
0
1
2
R OVR
0
0
W
Reset
0
0
0
16
17
18
R
0
0
0
W
Reset
0
0
0
Figure 23-8. REACM Global Error Flag Register (REACM_GEFR)
Field
0
Overrun Detection Flag
OVR
The OVR flag is used to indicate that an overrun condition was detected at the ADC Interface. See
Section 23.4.6, ADC
1 Overrun detected
0 Overrun not detected
1–25
Reserved, should be cleared.
26–31
Error Flag
EFn
The EFn error flag bit indicates an error condition occurred in channel n. This bit is provided for a
fast channel error resolution in the Reaction module. The condition could be any error indicated by
MAXL, OCDF, SCDF, SQER, RAER, or TAER error flags as described in
Channel n Status Register
corresponding channel flags are all cleared.
702
Table 23-7. REACM_SINR field descriptions
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
19
20
21
22
23
0
0
0
0
0
0
0
0
0
0
Table 23-8. REACM_GEFR field descriptions
interface.
(REACM_CHSRn). The EFn bit is automatically cleared if the
MPC5644A Microcontroller Reference Manual, Rev. 6
Description
8
9
10
11
0
0
0
0
0
0
0
0
24
25
26
27
0
0
EF5
EF4
0
0
0
0
Description
Access: User read/write
12
13
14
15
0
0
0
0
0
0
0
0
28
29
30
31
EF3
EF2
EF1
EF0
0
0
0
0
Section 23.3.8, REACM
Freescale Semiconductor

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