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Enhanced Time Processing Unit (eTPU2)
24.4.6.6
ETPU_CDTRER – eTPU Channel Data Transfer Request Enable Register
Data Transfer request enable (see
are grouped in ETPU_CDTRER. These bits are mirrored from the Channel Configuration registers (see
Section 24.4.7.1, ETPU_CxCR – eTPU Channel x Configuration
Offset: eTPU_A: eTPU_Base + 0x250; eTPU_B: eTPU_Base + 0x254
0
1
R DTR
DTR
E
E
W
31
30
Reset
0
0
16
17
R DTR
DTR
E
E
W
15
14
Reset
0
0
= Unimplemented or Reserved
Field
0-31
DTREx—Channel x Data Transfer Request Enable
1: Data Transfer request enabled for channel x.
0: Data Transfer request disabled for channel x.
For details about interrupts see
798
Section 24.5.2.2, Interrupts and data transfer
2
3
4
5
6
DTR
DTR
DTR
DTR
DTR
E
E
E
E
E
29
28
27
26
25
0
0
0
0
0
18
19
20
21
22
DTR
DTR
DTR
DTR
DTR
E
E
E
E
E
13
12
11
10
9
0
0
0
0
0
Figure 24-18. ETPU_CDTRER Register
Table 24-28. ETPU_CDTRER field description
Section 24.5.9.3.10, Channel interrupt and data transfer
MPC5644A Microcontroller Reference Manual, Rev. 6
Register).
7
8
9
10
11
DTR
DTR
DTR
DTR
DTR
E
E
E
E
E
24
23
22
21
20
0
0
0
0
0
23
24
25
26
27
DTR
DTR
DTR
DTR
DTR
E
E
E
E
E
8
7
6
5
4
0
0
0
0
0
Description
requests) from all channels
Access: User read/write
12
13
14
15
DTR
DTR
DTR
DTR
E
E
E
E
19
18
17
16
0
0
0
0
28
29
30
31
DTR
DTR
DTR
DTR
E
E
E
E
3
2
1
0
0
0
0
0
requests.
Freescale Semiconductor
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