Memory Map/Register Definition - NXP Semiconductors MPC5644A Reference Manual

Enhanced Time Processing Unit (eTPU2)
a programmed value. The clock and operation submode of the TCRCLK filter is configured independently
of the other channel input filters, through the field ETPU_TBCR[TCRCF].
For more information on filter submodes, refer to
Angle Modes, the output of the digital filter of channel 0 is replaced with the output of TCRCLK signal
digital filter (see Section 24.5.7, EAC – eTPU angle
24.3.2.4 ipp_ind_etpu_odis_[1|2]([0 – 3]) eTPU Channel Output Disable Signals
Each of these four input signals are used to force the outputs of a group of eight channels to an inactive
level. When an ODIS input is active, all the channels in its group of eight that have their bits ODIS = 1 in
ETPU_CxCR have their outputs forced to the opposite of the value specified in bit OPOL of the same
register. Therefore, channels can be individually selected to be affected by the output disable signals, as
well as their disabling forced polarity (see
The output disable channel groups are defined in
1
The ETPU2 output_disable signals ipp_ind_etpu_odis_1(0 to 3) are connected to the EMIOS
channel _flags_ (channel 11 to 8) respectively.
In a dual-engine eTPU there are 8 output disable signals for the 64 channels.
24.4

Memory map/register definition

The guideline for the description of all bits and fields throughout
definition, is to provide only a brief explanation (without examples or method of use) of the features, since
it will be used mainly as a reference for the reader that is studying
where those features are explained in detail.
24.4.1 Memory map
The eTPU System simplified memory map is shown in
have their own reserved address areas.
Table 24-4 shows a detailed memory map. Offsets are relative to the eTPU base address, which is
MCU-dependent.
For MPC5644A, the eTPU2 base address is 0xC3FC_0000.
760
Section 24.5.6.5, TCRCLK digital
counter).
Figure 24-37).
Table
Table 24-2. Output disable channel groups
1
Output disable signal
ipp_ind_etpu_odis_[1|2](0)
ipp_ind_etpu_odis_[1|2](1)
ipp_ind_etpu_odis_[1|2](2)
ipp_ind_etpu_odis_[1|2](3)
NOTE
MPC5644A Microcontroller Reference Manual, Rev. 6
24-2.
Channels
8 to 15
16 to 23
24 to 31
Section 24.4, Memory map/register
Section 24.5, Functional
Table 24-3. Each of the register areas shown may
filter. In one of the
0 to 7
description,
Freescale Semiconductor