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Frequency-modulated phase locked loop (FMPLL)
Field
24
Mode of operation
MODE
This bit indicates whether the FMPLL is working in bypass mode or normal mode. The reset value
indicates bypass mode. In legacy mode (FMPLL_ESYNCR1[EMODE] negated), the MODE bit will change
to normal mode at the first time the FMPLL_SYNCR is written. In enhanced mode
(FMPLL_ESYNCR1[EMODE] asserted), the MODE bit reflects the value of the CLKCFG[0] bit of the
FMPLL_ESYNCR1.
0 Bypass mode
1 Normal mode
25
Mode select
PLLSEL
In previous MCUs of the MPC5500 family, this bit was used to differentiate between dual controller mode
and normal mode (negated in bypass or dual controller mode, asserted in normal mode). Dual controller
mode is not supported, therefore in legacy mode this bit resets to '0' (bypass), but changes to '1' (normal
mode) at the first time the FMPLL_SYNCR is written. In enhanced mode, the MODE bit reflects the value
of the CLKCFG[1] bit of the FMPLL_ESYNCR1.
0 Legacy mode: bypass or dual controller; enhanced mode: PLL off
1 Legacy mode: normal; enhanced mode: PLL on
26
FMPLL reference source
PLLREF
This bit indicates whether the FMPLL reference is from a crystal oscillator or from an external clock
generator. The reset value is determined by the state of the PLLREF pin. In legacy mode, the reset value
captured from the PLLREF pin cannot be changed anymore after reset. In enhanced mode, the PLLREF
bit reflects the value of the CLKCFG[2] bit of the FMPLL_ESYNCR1.
0 External clock reference
1 Crystal oscillator reference
27
Sticky FMPLL lock status bit
LOCKS
This bit is set by the lock detect circuitry when the FMPLLL acquires lock after one of the following:
• A system reset
• A write to the FMPLL_SYNCR in legacy mode which changes the PREDIV or MFD fields
• A write to the FMPLL_ESYNCR1 in enhanced mode which changes the EMODE, EPREDIV, EMFD or
CLKCFG[1:2] fields
Whenever the FMPLL loses lock, LOCKS is cleared. LOCKS remains cleared even after the FMPLL
relocks, until one of the three previously stated conditions occurs. Coming in bypass mode from system
reset, LOCKS is asserted as soon as the FMPLL has locked, even if normal mode was not entered yet. If
the FMPLL is locked, going from normal to bypass mode does not clear the LOCKS bit.
0 FMPLL has lost lock since last system reset or last write to PLL registers which affect the lock status.
1 FMPLL has not lost lock.
28
FMPLL lock status bit
LOCK
Indicates whether the FMPLL has acquired lock. FMPLL lock occurs when the synthesized frequency
matches to within approximately 4% of the programmed frequency. The FMPLL loses lock when a
frequency deviation of greater than approximately 16% occurs. The flag is also immediately negated when
the PREDIV or MFD fields of the SYNCR are changed in legacy mode, or when EMODE, EPREDIV,
EMFD or CLKCFG[1:2] are changed in enhanced mode, and then asserted again when the PLL regains
lock. If operating in bypass mode, the LOCK bit is still asserted or negated when the FMPLL acquires or
loses lock.
0 FMPLL is unlocked.
1 FMPLL is locked.
568
Table 17-7. SYNSR field descriptions (continued)
Description
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
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