Endianness - NXP Semiconductors MPC5644A Reference Manual

Enhanced Time Processing Unit (eTPU2)
Notice that channels 2 and 8 are well within their WCL requirements. The system could be reconfigured
as shown in Table 24-127
within their WCL requirements.
Table 24-127. Second-try system with channel 0 and 1 reconfigured
Channel
0
1
2
8
15
1
0% RAM collision rate
2
CPU clock rate = 40 MHz, or 60 ns per clock period
24.6.6

Endianness

The address of the 24-bit parameters and the most significant byte depends on the endianness of the MCU.
Table 24-128 shows the parameter addresses for big and little endian machines.
32-bit parameter's most significant byte
24-bit parameter's most significant byte
Least significant byte
24.7 Appendices
24.7.1 Microcycle and I/O timing
24.7.1.1 Execution and channel timing
Figure 24-75 shows the main timings related to microinstruction execution when channels and timebases
run on T2 timing.
988
to give channels 0 and 1 a larger margin while still keeping channels 2, 8 and 15
Priority
High
High
Middle
Low
Low
Table 24-128. Parameter addresses and endianness
Parameter
32-bit
24-bit
MPC5644A Microcontroller Reference Manual, Rev. 6
,
1 2
Function
PWM at 50 kHz (needs a 10-µs WCL)
PWM at 50 kHz (needs a 10-µs WCL)
PWM at 5 kHz (needs a 40-µs WCL)
PPWA at 5 kHz (needs an 80-µs WCL)
DIO as input at rate of 1 ms
Byte address offset (n = word address offset)
Big endian
4*n
4*n + 1
4*n
4*n + 1
4*n + 3
Little endian
4*n
4*n + 3
4*n + 2
4*n
Freescale Semiconductor