NXP Semiconductors MPC5644A Reference Manual page 773

Field
17-23 PARAM0[6:0]—Channel Parameter number 0
This field, in concatenation with CTBASE[4:0], determines the word address offset (from the SPRAM
base) of the parameters that are destination or source (defined by WR) of the coherent transfer. The word
SPRAM address offset of the parameters are {CTBASE, PARAM0}.Note that PARAM0 and PARAM1 allow
non-contiguous parameters to be transferred coherently. The parameter pointed by {CTBASE, PARAM0}
is the first transferred.
24 WR—Read/Write selection
This bit selects the direction of the coherent data transfer.
1: Write operation. Data transfer is from the PB to the selected parameter RAM address.
0: Read operation. Data transfer is from the selected parameter RAM address to the PB.
25-31 PARAM1[6:0]—Channel Parameter number 1
This field, in concatenation with CTBASE[4:0] determines the word address offset (from the SPRAM base)
of the parameters that are destination or source (defined by WR) of the coherent transfer. The word
SPRAM address offset of the parameters are {CTBASE, PARAM1}.Note that PARAM0 and PARAM1 allow
non-contiguous parameters to be transferred coherently. The parameter pointed by {CTBASE, PARAM0}
is the first transferred.
24.4.2.3 ETPU_MISCCMPR – eTPU MISC Compare Register
The eTPU includes a feature called the Multiple Input Signature Calculator (MISC) which comprises
hardware that sequentially reads all Shared Code Memory (SCM) and calculates a 32-bit CRC signature.
The ETPU_MISCCMPR stores the 32-bit expected value to be compared to the signature generated by the
MISC.
The sequence is as follows:
1. The host loads the ETPU_MISCCMPR with the expected value to be found at the end of the MISC
cycle
2. The host starts signature calculation by writing bit SCMMISEN = 1 in the ETPU_MCR. The
MISC zeroes the signature accumulator and starts reading SCM data and calculating the signature.
3. After last SCM position is read, MISC compares the value in the signature accumulator against the
value in the ETPU_MISCCMPR. If there is a mismatch, the MISC stops, issues a Global Exception
and the SC MM I SF bit in the ETPU_MCR assumes value 1. If no mismatch is found, MISC
repeats the procedure automatically.
Freescale Semiconductor
Table 24-6. ETPU_CDCR field description
Description
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Time Processing Unit (eTPU2)
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