NXP Semiconductors MPC5644A Reference Manual page 114

Operating Modes and Clocking
Block name
DSPI_B
DSPI_C
DSPI_D
EBI
eTPU
FlexCAN A
FlexCAN B
FlexCAN C
eMIOS
eSCI_A
eSCI_B
eSCI_C
Decimation Filter
Red Line Module
NPC
Flash Memory Array
1
The MDIS bit default reset value is zero.
5.3.4.5.2 Halt clock gating
Software controlled clock gating can be done via the centralized halt mechanism. The SIU_HLT register
bits corresponding to individual modules are configured to determine which modules are clock gated.
The SIU_HLT register bits are used to drive a stop request signal to the modules. After the module
completes a clean shut down, the module asserts a stop acknowledge handshake signal that is used to gate
the clock to the module (see
SIU_HLTACK read-only register bits.
The halted modules recover when the corresponding SIU_HLT register bit is cleared by software. Once
the bit is cleared, logic will re-enable the clocks to the modules and then negate the stop request signal after
the required timing has been met.
5.3.4.5.3 CPU clock gating
The SIU_HLT register has a bit to halt the clock to the CPU, but in order to prevent accidental CPU halting,
a stop request is only activated if the CPU is in wait state due to the execution of the WAIT instruction.
To gate the CPU clock you need to first program the SIU_HLT register bit
assigned for CPU and then execute the CPU WAIT instruction.
114
Table 5-2. MDIS support
Register name
DSPI_B_MCR
DSPI_C_MCR
DSPI_D_MCR
EBI_MCR
ETPUECR_1
FLEXCAN_A_MCR
FLEXCAN_B_MCR
FLEXCAN_C_MCR
EMIOS_MCR
eSCI_A_SCICR3
eSCI_B_SCICR3
eSCI_C_SCICR3
DECFILTERMCR
TBD
NPC_PCR
FLASH_MCR
Figure 5-7). The stop acknowledge signals are also captured in the
NOTE
MPC5644A Microcontroller Reference Manual, Rev. 6
1
Bit name
MDIS
MDIS
MDIS
MDIS
MDIS
MDIS
MDIS
MDIS
MDIS
MDIS
MDIS
MDIS
MDIS
MDIS
MCKO_EN, MCKO_GT
STOP
Freescale Semiconductor