Loss Of Clock - NXP Semiconductors MPC5644A Reference Manual

controller then waits four clock cycles before negating RSTOUT, and the associated bits/fields are updated
in the SIU_RSR. In addition, SIU_RSR[LLRS] is set, and all other reset status bits in the SIU_RSR are
cleared. Refer to Section 17.5.3, Lock detection,
4.5.4

Loss of clock

A Loss of Clock Reset occurs when the Clock Quality Monitor Module (CQM) detects a failure in either
the reference signal or FMPLL output, and the Loss of Clock Reset Enable (LOCRE) bit in the SYNCR is
set. The internal reset signal and RSTOUT pin are asserted. The value on the WKPCFG pin is applied at
the assertion of the internal reset signal (assertion of RSTOUT), as is the PLLREF value. Once the Loss
of Clock reset request signals is negated, the reset controller waits for a predetermined number of clock
cycles (refer to Section 4.3.2,
BOOTCFG[0:1] pins are sampled. The reset controller then waits four clock cycles before negating
RSTOUT, and the associated bits/fields are updated in the SIU_RSR. In addition, SIU_RSR[LCRS] is set,
and all other reset status bits in the SIU_RSR are cleared. Refer to
information on loss of clock.
The CQM module, when enabled, can generate either a system reset or an interrupt signal (refer to
Section 17.5.4, Loss-of-clock detection,
4.5.5 Core watchdog timer/debug reset
There are two watchdog timer resets: A core watchdog and a platform watchdog.
A Core Watchdog Timer Reset occurs when the e200z4 core watchdog timer is enabled (the e200z4 core
watchdog is counting core clocks, which is different than the peripheral/platform clocks), and a time-out
occurs with the Enable Next Watchdog Timer (EWT) and Watchdog Timer Interrupt Status (WIS) bits set
in the Timer Status Register, and with the Watchdog Reset Control (WRC) field in the Timer Control
Register configured for a reset. SIU_RSR[WDRS] is also set when a debug reset command is issued from
a debug tool. To determine whether SIU_RSR[WDRS] was set due to a Watchdog Timer or Debug Reset,
see the WRS field in the e200z4 core Timer Status Register.
The effect of a Watchdog Timer or Debug Reset request is the same for the reset controller. The internal
reset signal and RSTOUT pin are asserted. The value on the WKPCFG pin is applied at the assertion of
the internal reset signal (assertion of RSTOUT), as is the PLLREF value. Once the Watchdog Timer/Debug
reset request is negated and the FMPLL Loss of Lock reset request signal is negated, the reset controller
waits for a predetermined number of clock cycles (refer to
finishes the reset configuration pins are sampled. The reset controller then waits four clock cycles before
negating RSTOUT, and the associated bits/fields are updated in the SIU_RSR. In addition,
SIU_RSR[WDRS] is set, and all other reset status bits in the SIU_RSR are cleared.
Refer to the e200z4 Power Architecture
Register and Timer Control Register, as for more information on the core watchdog timer and debug
operation. Refer to Chapter 20, Software Watchdog Timer
watchdog.
Freescale Semiconductor
for more information on loss of lock.
RSTOUT). Once the clock count finishes, the WKPCFG and
for details).

Core Reference Manual for descriptions of the Timer Status
MPC5644A Microcontroller Reference Manual, Rev. 6
Section 17.5.3, Lock detection,
Section 4.3.2, RSTOUT). Once the clock count
(SWT), for more information on the platform
Resets
for more
99