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Operating Modes and Clocking
exit this mode are also listed. See the "Modes of Operation" section of the individual module for a
description of how the Module Disable Mode affects the behavior of the module.
5.2.3.2
Module halt mode
Module Halt mode is a low power mode in which the clock to all registers within each module can be
completely halted. The control of the clock gating is centralized in the SIU_HLT register, which has one
control bit for each module to be halted. The CPU itself can also be halted.
5.2.3.3
Standby mode
In this mode, the power is removed from all functions except the standby RAM. Standby mode is entered
by removing all power supplies except the one on the VSTBY pin. The device is recovered from the
standby mode when powered again; see
5.3
Clock architecture
The following sections detail the MPC5644A clocking architecture.
5.3.1
Overview
This section describes different sources for the system clocks. The MPC5644A clocking architecture
consists of the following:
•
On-chip MHz oscillator: Range (4–40 MHz)
•
Relaxation oscillator (RCOSC): 16 MHz
•
Phase-locked loop (PLL): VCO range (256–512 MHz)
•
PLLREF top level pin to control PLL reference
•
Clock quality monitor
•
System Clock Divider (SYSDIV) used to further reduce the system clock frequency
•
Register to control system clock source and programming of PLL parameter
•
Clock gating for individual modules controlled by either SIU_HLT register or module's MDIS
register bit
106
Chapter 4, Resets
MPC5644A Microcontroller Reference Manual, Rev. 6
for more information.
Freescale Semiconductor
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