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Enhanced Time Processing Unit (eTPU2)
This sequence scheme gives higher-priority channels more service time than lower-priority channels.
High-priority channels are allocated four of seven time slots, middle-priority channels are allocated two
of seven time slots, and low-priority channels are allocated one of seven time slots.
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24.6.5.3.1
Priority passing
If no channel of the priority level assigned to the time slot is requesting service, the eTPU scheduler can
pass priority to other levels. If no high-level channel is requesting service during a high level time slot, a
middle-level channel is granted service; or, if no middle level-channel is requesting service, a low-level
channel is granted service. If no middle-level channel is requesting service during a middle-level time slot,
a high-level channel is granted service; or, if no high-level channel is requesting service, a low-level
channel is granted service. If no low-level channel is requesting service during a low-level time slot, a
high-level channel is granted service; or, if no high-level channel is requesting service, a middle-level
channel is granted service. If no channel is requesting service, the time slot sequence is reset to state 1 and
the scheduler idles until a request is received.
Priority passing is implemented in hardware and does not contribute to worst-case latency.
24.6.5.3.2
Time-slot transition
After each time slot, the eTPU must prepare for the next time slot. This preparation time between each
time slot is called a time-slot transition. See
can take from six up to ten system clocks.
24.6.5.3.3
Channel number priority
If more than one channel of a priority level is requesting service, the lowest numbered channel is granted
service first. For example, if channels 0, 5, and 9 are all high-level channels requesting service during a
high time slot, channel 0 is granted service first. Continuing this example, if channel 0 requests service
again immediately after being serviced, it is not serviced again until channels 5 and 9 are serviced. This
scheme is implemented so that continuously-requesting low numbered channels do not take all the time on
the eTPU execution unit and leave no time for other channels.
The scheduler uses registers to keep track of which channels have been serviced and which require
servicing. Each channel has two register bit: a service request register (SRR) and a service grant register
(SGR). The SRR is set when a channel requests service. After the channel has been granted service, the
SGR is set and the SRR is cleared.
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Figure 24-67. Multiple time-slot sequences
Section 24.5.1.2, Time slot
MPC5644A Microcontroller Reference Manual, Rev. 6
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