NXP Semiconductors MPC5644A Reference Manual page 465

Microcontroller
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16.6.15.78.8 Pad Configuration Register 121 (SIU_PCR121)
SIU_BASE+0x132
0
1
R
0
0
W
Reset
0
0
= Unimplemented or Reserved
1
The OBE bit must be set to one for both ETPU_A[7] and GPIO[121] when configured as outputs.
2
The IBE bit must be set to one for both ETPU_A[7] and GPIO[121] when configured as inputs. When configured as
ETPU_A[19] or when ETPU_A[7] or GPIO[119] are configured as outputs, the IBE bit may be set to one to reflect
the pin state in the corresponding GPDI register.
3
The weak pull up/down selection at reset for the ETPU_A[7] pin is determined by the WKPCFG pin.
Signal
Primary
ETPU_A[7]
ALT1
ETPU_A[19]
ALT2
DSPI_B_SOUT_LVDS
ALT3
ETPU_A[6]
GPIO
GPIO[121]
1
In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE
bits. Set IBE = 1 for input or OBE = 1 for output.
2
For I/O functions that change direction dynamically, such as the external data bus, switching between input and
output is handled internally and the IBE and OBE bits are ignored.
16.6.15.78.9 Pad Configuration Register 122 (SIU_PCR122)
SIU_BASE+0x134
0
1
R
0
0
W
Reset
0
0
= Unimplemented or Reserved
1
The OBE bit must be set to one for both ETPU_A[8] and GPIO[122] when configured as outputs.
2
The IBE bit must be set to one for both ETPU_A[8] and GPIO[122] when configured as inputs. When configured as
ETPU_A[20] or when ETPU_A[8] or GPIO[122] are configured as outputs, the IBE bit may be set to one to reflect
the pin state in the corresponding GPDI register.
3
The weak pull up/down selection at reset for the ETPU_A[8] pin is determined by the WKPCFG pin.
Freescale Semiconductor
2
3
4
5
6
PA
OBE
0
0
0
0
0
Figure 16-107. Pad Configuration Register (SIU_PCR121)
Table 16-110. SIU_PCR121 PA values
Name
Module
eTPU
eTPU
DSPI
eTPU
SIU
2
3
4
5
6
0
PA
OBE
0
0
0
0
0
Figure 16-108. Pad Configuration Register (SIU_PCR122)
MPC5644A Microcontroller Reference Manual, Rev. 6
7
8
9
10
1
2
IBE
0
0
ODE
0
0
0
0
Description
eTPU channel
I/O
eTPU channel
O
LVDS output
O
eTPU channel
O
GPIO
I/O
7
8
9
10
1
2
IBE
0
0
ODE
0
0
0
0
System Integration Unit (SIU)
11
12
13
14
15
HYS
SRC
WPE
WPS
0
0
0
1
WKP
1,2
I/O
PA value
0b0001
0b0010
0b0100
0b1000
0b0000
11
12
13
14
15
HYS
SRC
WPE
WPS
0
0
0
1
WKP
3
3
465

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