NXP Semiconductors MPC5644A Reference Manual page 749

IPI
SkyBlue,
HOST
Green
INTERFACE
Lines
ENGINE
CONFIGURATION
IPI
Indigo
Line
TIME BASE
CONFIGURATION
CHANNEL
IPI
CONTROL
DarkBlue
Line
to NDEDI
DEBUG
INTERFACE
eTPU engines 1 and 2 are sometimes called eTPU 1 and eTPU 2 throughout this document.
24.2.1.1.1 Time bases
Two 24-bit counters TCR1 and TCR2 provide reference time bases for all match and input capture events.
Prescalers for both time bases are controlled by the Host CPU through bit fields in the eTPU engine
configuration registers. The eTPU is able to export/import time to/from TCR1 or TCR2 in accordance to
the Red Line bus specification.
The clock for each of TCR1 and TCR2 clock can be independently derived from the system clock or from
an external input via the TCRCLK clock pin. In addition, the TCR2 timebase can be derived from special
angle-clock hardware which enables implementing angle-based functions. This feature is added to support
advanced angle based engine control applications.
For further details refer to
Freescale Semiconductor
CONTROL SCHEDULER
MICROENGINE
FETCH and
DECODE
CONTROL
EXECUTION
UNIT
MDU
CONTROL
and DATA
SHARED
PARAMETER
RAM
(SPRAM)
Figure 24-2. eTPU engine block diagram
Section 24.5.6, Time Bases.
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Time Processing Unit (eTPU2)
Red Line Red Line
INTERFACE
SERVICE REQUESTS
TCR1
TCRCLK
TCR2/
PIN
ANGLE COUNT
CONTROL AND DATA
SHARED
CODE
MEMORY
(SCM)
TIMER
CHANNELS
CHANNEL 0
CHANNEL 1
IPI
Purple
Line
(PINS)
CHANNEL 31
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