NXP Semiconductors MPC5644A Reference Manual page 975

Since the definition of worse-case latency assumes a fully loaded running system, initialization threads are
not part of worst-case calculations. For the channel 5 example, the two PWM threads in
thus the two normal running threads, threads 2 and 3.
Figure 24-64 does not define which thread is thread 2 and which is thread 3. Since the worst-case latency
derived from the first-pass analysis is the worst case between any two threads (not counting initialization
threads), it is safe to say that the worst-case latency shown in
high time and the worst-case low time.
Notice in Figure 24-64 that worst-case latency is drawn from the end of the execution of the first PWM
thread to the end of the execution of the next PWM thread. It is drawn from end to end because the
microcode instructions that make up the threads control the channel hardware. To make sure that all the
microcode instructions needed to change the pin thread have been executed, it is necessary to include the
execution time of the second thread.
Thread information for each function is found in the programming notes for individual TPU functions.
Refer to Freescale Programming Note TPUPN00/D, Using the TPU Function Library and TPU Emulation
Mode, for a list of available programming notes. Similar documentation will we provided for the eTPU
new functions.
24.6.5.3 Priority scheme details used in WCL analysis
The user assigns functions to channel numbers and gives each active channel a priority level of high,
middle, or low. The Scheduler uses the channel number and channel priority level to determine the order
in which to grant service.
The scheduler allocates time slots to specific priority levels of high, middle, or low. One function thread
is executed in each time slot. The length of a time slot varies according to the length of the executing
thread. When fully loaded, the scheduler always assigns time slots in a seven-slot sequence (see
Figure 24-66). After a seven-slot sequence is completed, another seven-slot sequence begins (see
Figure 24-67). Note that in eTPU, when no service request exists, the scheduler goes to thread 1, but WCL
calculation considers full load.
Freescale Semiconductor
H M H L H
Time Slots of
Varying Lengths
Figure 24-66. Time-slot sequence
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Time Processing Unit (eTPU2)
Figure 24-65 represents both the worst-case
Time Slot Transitions
(10 CPU Clock Cycle Each)
M H
Figure 24-64 are
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