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input bit for the CS[0]_GPIO[0] pin, and PDI213 is the pin data input bit for the WKPCFG_GPIO[213]
pin. Gaps exist in this memory space where the pin is not available in the package.
SIU_BASE + 0x800
0
1
R
0
0
W
Reset
0
0
16
17
R
0
0
W
Reset
0
0
= Unimplemented or Reserved
Figure 16-200. GPIO Pin Data In Register 0 – 3 (SIU_GPDI0 – SIU_GPDI3)
SIU_BASE + 0x8EA
0
1
R
0
0
W
Reset
0
0
16
17
R
0
0
W
Reset
0
0
= Unimplemented or Reserved
Figure 16-201. GPIO Pin Data In Register 230 – 232 (SIU_GPDI230 – SIU_GPDI232)
Field
Pin Data In. This bit stores the input state on the external GPIO pin associated with the register.
PDIx
0 Signal on pin is less than or equal to VIL.
1 Signal on pin is greater than or equal to VIH.
16.6.18 eQADC Trigger Input Select Register (SIU_ETISR
The eQADC Trigger Input Select Register (SIU_ETISR) selects the source for the eQADC trigger inputs.
The fields in this register operate in conjunction with the corresponding fields in the SIU_ISEL3 register.
Each field in the SIU_ETISR offers direct selection of three signals to be used as a trigger to a eQADC
CFIFO queue. The TSEL5 field is used to select the trigger source for eQADC CFIFO5, the TSEL4 field
selects the trigger source for eQADC CFIFO4, and so on. Additionally, each SIU_ETISR field offers
selection among a group of signals using the corresponding field in the SIU_ISEL3 register.
1. The ETISR is sometimes referred to as ISEL0
Freescale Semiconductor
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
0
0
0
0
0
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
0
0
0
0
0
Table 16-202. SIU_GPDIx_x field description
MPC5644A Microcontroller Reference Manual, Rev. 6
7
8
9
10
11
PDI
0
0
0
0
0
U
0
0
0
0
23
24
25
26
27
PDI
0
0
0
0
2
U
0
0
0
0
7
8
9
10
11
PDI
0
0
0
0
230
U
0
0
0
0
23
24
25
26
27
PDI
0
0
0
0
232
U
0
0
0
0
Description
System Integration Unit (SIU)
12
13
14
15
0
0
0
PDI
1
0
0
0
U
28
29
30
31
0
0
0
PDI
3
0
0
0
U
12
13
14
15
0
0
0
PDI
231
0
0
0
U
28
29
30
31
0
0
0
0
0
0
0
0
1
)
523
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