NXP Semiconductors MPC5644A Reference Manual page 779

Field
16-17 CDFC[1:0]—Channel Digital Filter Control
These bits select a digital filtering mode for the channels when configured as inputs for improved noise
immunity (refer to
programmable trade-off between signal latency and noise immunity (see
Digital Filter –
since it changes the behavior of the transition detection logic while executing its operation.
CDFC
00 TPU2/3 Two Sample Mode: Using the filter clock which is the system clock divided by
(2, 4, 8,.., 256) as a sampling clock (selected by FPSCK field in ETPU_ECR),
comparing two consecutive samples which agree with each other sets the input signal
state. This is the default reset state.
01 eTPU bypass mode: the input signal is taken unfiltered, also making the channels
work on T2/T4 timing mode
10 eTPU Three Sample Mode: Similar to the TPU2/3 two sample mode, but comparing
three consecutive samples which agree with each other sets the input signal state.
11 eTPU Continuous Mode: Signal need to be stable for the whole filter clock period. This
mode compares all the values at the rate of system clock (FCSS = 1) or system clock
divided by two (FCSS = 0), between two consecutive filter clock pulses. Signal needs
to be continuously stable for the entire period. If all the values agree with each other,
input signal state is updated.
1
See Section 24.5.5.7.2, T2/T4 Channel Timing
18 Reserved
19-23
ERBA—Engine Relative Base Address
This field value is concatenated with the AID instruction field in engine relative address mode to form the
SPRAM address (see
24 SPPDIS—Schedule Priority Passing Disable
SPPDIS is used to disable the priority passing mechanism of the microengine scheduler (see
Section 24.5.3.2.1, Primary scheme – priority among channels on different
1: Scheduler priority passing mechanism disabled.
0: Scheduler priority passing mechanism enabled.
Note: SPPDIS bit must not be changed while any channel is enabled.
25-26 Reserved
Freescale Semiconductor
Table 24-9. ETPU_ECR field description
Table 24-11). The eTPU has three digital filtering modes for the channels which provide
EDF). Changing CDFC during eTPU normal input channel operation is not recommended
Table 24-11. Channel digital filter control
Selected digital filter
1
.
Section , Engine relative addressing
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Time Processing Unit (eTPU2)
Description
Section 24.5.5.6, Enhanced
mode).
levels).
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