NXP Semiconductors MPC5644A Reference Manual page 238

Microcontroller
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Flash memory
12.3.2.10 Bus Interface Unit Configuration Register 2 (BIUCR2)
Offset: FLASH_REGS_BASE + 0x0024
0
1
R
LBCFG
W
Reset
1
1
16
17
R
1
1
W
Reset
1
1
Figure 12-12. Bus Interface Unit Configuration Register 2 (BIUCR2)
Field
LBCFG
Line Buffer Configuration
This field controls the configuration of all the line buffers in the PFLASH controller. The buffers can
be organized as a "pool" of available resources, or with a fixed partition between instruction and data
buffers.
In all cases, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the
group and the just-fetched entry then marked as most-recently-used. If the flash access is for the
next-sequential line, the buffer is not marked as most-recently-used until the given address produces
a buffer hit.
This field is initialized by hardware reset to the value contained in address 0x7e00 of the shadow
block of the flash array. An erased or unprogrammed flash sets this field to 0b11.
This field controls the configuration of both the 4 x 128 and 4 x 256 line buffers.
00: All four buffers are available for any flash access, that is, there is no partitioning of the buffers
based on the access type.
01: Reserved
10: The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches
and buffers 2 and 3 for data accesses.
11: The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and
buffer 3 for data accesses.
12.3.2.11 User Test 0 (UT0) Register
The User Test 0 (UT0) Register provides a means to control UTest. The UTest mode gives the users of the
flash module the ability to perform test features on the flash. This register is only writable when the flash
is put into UTest mode by writing a passcode.
238
2
3
4
5
6
1
1
1
1
1
1
1
1
1
1
18
19
20
21
22
1
1
1
1
1
1
1
1
1
1
Table 12-14. BIUCR2 field descriptions
MPC5644A Microcontroller Reference Manual, Rev. 6
7
8
9
10
11
1
1
1
1
1
1
1
1
1
1
23
24
25
26
27
1
1
1
1
1
1
1
1
1
1
Description
Access: User read/write
12
13
14
15
1
1
1
1
1
1
1
1
28
29
30
31
1
1
1
1
1
1
1
1
Freescale Semiconductor

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